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Bo Shenf7fa2f32012-07-05 17:21:46 +00001/*
2 * Copyright (C) 2012 Atmel Corporation
3 *
4 * Configuation settings for the AT91SAM9X5EK board.
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Bo Shenf7fa2f32012-07-05 17:21:46 +00007 */
8
9#ifndef __CONFIG_H__
10#define __CONFIG_H__
11
12#include <asm/hardware.h>
13
Bo Shen77461a62013-08-13 14:50:49 +080014#define CONFIG_SYS_TEXT_BASE 0x26f00000
15
Bo Shenf7fa2f32012-07-05 17:21:46 +000016/* ARM asynchronous clock */
17#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
18#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
Bo Shenf7fa2f32012-07-05 17:21:46 +000019
20#define CONFIG_AT91SAM9X5EK
Bo Shenf7fa2f32012-07-05 17:21:46 +000021
Bo Shenf7fa2f32012-07-05 17:21:46 +000022#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
23#define CONFIG_SETUP_MEMORY_TAGS
24#define CONFIG_INITRD_TAG
25#define CONFIG_SKIP_LOWLEVEL_INIT
Bo Shenf7fa2f32012-07-05 17:21:46 +000026
27/* general purpose I/O */
28#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
Bo Shenf7fa2f32012-07-05 17:21:46 +000029
30/* LCD */
Bo Shenf7fa2f32012-07-05 17:21:46 +000031#define LCD_BPP LCD_COLOR16
32#define LCD_OUTPUT_BPP 24
33#define CONFIG_LCD_LOGO
Bo Shenf7fa2f32012-07-05 17:21:46 +000034#define CONFIG_LCD_INFO
35#define CONFIG_LCD_INFO_BELOW_LOGO
Bo Shenf7fa2f32012-07-05 17:21:46 +000036#define CONFIG_ATMEL_HLCD
37#define CONFIG_ATMEL_LCD_RGB565
Bo Shenf7fa2f32012-07-05 17:21:46 +000038
Bo Shenf7fa2f32012-07-05 17:21:46 +000039
40/*
41 * BOOTP options
42 */
43#define CONFIG_BOOTP_BOOTFILESIZE
44#define CONFIG_BOOTP_BOOTPATH
45#define CONFIG_BOOTP_GATEWAY
46#define CONFIG_BOOTP_HOSTNAME
47
48/*
49 * Command line configuration.
50 */
Bo Shenf7fa2f32012-07-05 17:21:46 +000051#define CONFIG_CMD_NAND
Richard Genoudb030e732012-11-29 23:18:34 +000052
53/*
Tom Rini8850c5d2017-05-12 22:33:27 -040054 * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
Richard Genoudb030e732012-11-29 23:18:34 +000055 * NB: in this case, USB 1.1 devices won't be recognized.
56 */
57
Bo Shenf7fa2f32012-07-05 17:21:46 +000058/* SDRAM */
59#define CONFIG_NR_DRAM_BANKS 1
60#define CONFIG_SYS_SDRAM_BASE 0x20000000
61#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
62
63#define CONFIG_SYS_INIT_SP_ADDR \
Wenyou Yang74631b62017-04-18 14:51:54 +080064 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Bo Shenf7fa2f32012-07-05 17:21:46 +000065
66/* DataFlash */
Bo Shen1d7442e2012-08-19 20:32:24 +000067#ifdef CONFIG_CMD_SF
Bo Shen1d7442e2012-08-19 20:32:24 +000068#define CONFIG_SF_DEFAULT_SPEED 30000000
Bo Shenf7fa2f32012-07-05 17:21:46 +000069#endif
70
Bo Shenf7fa2f32012-07-05 17:21:46 +000071/* NAND flash */
72#ifdef CONFIG_CMD_NAND
73#define CONFIG_NAND_ATMEL
74#define CONFIG_SYS_MAX_NAND_DEVICE 1
75#define CONFIG_SYS_NAND_BASE 0x40000000
76#define CONFIG_SYS_NAND_DBW_8 1
77/* our ALE is AD21 */
78#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
79/* our CLE is AD22 */
80#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
81#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
82#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
83
Wu, Joshdf953212012-08-23 00:05:38 +000084/* PMECC & PMERRLOC */
85#define CONFIG_ATMEL_NAND_HWECC 1
86#define CONFIG_ATMEL_NAND_HW_PMECC 1
87#define CONFIG_PMECC_CAP 2
88#define CONFIG_PMECC_SECTOR_SIZE 512
Wu, Joshdf953212012-08-23 00:05:38 +000089
Bo Shence76f0a2013-06-26 10:48:53 +080090#define CONFIG_CMD_NAND_TRIMFFS
91
Bo Shenf7fa2f32012-07-05 17:21:46 +000092#define CONFIG_MTD_DEVICE
Bo Shenf7fa2f32012-07-05 17:21:46 +000093#define CONFIG_MTD_PARTITIONS
Bo Shenf7fa2f32012-07-05 17:21:46 +000094#endif
95
Richard Genoudb030e732012-11-29 23:18:34 +000096/* USB */
97#ifdef CONFIG_CMD_USB
Tom Rini8850c5d2017-05-12 22:33:27 -040098#ifndef CONFIG_USB_EHCI_HCD
Bo Shendcd2f1a2013-10-21 16:14:00 +080099#define CONFIG_USB_ATMEL
100#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
Richard Genoudb030e732012-11-29 23:18:34 +0000101#define CONFIG_USB_OHCI_NEW
102#define CONFIG_SYS_USB_OHCI_CPU_INIT
103#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
104#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5"
105#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
106#endif
Richard Genoudb030e732012-11-29 23:18:34 +0000107#endif
108
Bo Shenf7fa2f32012-07-05 17:21:46 +0000109#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
110
111#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
112#define CONFIG_SYS_MEMTEST_END 0x26e00000
113
114#ifdef CONFIG_SYS_USE_NANDFLASH
115/* bootstrap + u-boot + env + linux in nandflash */
Wenyou Yang74631b62017-04-18 14:51:54 +0800116#define CONFIG_ENV_OFFSET 0x120000
Bo Shenf7fa2f32012-07-05 17:21:46 +0000117#define CONFIG_ENV_OFFSET_REDUND 0x100000
118#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
119#define CONFIG_BOOTCOMMAND "nand read " \
120 "0x22000000 0x200000 0x300000; " \
121 "bootm 0x22000000"
Wu, Joshb7e31292012-11-02 00:17:27 +0000122#elif defined(CONFIG_SYS_USE_SPIFLASH)
Bo Shen1d7442e2012-08-19 20:32:24 +0000123/* bootstrap + u-boot + env + linux in spi flash */
Bo Shen1d7442e2012-08-19 20:32:24 +0000124#define CONFIG_ENV_OFFSET 0x5000
125#define CONFIG_ENV_SIZE 0x3000
126#define CONFIG_ENV_SECT_SIZE 0x1000
127#define CONFIG_ENV_SPI_MAX_HZ 30000000
128#define CONFIG_BOOTCOMMAND "sf probe 0; " \
129 "sf read 0x22000000 0x100000 0x300000; " \
130 "bootm 0x22000000"
Bo Shen961ffc72012-12-06 21:37:04 +0000131#elif defined(CONFIG_SYS_USE_DATAFLASH)
132/* bootstrap + u-boot + env + linux in data flash */
Bo Shen961ffc72012-12-06 21:37:04 +0000133#define CONFIG_ENV_OFFSET 0x4200
134#define CONFIG_ENV_SIZE 0x4200
135#define CONFIG_ENV_SECT_SIZE 0x210
136#define CONFIG_ENV_SPI_MAX_HZ 30000000
137#define CONFIG_BOOTCOMMAND "sf probe 0; " \
138 "sf read 0x22000000 0x84000 0x294000; " \
139 "bootm 0x22000000"
Wu, Joshb7e31292012-11-02 00:17:27 +0000140#else /* CONFIG_SYS_USE_MMC */
141/* bootstrap + u-boot + env + linux in mmc */
Wu, Josh26961772015-01-20 10:33:33 +0800142#define FAT_ENV_INTERFACE "mmc"
143#define FAT_ENV_FILE "uboot.env"
144#define FAT_ENV_DEVICE_AND_PART "0"
145#define CONFIG_ENV_SIZE 0x4000
Bo Shenf7fa2f32012-07-05 17:21:46 +0000146#endif
147
Wu, Joshb7e31292012-11-02 00:17:27 +0000148#ifdef CONFIG_SYS_USE_MMC
149#define CONFIG_BOOTARGS "mem=128M console=ttyS0,115200 " \
150 "mtdparts=atmel_nand:" \
151 "8M(bootstrap/uboot/kernel)ro,-(rootfs) " \
152 "root=/dev/mmcblk0p2 " \
153 "rw rootfstype=ext4 rootwait"
154#else
Bo Shen0c58cfa2013-02-20 00:16:25 +0000155#define CONFIG_BOOTARGS \
156 "console=ttyS0,115200 earlyprintk " \
157 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
158 "256k(env),256k(env_redundant),256k(spare)," \
159 "512k(dtb),6M(kernel)ro,-(rootfs) " \
160 "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw"
Wu, Joshb7e31292012-11-02 00:17:27 +0000161#endif
Bo Shenf7fa2f32012-07-05 17:21:46 +0000162
Bo Shenf7fa2f32012-07-05 17:21:46 +0000163#define CONFIG_SYS_CBSIZE 256
164#define CONFIG_SYS_MAXARGS 16
Bo Shenf7fa2f32012-07-05 17:21:46 +0000165#define CONFIG_SYS_LONGHELP
166#define CONFIG_CMDLINE_EDITING
167#define CONFIG_AUTO_COMPLETE
Bo Shenf7fa2f32012-07-05 17:21:46 +0000168
169/*
170 * Size of malloc() pool
171 */
172#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
173
Bo Shend85e8912015-03-27 14:23:35 +0800174/* SPL */
175#define CONFIG_SPL_FRAMEWORK
176#define CONFIG_SPL_TEXT_BASE 0x300000
177#define CONFIG_SPL_MAX_SIZE 0x6000
178#define CONFIG_SPL_STACK 0x308000
179
180#define CONFIG_SPL_BSS_START_ADDR 0x20000000
181#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
182#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
183#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
184
Bo Shend85e8912015-03-27 14:23:35 +0800185#define CONFIG_SYS_MONITOR_LEN (512 << 10)
186
187#define CONFIG_SYS_MASTER_CLOCK 132096000
188#define CONFIG_SYS_AT91_PLLA 0x20c73f03
189#define CONFIG_SYS_MCKR 0x1301
190#define CONFIG_SYS_MCKR_CSS 0x1302
191
Bo Shend85e8912015-03-27 14:23:35 +0800192#ifdef CONFIG_SYS_USE_MMC
193#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
Bo Shend85e8912015-03-27 14:23:35 +0800194#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
195#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Bo Shend85e8912015-03-27 14:23:35 +0800196
197#elif CONFIG_SYS_USE_NANDFLASH
Bo Shend85e8912015-03-27 14:23:35 +0800198#define CONFIG_SPL_NAND_DRIVERS
199#define CONFIG_SPL_NAND_BASE
200#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
201#define CONFIG_SYS_NAND_5_ADDR_CYCLE
202#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
203#define CONFIG_SYS_NAND_PAGE_COUNT 64
204#define CONFIG_SYS_NAND_OOBSIZE 64
205#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
206#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
207#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
208
209#elif CONFIG_SYS_USE_SPIFLASH
Bo Shend85e8912015-03-27 14:23:35 +0800210#define CONFIG_SPL_SPI_LOAD
211#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
212
213#endif
214
Bo Shenf7fa2f32012-07-05 17:21:46 +0000215#endif