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Macpaul Lin6cb144b2010-10-19 17:05:51 +08001/*
2 * Copyright (C) 2011 Andes Technology Corporation
3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Macpaul Lin6cb144b2010-10-19 17:05:51 +08007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Masahiro Yamada7e3f94e2015-07-15 20:59:28 +090012#include <asm/arch-ag101/ag101.h>
Macpaul Lin6cb144b2010-10-19 17:05:51 +080013
14/*
15 * CPU and Board Configuration Options
16 */
17#define CONFIG_ADP_AG101P
18
19#define CONFIG_USE_INTERRUPT
20
21#define CONFIG_SKIP_LOWLEVEL_INIT
22
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +080023#define CONFIG_SYS_GENERIC_GLOBAL_DATA
24
ken kuoe3c58b02013-06-08 11:14:12 +080025/*
26 * Definitions related to passing arguments to kernel.
27 */
28#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
29#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
30#define CONFIG_INITRD_TAG /* send initrd params */
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +080031#define CONFIG_NEEDS_MANUAL_RELOC
ken kuoe3c58b02013-06-08 11:14:12 +080032
Macpaul Lin6cb144b2010-10-19 17:05:51 +080033#ifndef CONFIG_SKIP_LOWLEVEL_INIT
34#define CONFIG_MEM_REMAP
35#endif
36
37#ifdef CONFIG_SKIP_LOWLEVEL_INIT
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +080038#define CONFIG_SYS_TEXT_BASE 0x00500000
39#else
40#ifdef CONFIG_MEM_REMAP
41#define CONFIG_SYS_TEXT_BASE 0x80000000
Macpaul Lin6cb144b2010-10-19 17:05:51 +080042#else
43#define CONFIG_SYS_TEXT_BASE 0x00000000
44#endif
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +080045#endif
Macpaul Lin6cb144b2010-10-19 17:05:51 +080046
47/*
48 * Timer
49 */
Macpaul Lin6cb144b2010-10-19 17:05:51 +080050#define CONFIG_SYS_CLK_FREQ 39062500
51#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
52
53/*
54 * Use Externel CLOCK or PCLK
55 */
56#undef CONFIG_FTRTC010_EXTCLK
57
58#ifndef CONFIG_FTRTC010_EXTCLK
59#define CONFIG_FTRTC010_PCLK
60#endif
61
62#ifdef CONFIG_FTRTC010_EXTCLK
63#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
64#else
65#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
66#endif
67
68#define TIMER_LOAD_VAL 0xffffffff
69
70/*
71 * Real Time Clock
72 */
73#define CONFIG_RTC_FTRTC010
74
75/*
76 * Real Time Clock Divider
77 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
78 */
79#define OSC_5MHZ (5*1000000)
80#define OSC_CLK (4*OSC_5MHZ)
81#define RTC_DIV_COUNT (0.5) /* Why?? */
82
83/*
84 * Serial console configuration
85 */
86
87/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
88#define CONFIG_BAUDRATE 38400
89#define CONFIG_CONS_INDEX 1
Macpaul Lin6cb144b2010-10-19 17:05:51 +080090#define CONFIG_SYS_NS16550_SERIAL
91#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
92#define CONFIG_SYS_NS16550_REG_SIZE -4
93#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
94
Macpaul Lin6cb144b2010-10-19 17:05:51 +080095/*
96 * Ethernet
97 */
98#define CONFIG_FTMAC100
99
100#define CONFIG_BOOTDELAY 3
101
102/*
103 * SD (MMC) controller
104 */
105#define CONFIG_MMC
106#define CONFIG_CMD_MMC
107#define CONFIG_GENERIC_MMC
108#define CONFIG_DOS_PARTITION
109#define CONFIG_FTSDC010
110#define CONFIG_FTSDC010_NUMBER 1
ken kuo61ccf082013-06-08 11:14:11 +0800111#define CONFIG_FTSDC010_SDIO
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800112#define CONFIG_CMD_FAT
ken kuo61ccf082013-06-08 11:14:11 +0800113#define CONFIG_CMD_EXT2
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800114
115/*
116 * Command line configuration.
117 */
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800118#define CONFIG_CMD_CACHE
119#define CONFIG_CMD_DATE
120#define CONFIG_CMD_PING
121
122/*
123 * Miscellaneous configurable options
124 */
125#define CONFIG_SYS_LONGHELP /* undef to save memory */
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800126#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
127
128/* Print Buffer Size */
129#define CONFIG_SYS_PBSIZE \
130 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
131
132/* max number of command args */
133#define CONFIG_SYS_MAXARGS 16
134
135/* Boot Argument Buffer Size */
136#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
137
138/*
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800139 * Size of malloc() pool
140 */
141/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
142#define CONFIG_SYS_MALLOC_LEN (512 << 10)
143
144/*
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800145 * AHB Controller configuration
146 */
147#define CONFIG_FTAHBC020S
148
149#ifdef CONFIG_FTAHBC020S
150#include <faraday/ftahbc020s.h>
151
152/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
153#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
154
155/*
156 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
157 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
158 * in C language.
159 */
160#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
161 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
162 FTAHBC020S_SLAVE_BSR_SIZE(0xb))
163#endif
164
165/*
166 * Watchdog
167 */
168#define CONFIG_FTWDT010_WATCHDOG
169
170/*
171 * PMU Power controller configuration
172 */
173#define CONFIG_PMU
174#define CONFIG_FTPMU010_POWER
175
176#ifdef CONFIG_FTPMU010_POWER
177#include <faraday/ftpmu010.h>
178#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E
179#define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \
180 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \
181 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \
182 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
183 FTPMU010_SDRAMHTC_CKE_DCSR | \
184 FTPMU010_SDRAMHTC_DQM_DCSR | \
185 FTPMU010_SDRAMHTC_SDCLK_DCSR)
186#endif
187
188/*
189 * SDRAM controller configuration
190 */
191#define CONFIG_FTSDMC021
192
193#ifdef CONFIG_FTSDMC021
194#include <faraday/ftsdmc021.h>
195
196#define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \
197 FTSDMC021_TP1_TRP(1) | \
198 FTSDMC021_TP1_TRCD(1) | \
199 FTSDMC021_TP1_TRF(3) | \
200 FTSDMC021_TP1_TWR(1) | \
201 FTSDMC021_TP1_TCL(2))
202
203#define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \
204 FTSDMC021_TP2_INI_REFT(8) | \
205 FTSDMC021_TP2_REF_INTV(0x180))
206
207/*
208 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
209 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
210 * C language.
211 */
212#define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \
213 FTSDMC021_CR1_DSZ(3) | \
214 FTSDMC021_CR1_MBW(2) | \
215 FTSDMC021_CR1_BNKSIZE(6))
216
217#define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \
218 FTSDMC021_CR2_IREF | \
219 FTSDMC021_CR2_ISMR)
220
221#define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
222#define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \
223 CONFIG_SYS_FTSDMC021_BANK0_BASE)
224
ken kuo3c016702013-06-08 11:14:09 +0800225#define CONFIG_SYS_FTSDMC021_BANK1_BASE \
226 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
227#define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \
228 CONFIG_SYS_FTSDMC021_BANK1_BASE)
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800229#endif
230
231/*
232 * Physical Memory Map
233 */
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +0800234#ifdef CONFIG_SKIP_LOWLEVEL_INIT
235#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
236#else
237#ifdef CONFIG_MEM_REMAP
238#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
239#else
240#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800241#endif
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800242#endif
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +0800243
ken kuo3c016702013-06-08 11:14:09 +0800244#define PHYS_SDRAM_1 \
245 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800246
ken kuo3c016702013-06-08 11:14:09 +0800247#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +0800248
249#ifdef CONFIG_SKIP_LOWLEVEL_INIT
250#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
251#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
252#else
253#ifdef CONFIG_MEM_REMAP
254#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
255#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
256#else
257#define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */
258#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
259#endif
260#endif
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800261
262#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
263
264#ifdef CONFIG_MEM_REMAP
265#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
266 GENERATED_GBL_DATA_SIZE)
267#else
268#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
269 GENERATED_GBL_DATA_SIZE)
270#endif /* CONFIG_MEM_REMAP */
271
272/*
273 * Load address and memory test area should agree with
274 * arch/nds32/config.mk. Be careful not to overwrite U-boot itself.
275 */
276#define CONFIG_SYS_LOAD_ADDR 0x300000
277
278/* memtest works on 63 MB in DRAM */
279#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
280#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
281
282/*
283 * Static memory controller configuration
284 */
285#define CONFIG_FTSMC020
286
287#ifdef CONFIG_FTSMC020
288#include <faraday/ftsmc020.h>
289
290#define CONFIG_SYS_FTSMC020_CONFIGS { \
291 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
292 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
293}
294
295#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
296#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
297 FTSMC020_BANK_SIZE_32M | \
298 FTSMC020_BANK_MBW_32)
299
300#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
301 FTSMC020_TPR_AST(1) | \
302 FTSMC020_TPR_CTW(1) | \
303 FTSMC020_TPR_ATI(1) | \
304 FTSMC020_TPR_AT2(1) | \
305 FTSMC020_TPR_WTC(1) | \
306 FTSMC020_TPR_AHT(1) | \
307 FTSMC020_TPR_TRNA(1))
308#endif
309
310/*
311 * FLASH on ADP_AG101P is connected to BANK0
312 * Just disalbe the other BANK to avoid detection error.
313 */
314#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
315 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
316 FTSMC020_BANK_SIZE_32M | \
317 FTSMC020_BANK_MBW_32)
318
319#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
320 FTSMC020_TPR_CTW(3) | \
321 FTSMC020_TPR_ATI(0xf) | \
322 FTSMC020_TPR_AT2(3) | \
323 FTSMC020_TPR_WTC(3) | \
324 FTSMC020_TPR_AHT(3) | \
325 FTSMC020_TPR_TRNA(0xf))
326
327#define FTSMC020_BANK1_CONFIG (0x00)
328#define FTSMC020_BANK1_TIMING (0x00)
329#endif /* CONFIG_FTSMC020 */
330
331/*
332 * FLASH and environment organization
333 */
334/* use CFI framework */
335#define CONFIG_SYS_FLASH_CFI
336#define CONFIG_FLASH_CFI_DRIVER
337
338#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
339#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +0800340#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800341
342/* support JEDEC */
343
344/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
345#ifdef CONFIG_SKIP_LOWLEVEL_INIT
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +0800346#define PHYS_FLASH_1 0x80000000 /* BANK 0 */
347#else
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800348#ifdef CONFIG_MEM_REMAP
349#define PHYS_FLASH_1 0x80000000 /* BANK 0 */
350#else
351#define PHYS_FLASH_1 0x00000000 /* BANK 0 */
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +0800352#endif
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800353#endif /* CONFIG_MEM_REMAP */
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800354
355#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
356#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
357#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
358
359#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
360#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
361
362/* max number of memory banks */
363/*
364 * There are 4 banks supported for this Controller,
365 * but we have only 1 bank connected to flash on board
366 */
367#define CONFIG_SYS_MAX_FLASH_BANKS 1
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +0800368#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800369
370/* max number of sectors on one chip */
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +0800371#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800372#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +0800373#define CONFIG_SYS_MAX_FLASH_SECT 512
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800374
375/* environments */
376#define CONFIG_ENV_IS_IN_FLASH
377#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000)
378#define CONFIG_ENV_SIZE 8192
379#define CONFIG_ENV_OVERWRITE
380
381#endif /* __CONFIG_H */