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wdenk3bbc8992003-12-07 22:27:15 +00001/*
2 * (C) Copyright 2003
3 * MuLogic B.V.
4 *
5 * (C) Copyright 2002
6 * Simple Network Magic Corporation, dnevil@snmc.com
7 *
8 * (C) Copyright 2000
9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#include <common.h>
31#include <asm/u-boot.h>
32#include <commproc.h>
33#include "mpc8xx.h"
34
35/* ------------------------------------------------------------------------- */
36
37static long int dram_size (long int, long int *, long int);
38
39/* ------------------------------------------------------------------------- */
40
41const uint sdram_table[] =
42{
43 /*
44 * Single Read. (Offset 0 in UPMA RAM)
45 */
46 0x0f07cc04, 0x00adcc04, 0x00a74c00, 0x00bfcc04,
47 0x1fffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
48 /*
49 * Burst Read. (Offset 8 in UPMA RAM)
50 */
51 0x0ff7fc04, 0x0ffffc04, 0x00bdfc04, 0x00fffc00,
52 0x00fffc00, 0x00fffc00, 0x0ff77c00, 0x1ffffc05,
53 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05,
54 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05,
55 /*
56 * Single Write. (Offset 18 in UPMA RAM)
57 */
58 0x0f07cc04, 0x0fafcc00, 0x01ad0c04, 0x1ff74c07,
59 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
60 /*
61 * Burst Write. (Offset 20 in UPMA RAM)
62 */
63 0x0ff7fc04, 0x0ffffc00, 0x00bd7c00, 0x00fffc00,
64 0x00fffc00, 0x00fffc00, 0x0ffffc04, 0x0ff77c04,
65 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05,
66 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05,
67 /*
68 * Refresh (Offset 30 in UPMA RAM)
69 */
70 0xffffcc04, 0x1ff5cc84, 0xffffcc04, 0xffffcc04,
71 0xffffcc84, 0xffffcc05, 0xffffcc04, 0xffffcc04,
72 0xffffcc04, 0xffffcc04, 0xffffcc04, 0xffffcc04,
73 /*
74 * Exception. (Offset 3c in UPMA RAM)
75 */
76 0x1ff74c04, 0xffffcc07, 0xffffaa34, 0x1fb54a37
77};
78
79/* ------------------------------------------------------------------------- */
80
81
82/*
83 * Check Board Identity:
84 *
85 * Test ID string (QS850, QS823, ...)
86 *
87 * Always return 1
88 */
Wolfgang Denk45b16d22008-07-14 22:38:42 +020089#if defined(CONFIG_QS850)
90#define BOARD_IDENTITY "QS850"
91#elif defined(CONFIG_QS823)
92#define BOARD_IDENTITY "QS823"
93#else
94#define BOARD_IDENTITY "QS???"
95#endif
wdenk3bbc8992003-12-07 22:27:15 +000096
97int checkboard (void)
98{
Wolfgang Denk77ddac92005-10-13 16:45:02 +020099 char *s, *e;
100 char buf[64];
wdenk3bbc8992003-12-07 22:27:15 +0000101 int i;
102
Wolfgang Denkcdb74972010-07-24 21:55:43 +0200103 i = getenv_f("serial#", buf, sizeof(buf));
wdenk3bbc8992003-12-07 22:27:15 +0000104 s = (i>0) ? buf : NULL;
105
Wolfgang Denk45b16d22008-07-14 22:38:42 +0200106 if (!s || strncmp(s, BOARD_IDENTITY, 5)) {
107 puts ("### No HW ID - assuming " BOARD_IDENTITY);
wdenk3bbc8992003-12-07 22:27:15 +0000108 } else {
109 for (e=s; *e; ++e) {
110 if (*e == ' ')
111 break;
112 }
113
114 for ( ; s<e; ++s) {
115 putc (*s);
116 }
117 }
118 putc ('\n');
119
120 return (0);
121}
122
123/* ------------------------------------------------------------------------- */
124/* SDRAM Mode Register Definitions */
125
126/* Set SDRAM Burst Length to 4 (010) */
127/* See Motorola MPC850 User Manual, Page 13-14 */
128#define SDRAM_BURST_LENGTH (2)
129
130/* Set Wrap Type to Sequential (0) */
131/* See Motorola MPC850 User Manual, Page 13-14 */
132#define SDRAM_WRAP_TYPE (0 << 3)
133
134/* Set /CAS Latentcy to 2 clocks */
135#define SDRAM_CAS_LATENTCY (2 << 4)
136
137/* The Mode Register value must be shifted left by 2, since it is */
138/* placed on the address bus, and the 2 LSBs are ignored for 32-bit accesses */
139#define SDRAM_MODE_REG ((SDRAM_BURST_LENGTH|SDRAM_WRAP_TYPE|SDRAM_CAS_LATENTCY) << 2)
140
141#define UPMA_RUN(loops,index) (0x80002000 + (loops<<8) + index)
142
143/* Please note a value of zero = 16 loops */
144#define REFRESH_INIT_LOOPS (0)
145
146
Becky Bruce9973e3c2008-06-09 16:03:40 -0500147phys_size_t initdram (int board_type)
wdenk3bbc8992003-12-07 22:27:15 +0000148{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
wdenk3bbc8992003-12-07 22:27:15 +0000150 volatile memctl8xx_t *memctl = &immap->im_memctl;
151 long int size;
152
153 upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
154
155 /*
156 * Prescaler for refresh
157 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
wdenk3bbc8992003-12-07 22:27:15 +0000159
160 /*
161 * Map controller bank 1 to the SDRAM address
162 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163 memctl->memc_or1 = CONFIG_SYS_OR1;
164 memctl->memc_br1 = CONFIG_SYS_BR1;
wdenk3bbc8992003-12-07 22:27:15 +0000165 udelay(1000);
166
167 /* perform SDRAM initialization sequence */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168 memctl->memc_mamr = CONFIG_SYS_16M_MAMR;
wdenk3bbc8992003-12-07 22:27:15 +0000169 udelay(100);
170
171 /* Program the SDRAM's Mode Register */
172 memctl->memc_mar = SDRAM_MODE_REG;
173
174 /* Run the Prechard Pattern at 0x3C */
175 memctl->memc_mcr = UPMA_RUN(1,0x3c);
176 udelay(1);
177
178 /* Run the Refresh program residing at MAD index 0x30 */
179 /* This contains the CBR Refresh command with a loop */
180 /* The SDRAM must be refreshed at least 2 times */
181 /* Please note a value of zero = 16 loops */
182 memctl->memc_mcr = UPMA_RUN(REFRESH_INIT_LOOPS,0x30);
183 udelay(1);
184
185 /* Run the Exception program residing at MAD index 0x3E */
186 /* This contains the Write Mode Register command */
187 /* The Write Mode Register command uses the value written to MAR */
188 memctl->memc_mcr = UPMA_RUN(1,0x3e);
189
190 udelay (1000);
191
192 /*
193 * Check for 32M SDRAM Memory Size
194 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195 size = dram_size(CONFIG_SYS_32M_MAMR|MAMR_PTAE,
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200196 (long *)SDRAM_BASE, SDRAM_32M_MAX_SIZE);
wdenk3bbc8992003-12-07 22:27:15 +0000197 udelay (1000);
198
199 /*
200 * Check for 16M SDRAM Memory Size
201 */
202 if (size != SDRAM_32M_MAX_SIZE) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203 size = dram_size(CONFIG_SYS_16M_MAMR|MAMR_PTAE,
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200204 (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
wdenk3bbc8992003-12-07 22:27:15 +0000205 udelay (1000);
206 }
207
208 udelay(10000);
209 return (size);
210}
211
212/* ------------------------------------------------------------------------- */
213
214/*
215 * Check memory range for valid RAM. A simple memory test determines
216 * the actually available RAM size between addresses `base' and
217 * `base + maxsize'. Some (not all) hardware errors are detected:
218 * - short between address lines
219 * - short between data lines
220 */
221
222static long int dram_size (long int mamr_value, long int *base, long int maxsize)
223{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
wdenk3bbc8992003-12-07 22:27:15 +0000225 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenk3bbc8992003-12-07 22:27:15 +0000226
227 memctl->memc_mamr = mamr_value;
228
wdenkc83bf6a2004-01-06 22:38:14 +0000229 return (get_ram_size(base, maxsize));
wdenk3bbc8992003-12-07 22:27:15 +0000230}