Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de> |
| 3 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Simon Glass | a8ba569 | 2014-10-01 19:57:27 -0600 | [diff] [blame] | 8 | #include <dm.h> |
| 9 | #include <errno.h> |
Stefano Babic | 4ec3d2a | 2010-08-18 10:22:42 +0200 | [diff] [blame] | 10 | #include <watchdog.h> |
Ilya Yanok | 47d19da | 2009-06-08 04:12:46 +0400 | [diff] [blame] | 11 | #include <asm/arch/imx-regs.h> |
| 12 | #include <asm/arch/clock.h> |
Masahiro Yamada | 86256b7 | 2014-10-24 12:41:19 +0900 | [diff] [blame] | 13 | #include <dm/platform_data/serial_mxc.h> |
Marek Vasut | a943472 | 2012-09-14 22:37:43 +0200 | [diff] [blame] | 14 | #include <serial.h> |
| 15 | #include <linux/compiler.h> |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 16 | |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 17 | /* UART Control Register Bit Fields.*/ |
| 18 | #define URXD_CHARRDY (1<<15) |
| 19 | #define URXD_ERR (1<<14) |
| 20 | #define URXD_OVRRUN (1<<13) |
| 21 | #define URXD_FRMERR (1<<12) |
| 22 | #define URXD_BRK (1<<11) |
| 23 | #define URXD_PRERR (1<<10) |
Juergen Kilb | d92ea21 | 2008-06-08 17:59:53 +0200 | [diff] [blame] | 24 | #define URXD_RX_DATA (0xFF) |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 25 | #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ |
| 26 | #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ |
| 27 | #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ |
| 28 | #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ |
| 29 | #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ |
| 30 | #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ |
| 31 | #define UCR1_IREN (1<<7) /* Infrared interface enable */ |
| 32 | #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ |
| 33 | #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ |
| 34 | #define UCR1_SNDBRK (1<<4) /* Send break */ |
| 35 | #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ |
| 36 | #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ |
| 37 | #define UCR1_DOZE (1<<1) /* Doze */ |
| 38 | #define UCR1_UARTEN (1<<0) /* UART enabled */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 39 | #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ |
| 40 | #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ |
| 41 | #define UCR2_CTSC (1<<13) /* CTS pin control */ |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 42 | #define UCR2_CTS (1<<12) /* Clear to send */ |
| 43 | #define UCR2_ESCEN (1<<11) /* Escape enable */ |
| 44 | #define UCR2_PREN (1<<8) /* Parity enable */ |
| 45 | #define UCR2_PROE (1<<7) /* Parity odd/even */ |
| 46 | #define UCR2_STPB (1<<6) /* Stop */ |
| 47 | #define UCR2_WS (1<<5) /* Word size */ |
| 48 | #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ |
| 49 | #define UCR2_TXEN (1<<2) /* Transmitter enabled */ |
| 50 | #define UCR2_RXEN (1<<1) /* Receiver enabled */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 51 | #define UCR2_SRST (1<<0) /* SW reset */ |
| 52 | #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 53 | #define UCR3_PARERREN (1<<12) /* Parity enable */ |
| 54 | #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ |
| 55 | #define UCR3_DSR (1<<10) /* Data set ready */ |
| 56 | #define UCR3_DCD (1<<9) /* Data carrier detect */ |
| 57 | #define UCR3_RI (1<<8) /* Ring indicator */ |
Eric Nelson | 3a56482 | 2014-05-14 16:58:03 -0700 | [diff] [blame] | 58 | #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 59 | #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ |
| 60 | #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ |
| 61 | #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 62 | #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ |
| 63 | #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ |
| 64 | #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ |
| 65 | #define UCR3_BPEN (1<<0) /* Preset registers enable */ |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 66 | #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 67 | #define UCR4_INVR (1<<9) /* Inverted infrared reception */ |
| 68 | #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ |
| 69 | #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ |
| 70 | #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ |
| 71 | #define UCR4_IRSC (1<<5) /* IR special case */ |
| 72 | #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ |
| 73 | #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ |
| 74 | #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ |
| 75 | #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 76 | #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ |
| 77 | #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ |
Maximilian Schwerin | 434afa8 | 2015-11-25 14:08:00 +0100 | [diff] [blame] | 78 | #define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */ |
Stefan Agner | 83fd908 | 2016-07-13 00:25:35 -0700 | [diff] [blame] | 79 | #define UFCR_DCEDTE (1<<6) /* DTE mode select */ |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 80 | #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ |
| 81 | #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 82 | #define USR1_RTSS (1<<14) /* RTS pin status */ |
| 83 | #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ |
| 84 | #define USR1_RTSD (1<<12) /* RTS delta */ |
| 85 | #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 86 | #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ |
| 87 | #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ |
| 88 | #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 89 | #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 90 | #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 91 | #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ |
| 92 | #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ |
| 93 | #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ |
| 94 | #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ |
| 95 | #define USR2_IDLE (1<<12) /* Idle condition */ |
| 96 | #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ |
| 97 | #define USR2_WAKE (1<<7) /* Wake */ |
| 98 | #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ |
| 99 | #define USR2_TXDC (1<<3) /* Transmitter complete */ |
| 100 | #define USR2_BRCD (1<<2) /* Break condition */ |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 101 | #define USR2_ORE (1<<1) /* Overrun error */ |
| 102 | #define USR2_RDR (1<<0) /* Recv data ready */ |
| 103 | #define UTS_FRCPERR (1<<13) /* Force parity error */ |
| 104 | #define UTS_LOOP (1<<12) /* Loop tx and rx */ |
| 105 | #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ |
| 106 | #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 107 | #define UTS_TXFULL (1<<4) /* TxFIFO full */ |
| 108 | #define UTS_RXFULL (1<<3) /* RxFIFO full */ |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 109 | #define UTS_SOFTRST (1<<0) /* Software reset */ |
| 110 | |
Stefan Agner | a99546a | 2016-10-05 15:27:03 -0700 | [diff] [blame] | 111 | DECLARE_GLOBAL_DATA_PTR; |
| 112 | |
Simon Glass | a8ba569 | 2014-10-01 19:57:27 -0600 | [diff] [blame] | 113 | #ifndef CONFIG_DM_SERIAL |
| 114 | |
| 115 | #ifndef CONFIG_MXC_UART_BASE |
| 116 | #error "define CONFIG_MXC_UART_BASE to use the MXC UART driver" |
| 117 | #endif |
| 118 | |
| 119 | #define UART_PHYS CONFIG_MXC_UART_BASE |
| 120 | |
| 121 | #define __REG(x) (*((volatile u32 *)(x))) |
| 122 | |
| 123 | /* Register definitions */ |
| 124 | #define URXD 0x0 /* Receiver Register */ |
| 125 | #define UTXD 0x40 /* Transmitter Register */ |
| 126 | #define UCR1 0x80 /* Control Register 1 */ |
| 127 | #define UCR2 0x84 /* Control Register 2 */ |
| 128 | #define UCR3 0x88 /* Control Register 3 */ |
| 129 | #define UCR4 0x8c /* Control Register 4 */ |
| 130 | #define UFCR 0x90 /* FIFO Control Register */ |
| 131 | #define USR1 0x94 /* Status Register 1 */ |
| 132 | #define USR2 0x98 /* Status Register 2 */ |
| 133 | #define UESC 0x9c /* Escape Character Register */ |
| 134 | #define UTIM 0xa0 /* Escape Timer Register */ |
| 135 | #define UBIR 0xa4 /* BRM Incremental Register */ |
| 136 | #define UBMR 0xa8 /* BRM Modulator Register */ |
| 137 | #define UBRC 0xac /* Baud Rate Count Register */ |
| 138 | #define UTS 0xb4 /* UART Test Register (mx31) */ |
| 139 | |
Maximilian Schwerin | 434afa8 | 2015-11-25 14:08:00 +0100 | [diff] [blame] | 140 | #define TXTL 2 /* reset default */ |
| 141 | #define RXTL 1 /* reset default */ |
| 142 | #define RFDIV 4 /* divide input clock by 2 */ |
| 143 | |
Marek Vasut | a943472 | 2012-09-14 22:37:43 +0200 | [diff] [blame] | 144 | static void mxc_serial_setbrg(void) |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 145 | { |
Stefano Babic | 71d64c0 | 2010-01-20 18:20:19 +0100 | [diff] [blame] | 146 | u32 clk = imx_get_uartclk(); |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 147 | |
| 148 | if (!gd->baudrate) |
| 149 | gd->baudrate = CONFIG_BAUDRATE; |
| 150 | |
Maximilian Schwerin | 434afa8 | 2015-11-25 14:08:00 +0100 | [diff] [blame] | 151 | __REG(UART_PHYS + UFCR) = (RFDIV << UFCR_RFDIV_SHF) |
| 152 | | (TXTL << UFCR_TXTL_SHF) |
| 153 | | (RXTL << UFCR_RXTL_SHF); |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 154 | __REG(UART_PHYS + UBIR) = 0xf; |
| 155 | __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); |
| 156 | |
| 157 | } |
| 158 | |
Marek Vasut | a943472 | 2012-09-14 22:37:43 +0200 | [diff] [blame] | 159 | static int mxc_serial_getc(void) |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 160 | { |
Stefano Babic | 4ec3d2a | 2010-08-18 10:22:42 +0200 | [diff] [blame] | 161 | while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) |
| 162 | WATCHDOG_RESET(); |
Juergen Kilb | d92ea21 | 2008-06-08 17:59:53 +0200 | [diff] [blame] | 163 | return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */ |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 164 | } |
| 165 | |
Marek Vasut | a943472 | 2012-09-14 22:37:43 +0200 | [diff] [blame] | 166 | static void mxc_serial_putc(const char c) |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 167 | { |
Alison Wang | 055457e | 2016-03-02 11:00:37 +0800 | [diff] [blame] | 168 | /* If \n, also do \r */ |
| 169 | if (c == '\n') |
| 170 | serial_putc('\r'); |
| 171 | |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 172 | __REG(UART_PHYS + UTXD) = c; |
| 173 | |
| 174 | /* wait for transmitter to be ready */ |
Stefano Babic | 4ec3d2a | 2010-08-18 10:22:42 +0200 | [diff] [blame] | 175 | while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)) |
| 176 | WATCHDOG_RESET(); |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 177 | } |
| 178 | |
| 179 | /* |
| 180 | * Test whether a character is in the RX buffer |
| 181 | */ |
Marek Vasut | a943472 | 2012-09-14 22:37:43 +0200 | [diff] [blame] | 182 | static int mxc_serial_tstc(void) |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 183 | { |
| 184 | /* If receive fifo is empty, return false */ |
| 185 | if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) |
| 186 | return 0; |
| 187 | return 1; |
| 188 | } |
| 189 | |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 190 | /* |
| 191 | * Initialise the serial port with the given baudrate. The settings |
| 192 | * are always 8 data bits, no parity, 1 stop bit, no start bits. |
| 193 | * |
| 194 | */ |
Marek Vasut | a943472 | 2012-09-14 22:37:43 +0200 | [diff] [blame] | 195 | static int mxc_serial_init(void) |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 196 | { |
| 197 | __REG(UART_PHYS + UCR1) = 0x0; |
| 198 | __REG(UART_PHYS + UCR2) = 0x0; |
| 199 | |
| 200 | while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST)); |
| 201 | |
Eric Nelson | 3a56482 | 2014-05-14 16:58:03 -0700 | [diff] [blame] | 202 | __REG(UART_PHYS + UCR3) = 0x0704 | UCR3_ADNIMP; |
Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 203 | __REG(UART_PHYS + UCR4) = 0x8000; |
| 204 | __REG(UART_PHYS + UESC) = 0x002b; |
| 205 | __REG(UART_PHYS + UTIM) = 0x0; |
| 206 | |
| 207 | __REG(UART_PHYS + UTS) = 0x0; |
| 208 | |
| 209 | serial_setbrg(); |
| 210 | |
| 211 | __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST; |
| 212 | |
| 213 | __REG(UART_PHYS + UCR1) = UCR1_UARTEN; |
| 214 | |
| 215 | return 0; |
| 216 | } |
Marek Vasut | a943472 | 2012-09-14 22:37:43 +0200 | [diff] [blame] | 217 | |
Marek Vasut | a943472 | 2012-09-14 22:37:43 +0200 | [diff] [blame] | 218 | static struct serial_device mxc_serial_drv = { |
| 219 | .name = "mxc_serial", |
| 220 | .start = mxc_serial_init, |
| 221 | .stop = NULL, |
| 222 | .setbrg = mxc_serial_setbrg, |
| 223 | .putc = mxc_serial_putc, |
Marek Vasut | ec3fd68 | 2012-10-06 14:07:02 +0000 | [diff] [blame] | 224 | .puts = default_serial_puts, |
Marek Vasut | a943472 | 2012-09-14 22:37:43 +0200 | [diff] [blame] | 225 | .getc = mxc_serial_getc, |
| 226 | .tstc = mxc_serial_tstc, |
| 227 | }; |
| 228 | |
| 229 | void mxc_serial_initialize(void) |
| 230 | { |
| 231 | serial_register(&mxc_serial_drv); |
| 232 | } |
| 233 | |
| 234 | __weak struct serial_device *default_serial_console(void) |
| 235 | { |
| 236 | return &mxc_serial_drv; |
| 237 | } |
Simon Glass | a8ba569 | 2014-10-01 19:57:27 -0600 | [diff] [blame] | 238 | #endif |
| 239 | |
| 240 | #ifdef CONFIG_DM_SERIAL |
| 241 | |
| 242 | struct mxc_uart { |
| 243 | u32 rxd; |
| 244 | u32 spare0[15]; |
| 245 | |
| 246 | u32 txd; |
| 247 | u32 spare1[15]; |
| 248 | |
| 249 | u32 cr1; |
| 250 | u32 cr2; |
| 251 | u32 cr3; |
| 252 | u32 cr4; |
| 253 | |
| 254 | u32 fcr; |
| 255 | u32 sr1; |
| 256 | u32 sr2; |
| 257 | u32 esc; |
| 258 | |
| 259 | u32 tim; |
| 260 | u32 bir; |
| 261 | u32 bmr; |
| 262 | u32 brc; |
| 263 | |
| 264 | u32 onems; |
| 265 | u32 ts; |
| 266 | }; |
| 267 | |
| 268 | int mxc_serial_setbrg(struct udevice *dev, int baudrate) |
| 269 | { |
| 270 | struct mxc_serial_platdata *plat = dev->platdata; |
| 271 | struct mxc_uart *const uart = plat->reg; |
| 272 | u32 clk = imx_get_uartclk(); |
Stefan Agner | 83fd908 | 2016-07-13 00:25:35 -0700 | [diff] [blame] | 273 | u32 tmp; |
Simon Glass | a8ba569 | 2014-10-01 19:57:27 -0600 | [diff] [blame] | 274 | |
Stefan Agner | 83fd908 | 2016-07-13 00:25:35 -0700 | [diff] [blame] | 275 | tmp = 4 << UFCR_RFDIV_SHF; |
| 276 | if (plat->use_dte) |
| 277 | tmp |= UFCR_DCEDTE; |
| 278 | writel(tmp, &uart->fcr); |
| 279 | |
Simon Glass | a8ba569 | 2014-10-01 19:57:27 -0600 | [diff] [blame] | 280 | writel(0xf, &uart->bir); |
| 281 | writel(clk / (2 * baudrate), &uart->bmr); |
| 282 | |
| 283 | writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST, |
| 284 | &uart->cr2); |
| 285 | writel(UCR1_UARTEN, &uart->cr1); |
| 286 | |
| 287 | return 0; |
| 288 | } |
| 289 | |
| 290 | static int mxc_serial_probe(struct udevice *dev) |
| 291 | { |
| 292 | struct mxc_serial_platdata *plat = dev->platdata; |
| 293 | struct mxc_uart *const uart = plat->reg; |
| 294 | |
| 295 | writel(0, &uart->cr1); |
| 296 | writel(0, &uart->cr2); |
| 297 | while (!(readl(&uart->cr2) & UCR2_SRST)); |
| 298 | writel(0x704 | UCR3_ADNIMP, &uart->cr3); |
| 299 | writel(0x8000, &uart->cr4); |
| 300 | writel(0x2b, &uart->esc); |
| 301 | writel(0, &uart->tim); |
| 302 | writel(0, &uart->ts); |
| 303 | |
| 304 | return 0; |
| 305 | } |
| 306 | |
| 307 | static int mxc_serial_getc(struct udevice *dev) |
| 308 | { |
| 309 | struct mxc_serial_platdata *plat = dev->platdata; |
| 310 | struct mxc_uart *const uart = plat->reg; |
| 311 | |
| 312 | if (readl(&uart->ts) & UTS_RXEMPTY) |
| 313 | return -EAGAIN; |
| 314 | |
| 315 | return readl(&uart->rxd) & URXD_RX_DATA; |
| 316 | } |
| 317 | |
| 318 | static int mxc_serial_putc(struct udevice *dev, const char ch) |
| 319 | { |
| 320 | struct mxc_serial_platdata *plat = dev->platdata; |
| 321 | struct mxc_uart *const uart = plat->reg; |
| 322 | |
| 323 | if (!(readl(&uart->ts) & UTS_TXEMPTY)) |
| 324 | return -EAGAIN; |
| 325 | |
| 326 | writel(ch, &uart->txd); |
| 327 | |
| 328 | return 0; |
| 329 | } |
| 330 | |
| 331 | static int mxc_serial_pending(struct udevice *dev, bool input) |
| 332 | { |
| 333 | struct mxc_serial_platdata *plat = dev->platdata; |
| 334 | struct mxc_uart *const uart = plat->reg; |
| 335 | uint32_t sr2 = readl(&uart->sr2); |
| 336 | |
| 337 | if (input) |
| 338 | return sr2 & USR2_RDR ? 1 : 0; |
| 339 | else |
| 340 | return sr2 & USR2_TXDC ? 0 : 1; |
| 341 | } |
| 342 | |
| 343 | static const struct dm_serial_ops mxc_serial_ops = { |
| 344 | .putc = mxc_serial_putc, |
| 345 | .pending = mxc_serial_pending, |
| 346 | .getc = mxc_serial_getc, |
| 347 | .setbrg = mxc_serial_setbrg, |
| 348 | }; |
| 349 | |
Stefan Agner | a99546a | 2016-10-05 15:27:03 -0700 | [diff] [blame] | 350 | #if CONFIG_IS_ENABLED(OF_CONTROL) |
| 351 | static int mxc_serial_ofdata_to_platdata(struct udevice *dev) |
| 352 | { |
| 353 | struct mxc_serial_platdata *plat = dev->platdata; |
| 354 | fdt_addr_t addr; |
| 355 | |
| 356 | addr = dev_get_addr(dev); |
| 357 | if (addr == FDT_ADDR_T_NONE) |
| 358 | return -EINVAL; |
| 359 | |
| 360 | plat->reg = (struct mxc_uart *)addr; |
| 361 | |
Simon Glass | e160f7d | 2017-01-17 16:52:55 -0700 | [diff] [blame] | 362 | plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), |
Stefan Agner | a99546a | 2016-10-05 15:27:03 -0700 | [diff] [blame] | 363 | "fsl,dte-mode"); |
| 364 | return 0; |
| 365 | } |
| 366 | |
| 367 | static const struct udevice_id mxc_serial_ids[] = { |
Sébastien Szymanski | 3a5d636 | 2017-03-07 14:33:24 +0100 | [diff] [blame] | 368 | { .compatible = "fsl,imx6ul-uart" }, |
Stefan Agner | a99546a | 2016-10-05 15:27:03 -0700 | [diff] [blame] | 369 | { .compatible = "fsl,imx7d-uart" }, |
| 370 | { } |
| 371 | }; |
| 372 | #endif |
| 373 | |
Simon Glass | a8ba569 | 2014-10-01 19:57:27 -0600 | [diff] [blame] | 374 | U_BOOT_DRIVER(serial_mxc) = { |
| 375 | .name = "serial_mxc", |
| 376 | .id = UCLASS_SERIAL, |
Stefan Agner | a99546a | 2016-10-05 15:27:03 -0700 | [diff] [blame] | 377 | #if CONFIG_IS_ENABLED(OF_CONTROL) |
| 378 | .of_match = mxc_serial_ids, |
| 379 | .ofdata_to_platdata = mxc_serial_ofdata_to_platdata, |
| 380 | .platdata_auto_alloc_size = sizeof(struct mxc_serial_platdata), |
| 381 | #endif |
Simon Glass | a8ba569 | 2014-10-01 19:57:27 -0600 | [diff] [blame] | 382 | .probe = mxc_serial_probe, |
| 383 | .ops = &mxc_serial_ops, |
| 384 | .flags = DM_FLAG_PRE_RELOC, |
| 385 | }; |
| 386 | #endif |