Siarhei Siamashka | b8329ac | 2015-01-19 05:23:32 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) 2015 Siarhei Siamashka <siarhei.siamashka@gmail.com> |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * Support for the SSD2828 bridge chip, which can take pixel data coming |
| 9 | * from a parallel LCD interface and translate it on the flight into MIPI DSI |
| 10 | * interface for driving a MIPI compatible TFT display. |
| 11 | * |
| 12 | * Implemented as a utility function. To be used from display drivers, which are |
| 13 | * responsible for driving parallel LCD hardware in front of the video pipeline. |
| 14 | */ |
| 15 | |
| 16 | #ifndef _SSD2828_H |
| 17 | #define _SSD2828_H |
| 18 | |
| 19 | struct ctfb_res_modes; |
| 20 | |
| 21 | struct ssd2828_config { |
| 22 | /*********************************************************************/ |
| 23 | /* SSD2828 configuration */ |
| 24 | /*********************************************************************/ |
| 25 | |
| 26 | /* |
| 27 | * The pins, which are used for SPI communication. This is only used |
| 28 | * for configuring SSD2828, so the performance is irrelevant (only |
| 29 | * around a hundred of bytes is moved). Also these can be any arbitrary |
| 30 | * GPIO pins (not necessarily the pins having hardware SPI function). |
| 31 | * Moreover, the 'sdo' pin may be even not wired up in some devices. |
| 32 | * |
| 33 | * These configuration variables need to be set as pin numbers for |
| 34 | * the standard u-boot GPIO interface (gpio_get_value/gpio_set_value |
| 35 | * functions). Note that -1 value can be used for the pins, which are |
| 36 | * not really wired up. |
| 37 | */ |
| 38 | int csx_pin; |
| 39 | int sck_pin; |
| 40 | int sdi_pin; |
| 41 | int sdo_pin; |
| 42 | /* SSD2828 reset pin (shared with LCD panel reset) */ |
| 43 | int reset_pin; |
| 44 | |
| 45 | /* |
| 46 | * The SSD2828 has its own dedicated clock source 'tx_clk' (connected |
| 47 | * to TX_CLK_XIO/TX_CLK_XIN pins), which is necessary at least for |
| 48 | * clocking SPI after reset. The exact clock speed is not strictly, |
| 49 | * defined, but the datasheet says that it must be somewhere in the |
Siarhei Siamashka | dddccd6 | 2015-01-19 05:23:35 +0200 | [diff] [blame] | 50 | * 8MHz - 30MHz range (see "TX_CLK Timing" section). It can be also |
| 51 | * used as a reference clock for PLL. If the exact clock frequency |
| 52 | * is known, then it can be specified here. If it is unknown, or the |
| 53 | * information is not trustworthy, then it can be set to 0. |
| 54 | * |
| 55 | * If unsure, set to 0. |
Siarhei Siamashka | b8329ac | 2015-01-19 05:23:32 +0200 | [diff] [blame] | 56 | */ |
| 57 | int ssd2828_tx_clk_khz; |
| 58 | |
| 59 | /* |
| 60 | * This is not a property of the used LCD panel, but more like a |
| 61 | * property of the SSD2828 wiring. See the "SSD2828QN4 RGB data |
| 62 | * arrangement" table in the datasheet. The SSD2828 pins are arranged |
| 63 | * in such a way that 18bpp and 24bpp configurations are completely |
| 64 | * incompatible with each other. |
| 65 | * |
| 66 | * Depending on the color depth, this must be set to 16, 18 or 24. |
| 67 | */ |
| 68 | int ssd2828_color_depth; |
| 69 | |
| 70 | /*********************************************************************/ |
| 71 | /* LCD panel configuration */ |
| 72 | /*********************************************************************/ |
| 73 | |
| 74 | /* |
| 75 | * The number of lanes in the MIPI DSI interface. May vary from 1 to 4. |
| 76 | * |
| 77 | * This information can be found in the LCD panel datasheet. |
| 78 | */ |
| 79 | int mipi_dsi_number_of_data_lanes; |
| 80 | |
| 81 | /* |
| 82 | * Data transfer bit rate per lane. Please note that it is expected |
| 83 | * to be higher than the pixel clock rate of the used video mode when |
| 84 | * multiplied by the number of lanes. This is perfectly normal because |
| 85 | * MIPI DSI handles data transfers in periodic bursts, and uses the |
| 86 | * idle time between bursts for sending configuration information and |
| 87 | * commands. Or just for saving power. |
| 88 | * |
| 89 | * The necessary Mbps/lane information can be found in the LCD panel |
| 90 | * datasheet. Note that the transfer rate can't be always set precisely |
| 91 | * and it may be rounded *up* (introducing no more than 10Mbps error). |
| 92 | */ |
| 93 | int mipi_dsi_bitrate_per_data_lane_mbps; |
| 94 | |
| 95 | /* |
| 96 | * Setting this to 1 enforces packing of 18bpp pixel data in 24bpp |
| 97 | * envelope when sending it over the MIPI DSI link. |
| 98 | * |
| 99 | * If unsure, set to 0. |
| 100 | */ |
| 101 | int mipi_dsi_loosely_packed_pixel_format; |
| 102 | |
| 103 | /* |
| 104 | * According to the "Example for system sleep in and out" section in |
| 105 | * the SSD2828 datasheet, some LCD panel specific delays are necessary |
| 106 | * after MIPI DCS commands EXIT_SLEEP_MODE and SET_DISPLAY_ON. |
| 107 | * |
| 108 | * For example, Allwinner uses 100 milliseconds delay after |
| 109 | * EXIT_SLEEP_MODE and 200 milliseconds delay after SET_DISPLAY_ON. |
| 110 | */ |
| 111 | int mipi_dsi_delay_after_exit_sleep_mode_ms; |
| 112 | int mipi_dsi_delay_after_set_display_on_ms; |
| 113 | }; |
| 114 | |
| 115 | /* |
| 116 | * Initialize the SSD2828 chip. It needs the 'ssd2828_config' structure |
| 117 | * and also the video mode timings. |
| 118 | * |
| 119 | * The right place to insert this function call is after the parallel LCD |
| 120 | * interface is initialized and before turning on the backlight. This is |
| 121 | * advised in the "Example for system sleep in and out" section of the |
Siarhei Siamashka | dddccd6 | 2015-01-19 05:23:35 +0200 | [diff] [blame] | 122 | * SSD2828 datasheet. And also SS2828 may use 'pclk' as the clock source |
| 123 | * for PLL, which means that the input signal must be already there. |
Siarhei Siamashka | b8329ac | 2015-01-19 05:23:32 +0200 | [diff] [blame] | 124 | */ |
| 125 | int ssd2828_init(const struct ssd2828_config *cfg, |
| 126 | const struct ctfb_res_modes *mode); |
| 127 | |
| 128 | #endif |