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Dirk Eibach2da0fc02011-01-21 09:31:21 +01001/*
2 * (C) Copyright 2010
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Dirk Eibach2da0fc02011-01-21 09:31:21 +01006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1 /* this is a PPC405 CPU */
Dirk Eibach2da0fc02011-01-21 09:31:21 +010012#define CONFIG_DLVISION_10G 1 /* on a DLVision-10G board */
13
14#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
15
16/*
17 * Include common defines/options for all AMCC eval boards
18 */
19#define CONFIG_HOSTNAME dlvsion-10g
Dirk Eibachcccd4f42014-07-03 09:28:20 +020020#define CONFIG_IDENT_STRING " dlvision-10g 0.06"
Dirk Eibach2da0fc02011-01-21 09:31:21 +010021#include "amcc-common.h"
22
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000023#define CONFIG_BOARD_EARLY_INIT_F
24#define CONFIG_BOARD_EARLY_INIT_R
Dirk Eibachb19bf832012-04-26 03:54:23 +000025#define CONFIG_MISC_INIT_R
Dirk Eibach2da0fc02011-01-21 09:31:21 +010026#define CONFIG_LAST_STAGE_INIT
27
28#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
29
Dirk Eibach6cfa9ee2011-04-06 13:53:50 +020030#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
Dirk Eibach6cfa9ee2011-04-06 13:53:50 +020031
Dirk Eibach2da0fc02011-01-21 09:31:21 +010032/*
33 * Configure PLL
34 */
35#define PLLMR0_DEFAULT PLLMR0_266_133_66
36#define PLLMR1_DEFAULT PLLMR1_266_133_66
37
38/* new uImage format support */
39#define CONFIG_FIT
40#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
Dirk Eibach9a4f4792014-07-03 09:28:26 +020041#define CONFIG_FIT_DISABLE_SHA256
Dirk Eibach2da0fc02011-01-21 09:31:21 +010042
43#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
44
45/*
46 * Default environment variables
47 */
48#define CONFIG_EXTRA_ENV_SETTINGS \
49 CONFIG_AMCC_DEF_ENV \
50 CONFIG_AMCC_DEF_ENV_POWERPC \
51 CONFIG_AMCC_DEF_ENV_NOR_UPD \
52 "kernel_addr=fc000000\0" \
53 "fdt_addr=fc1e0000\0" \
54 "ramdisk_addr=fc200000\0" \
55 ""
56
57#define CONFIG_PHY_ADDR 4 /* PHY address */
58#define CONFIG_HAS_ETH0
59#define CONFIG_HAS_ETH1
60#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
61#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
62
63/*
64 * Commands additional to the ones defined in amcc-common.h
65 */
Dirk Eibachb19bf832012-04-26 03:54:23 +000066#define CONFIG_CMD_DTT
Dirk Eibach4fb9b412014-07-03 09:28:25 +020067#undef CONFIG_CMD_DHCP
68#undef CONFIG_CMD_DIAG
Dirk Eibach2da0fc02011-01-21 09:31:21 +010069#undef CONFIG_CMD_EEPROM
Dirk Eibache1d11272015-10-28 11:46:28 +010070#define CONFIG_CMD_I2C
Dirk Eibach4fb9b412014-07-03 09:28:25 +020071#undef CONFIG_CMD_IRQ
Dirk Eibach2da0fc02011-01-21 09:31:21 +010072
73/*
74 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
75 */
76#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
77
78/* SDRAM timings used in datasheet */
79#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
80#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
81#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
82#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
83#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
84
85/*
86 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
87 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
88 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
89 * The Linux BASE_BAUD define should match this configuration.
90 * baseBaud = cpuClock/(uartDivisor*16)
91 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
92 * set Linux BASE_BAUD to 403200.
93 */
94#define CONFIG_CONS_INDEX 1 /* Use UART0 */
95#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
96#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
97#define CONFIG_SYS_BASE_BAUD 691200
98
99/*
100 * I2C stuff
101 */
Dirk Eibache3135362014-07-03 09:28:19 +0200102#define CONFIG_SYS_I2C_PPC4XX
103#define CONFIG_SYS_I2C_PPC4XX_CH0
Dirk Eibach880540d2013-04-25 02:40:01 +0000104#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
Dirk Eibache3135362014-07-03 09:28:19 +0200105#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100106
Dirk Eibachb46226b2014-07-03 09:28:18 +0200107#define CONFIG_SYS_I2C_IHS
Dirk Eibache1d11272015-10-28 11:46:28 +0100108#define CONFIG_SYS_I2C_IHS_DUAL
Dirk Eibachb46226b2014-07-03 09:28:18 +0200109#define CONFIG_SYS_I2C_IHS_CH0
110#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
111#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
Dirk Eibache1d11272015-10-28 11:46:28 +0100112#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
113#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
Dirk Eibachb46226b2014-07-03 09:28:18 +0200114#define CONFIG_SYS_I2C_IHS_CH1
115#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
116#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
Dirk Eibache1d11272015-10-28 11:46:28 +0100117#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
118#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
Dirk Eibachb46226b2014-07-03 09:28:18 +0200119
Dirk Eibache1d11272015-10-28 11:46:28 +0100120#define CONFIG_SYS_SPD_BUS_NUM 4
Dirk Eibachb46226b2014-07-03 09:28:18 +0200121
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100122/* Temp sensor/hwmon/dtt */
Dirk Eibache1d11272015-10-28 11:46:28 +0100123#define CONFIG_SYS_DTT_BUS_NUM 4
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100124#define CONFIG_DTT_LM63 1 /* National LM63 */
Dirk Eibach2ade7be2012-04-26 03:54:24 +0000125#define CONFIG_DTT_SENSORS { 0x4c, 0x4e, 0x18 } /* Sensor addresses */
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100126#define CONFIG_DTT_PWM_LOOKUPTABLE \
Dirk Eibach97ca7b32011-10-04 11:13:53 +0200127 { { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\
128 { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100129#define CONFIG_DTT_TACH_LIMIT 0xa10
130
Dirk Eibache1d11272015-10-28 11:46:28 +0100131#define CONFIG_SYS_ICS8N3QV01_I2C {1, 3}
132#define CONFIG_SYS_SIL1178_I2C {0, 2}
133#define CONFIG_SYS_DP501_I2C {0, 2}
Dirk Eibache3135362014-07-03 09:28:19 +0200134
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100135/* EBC peripherals */
136
137#define CONFIG_SYS_FLASH_BASE 0xFC000000
138#define CONFIG_SYS_FPGA0_BASE 0x7f100000
139#define CONFIG_SYS_FPGA1_BASE 0x7f200000
140#define CONFIG_SYS_LATCH_BASE 0x7f300000
141
142#define CONFIG_SYS_FPGA_BASE(k) \
143 (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
144
145#define CONFIG_SYS_FPGA_DONE(k) \
146 (k ? 0x2000 : 0x1000)
147
148#define CONFIG_SYS_FPGA_COUNT 2
149
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200150#define CONFIG_SYS_FPGA_PTR { \
151 (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
152 (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
153
154#define CONFIG_SYS_FPGA_COMMON
155
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100156#define CONFIG_SYS_LATCH0_RESET 0xffff
157#define CONFIG_SYS_LATCH0_BOOT 0xffff
Dirk Eibach3e24dd22013-08-09 10:52:54 +0200158#define CONFIG_SYS_LATCH1_RESET 0xffbf
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100159#define CONFIG_SYS_LATCH1_BOOT 0xffff
160
Dirk Eibach5cb41002011-04-06 13:53:46 +0200161#define CONFIG_SYS_FPGA_NO_RFL_HI
162
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100163/*
164 * FLASH organization
165 */
166#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
167#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
168
169#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
170
171#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
172#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
173
174#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
175#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
176
177#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100178
179#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
180#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
181
182#ifdef CONFIG_ENV_IS_IN_FLASH
183#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
184#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
185#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
186
187/* Address and size of Redundant Environment Sector */
188#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
189#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
190#endif
191
192/*
193 * PPC405 GPIO Configuration
194 */
195#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
196{ \
197/* GPIO Core 0 */ \
198{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
199{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
200{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
201{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
202{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
203{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
204{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
205{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
206{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
207{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
208{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
209{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
210{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
211{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
212{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
213{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
214{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
215{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
216{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
217{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
218{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
219{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
220{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
221{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
222{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
223{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
224{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
225{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
226{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
227{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
228{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
229{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
230} \
231}
232
233/*
234 * Definitions for initial stack pointer and data area (in data cache)
235 */
236/* use on chip memory (OCM) for temperary stack until sdram is tested */
237#define CONFIG_SYS_TEMP_STACK_OCM 1
238
239/* On Chip Memory location */
240#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
241#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
242#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
243#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
244
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100245#define CONFIG_SYS_GBL_DATA_OFFSET \
Masahiro Yamada627b73e2014-02-07 09:23:03 +0900246 (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100247#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
248
249/*
250 * External Bus Controller (EBC) Setup
251 */
252
253/* Memory Bank 0 (NOR-flash) */
254#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_ENABLED | \
255 EBC_BXAP_FWT_ENCODE(8) | \
256 EBC_BXAP_BWT_ENCODE(7) | \
257 EBC_BXAP_BCE_DISABLE | \
258 EBC_BXAP_BCT_2TRANS | \
259 EBC_BXAP_CSN_ENCODE(0) | \
260 EBC_BXAP_OEN_ENCODE(2) | \
261 EBC_BXAP_WBN_ENCODE(2) | \
262 EBC_BXAP_WBF_ENCODE(2) | \
263 EBC_BXAP_TH_ENCODE(4) | \
264 EBC_BXAP_RE_DISABLED | \
265 EBC_BXAP_SOR_NONDELAYED | \
266 EBC_BXAP_BEM_WRITEONLY | \
267 EBC_BXAP_PEN_DISABLED)
268#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
269 EBC_BXCR_BS_64MB | \
270 EBC_BXCR_BU_RW | \
271 EBC_BXCR_BW_16BIT)
272
273/* Memory Bank 1 (FPGA0) */
274#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
275 EBC_BXAP_TWT_ENCODE(5) | \
276 EBC_BXAP_BCE_DISABLE | \
277 EBC_BXAP_BCT_2TRANS | \
278 EBC_BXAP_CSN_ENCODE(0) | \
279 EBC_BXAP_OEN_ENCODE(2) | \
280 EBC_BXAP_WBN_ENCODE(1) | \
281 EBC_BXAP_WBF_ENCODE(1) | \
282 EBC_BXAP_TH_ENCODE(0) | \
283 EBC_BXAP_RE_DISABLED | \
284 EBC_BXAP_SOR_NONDELAYED | \
285 EBC_BXAP_BEM_WRITEONLY | \
286 EBC_BXAP_PEN_DISABLED)
287#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
288 EBC_BXCR_BS_1MB | \
289 EBC_BXCR_BU_RW | \
290 EBC_BXCR_BW_16BIT)
291
292/* Memory Bank 2 (FPGA1) */
293#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
294 EBC_BXAP_TWT_ENCODE(6) | \
295 EBC_BXAP_BCE_DISABLE | \
296 EBC_BXAP_BCT_2TRANS | \
297 EBC_BXAP_CSN_ENCODE(0) | \
298 EBC_BXAP_OEN_ENCODE(2) | \
299 EBC_BXAP_WBN_ENCODE(1) | \
300 EBC_BXAP_WBF_ENCODE(1) | \
301 EBC_BXAP_TH_ENCODE(0) | \
302 EBC_BXAP_RE_DISABLED | \
303 EBC_BXAP_SOR_NONDELAYED | \
304 EBC_BXAP_BEM_WRITEONLY | \
305 EBC_BXAP_PEN_DISABLED)
306#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
307 EBC_BXCR_BS_1MB | \
308 EBC_BXCR_BU_RW | \
309 EBC_BXCR_BW_16BIT)
310
311/* Memory Bank 3 (Latches) */
312#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \
313 EBC_BXAP_FWT_ENCODE(8) | \
314 EBC_BXAP_BWT_ENCODE(4) | \
315 EBC_BXAP_BCE_DISABLE | \
316 EBC_BXAP_BCT_2TRANS | \
317 EBC_BXAP_CSN_ENCODE(0) | \
318 EBC_BXAP_OEN_ENCODE(1) | \
319 EBC_BXAP_WBN_ENCODE(1) | \
320 EBC_BXAP_WBF_ENCODE(1) | \
321 EBC_BXAP_TH_ENCODE(2) | \
322 EBC_BXAP_RE_DISABLED | \
323 EBC_BXAP_SOR_NONDELAYED | \
324 EBC_BXAP_BEM_WRITEONLY | \
325 EBC_BXAP_PEN_DISABLED)
326#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
327 EBC_BXCR_BS_1MB | \
328 EBC_BXCR_BU_RW | \
329 EBC_BXCR_BW_16BIT)
330
331/*
332 * OSD Setup
333 */
Dirk Eibach7749c842011-04-06 13:53:48 +0200334#define CONFIG_SYS_MPC92469AC
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100335#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
Dirk Eibache1d11272015-10-28 11:46:28 +0100336#define CONFIG_SYS_DP501_DIFFERENTIAL
337#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100338
339#endif /* __CONFIG_H */