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Tapani Utriainen550e3752013-12-04 09:27:33 +01001/*
2 * Configuration settings for the TechNexion TAO-3530 SOM
3 * equipped on Thunder baseboard.
4 *
5 * Edward Lin <linuxfae@technexion.com>
6 * Tapani Utriainen <linuxfae@technexion.com>
7 *
Stefan Roesea9f52492013-12-04 09:27:34 +01008 * Copyright (C) 2013 Stefan Roese <sr@denx.de>
9 *
Tapani Utriainen550e3752013-12-04 09:27:33 +010010 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16/*
17 * High Level Configuration Options
18 */
Tapani Utriainen550e3752013-12-04 09:27:33 +010019#define CONFIG_OMAP /* in a TI OMAP core */
Tapani Utriainen550e3752013-12-04 09:27:33 +010020
21#define CONFIG_OMAP_GPIO
22#define CONFIG_OMAP_COMMON
Nishanth Menonc6f90e12015-03-09 17:12:08 -050023/* Common ARM Erratas */
24#define CONFIG_ARM_ERRATA_454179
25#define CONFIG_ARM_ERRATA_430973
26#define CONFIG_ARM_ERRATA_621766
Tapani Utriainen550e3752013-12-04 09:27:33 +010027
28#define MACH_TYPE_OMAP3_TAO3530 2836
29
30#define CONFIG_SDRC /* Has an SDRC controller */
31
32#include <asm/arch/cpu.h> /* get chip and board defs */
Nishanth Menon987ec582015-03-09 17:12:04 -050033#include <asm/arch/omap.h>
Tapani Utriainen550e3752013-12-04 09:27:33 +010034
35/*
36 * Display CPU and Board information
37 */
38#define CONFIG_DISPLAY_CPUINFO
39#define CONFIG_DISPLAY_BOARDINFO
40
41/* Clock Defines */
42#define V_OSCK 26000000 /* Clock output from T2 */
43#define V_SCLK (V_OSCK >> 1)
44
45#define CONFIG_MISC_INIT_R
46
47#define CONFIG_OF_LIBFDT
48
49#define CONFIG_CMDLINE_TAG
50#define CONFIG_SETUP_MEMORY_TAGS
51#define CONFIG_INITRD_TAG
52#define CONFIG_REVISION_TAG
53
54/*
55 * Size of malloc() pool
56 */
57#define CONFIG_SYS_MALLOC_LEN (4 << 20)
58#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
59
60/*
61 * Hardware drivers
62 */
63
64/*
65 * NS16550 Configuration
66 */
67#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
68
Tapani Utriainen550e3752013-12-04 09:27:33 +010069#define CONFIG_SYS_NS16550_SERIAL
70#define CONFIG_SYS_NS16550_REG_SIZE (-4)
71#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
72
73/*
74 * select serial console configuration
75 */
76#define CONFIG_CONS_INDEX 3
77#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
78
79/* allow to overwrite serial and ethaddr */
80#define CONFIG_ENV_OVERWRITE
81#define CONFIG_BAUDRATE 115200
82#define CONFIG_GENERIC_MMC
83#define CONFIG_MMC
84#define CONFIG_OMAP_HSMMC
85#define CONFIG_DOS_PARTITION
86
Stefan Roese36481de2014-02-14 09:47:17 +010087/* GPIO banks */
88#define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */
89#define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */
90#define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */
91#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
92#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
93
Tapani Utriainen550e3752013-12-04 09:27:33 +010094/* commands to include */
Tapani Utriainen550e3752013-12-04 09:27:33 +010095#define CONFIG_CMD_CACHE
96#define CONFIG_CMD_EXT2 /* EXT2 Support */
97#define CONFIG_CMD_FAT /* FAT support */
98#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
99#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
100#define MTDIDS_DEFAULT "nand0=nand"
101#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
102 "1920k(u-boot),128k(u-boot-env),"\
103 "4m(kernel),-(fs)"
104
105#define CONFIG_CMD_I2C /* I2C serial bus support */
106#define CONFIG_CMD_MMC /* MMC support */
107#define CONFIG_CMD_NAND /* NAND support */
108#define CONFIG_CMD_DHCP
109#define CONFIG_CMD_PING
110
Tapani Utriainen550e3752013-12-04 09:27:33 +0100111#define CONFIG_SYS_NO_FLASH
112#define CONFIG_SYS_I2C
113#define CONFIG_SYS_I2C_OMAP34XX
114#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
115#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
116#define CONFIG_I2C_MULTI_BUS
117
118/*
119 * TWL4030
120 */
121#define CONFIG_TWL4030_POWER
122#define CONFIG_TWL4030_LED
123
124/*
125 * Board NAND Info.
126 */
Tapani Utriainen550e3752013-12-04 09:27:33 +0100127#define CONFIG_NAND_OMAP_GPMC
128#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
129 /* to access nand */
130#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
131 /* to access nand at */
132 /* CS0 */
Tapani Utriainen550e3752013-12-04 09:27:33 +0100133
134#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
135 /* devices */
Stefano Babic55f1b392015-07-26 15:18:15 +0200136#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
Tapani Utriainen550e3752013-12-04 09:27:33 +0100137/* Environment information */
138#define CONFIG_BOOTDELAY 3
139
140#define CONFIG_EXTRA_ENV_SETTINGS \
141 "loadaddr=0x82000000\0" \
142 "console=ttyO2,115200n8\0" \
143 "mpurate=600\0" \
144 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
145 "tv_mode=omapfb.mode=tv:ntsc\0" \
146 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
147 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
148 "extra_options= \0" \
Tapani Utriainen550e3752013-12-04 09:27:33 +0100149 "mmcdev=0\0" \
150 "mmcroot=/dev/mmcblk0p2 rw\0" \
151 "mmcrootfstype=ext3 rootwait\0" \
152 "nandroot=ubi0:rootfs ubi.mtd=4\0" \
153 "nandrootfstype=ubifs\0" \
154 "mmcargs=setenv bootargs console=${console} " \
Tapani Utriainen550e3752013-12-04 09:27:33 +0100155 "mpurate=${mpurate} " \
156 "${video_mode} " \
157 "root=${mmcroot} " \
158 "rootfstype=${mmcrootfstype} " \
159 "${extra_options}\0" \
160 "nandargs=setenv bootargs console=${console} " \
Tapani Utriainen550e3752013-12-04 09:27:33 +0100161 "mpurate=${mpurate} " \
162 "${video_mode} " \
163 "${network_setting} " \
164 "root=${nandroot} " \
165 "rootfstype=${nandrootfstype} "\
166 "${extra_options}\0" \
167 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
168 "bootscript=echo Running bootscript from mmc ...; " \
169 "source ${loadaddr}\0" \
170 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
171 "mmcboot=echo Booting from mmc ...; " \
172 "run mmcargs; " \
173 "bootm ${loadaddr}\0" \
174 "nandboot=echo Booting from nand ...; " \
175 "run nandargs; " \
176 "nand read ${loadaddr} 280000 400000; " \
177 "bootm ${loadaddr}\0" \
178
179#define CONFIG_BOOTCOMMAND \
180 "if mmc rescan ${mmcdev}; then " \
181 "if run loadbootscript; then " \
182 "run bootscript; " \
183 "else " \
184 "if run loaduimage; then " \
185 "run mmcboot; " \
186 "else run nandboot; " \
187 "fi; " \
188 "fi; " \
189 "else run nandboot; fi"
190
191/*
192 * Miscellaneous configurable options
193 */
194#define CONFIG_SYS_LONGHELP /* undef to save memory */
195#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
Tapani Utriainen550e3752013-12-04 09:27:33 +0100196#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
197
198/* turn on command-line edit/hist/auto */
199#define CONFIG_CMDLINE_EDITING
200#define CONFIG_COMMAND_HISTORY
201#define CONFIG_AUTO_COMPLETE
202
203/* Print Buffer Size */
204#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
205 sizeof(CONFIG_SYS_PROMPT) + 16)
206#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
207/* Boot Argument Buffer Size */
208#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
209
210#define CONFIG_SYS_ALT_MEMTEST 1
211#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */
212 /* defaults */
213#define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */
214#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
215
216#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
217 /* load address */
218#define CONFIG_SYS_TEXT_BASE 0x80008000
219
220/*
221 * OMAP3 has 12 GP timers, they can be driven by the system clock
222 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
223 * This rate is divided by a local divisor.
224 */
225#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
226#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
227
228/*
229 * Stack sizes
230 *
231 * The stack sizes are set up in start.S using the settings below
232 */
233#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
234
235/*
236 * Physical Memory Map
237 */
238#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
239#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
240#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
241#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
242
243/*
244 * FLASH and environment organization
245 */
246
247/* **** PISMO SUPPORT *** */
Tapani Utriainen550e3752013-12-04 09:27:33 +0100248#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
pekon gupta222a3112014-07-18 17:59:41 +0530249#define CONFIG_SYS_FLASH_BASE NAND_BASE
Tapani Utriainen550e3752013-12-04 09:27:33 +0100250
251/* Monitor at start of flash */
252#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
253#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
254
255#define CONFIG_ENV_IS_IN_NAND 1
256#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
257#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
258
259#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10)
260#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
261#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
262
263#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
264#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
265#define CONFIG_SYS_INIT_RAM_SIZE 0x800
266#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
267 CONFIG_SYS_INIT_RAM_SIZE - \
268 GENERATED_GBL_DATA_SIZE)
269
270#define CONFIG_OMAP3_SPI
271
272/*
273 * USB
274 *
275 * Currently only EHCI is enabled, the MUSB OTG controller
276 * is not enabled.
277 */
278
279/* USB EHCI */
280#define CONFIG_CMD_USB
281#define CONFIG_USB_EHCI
282#define CONFIG_USB_EHCI_OMAP
283#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162
284
285#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
286#define CONFIG_USB_HOST_ETHER
287#define CONFIG_USB_ETHER_SMSC95XX
288
289#define CONFIG_USB_ETHER
290#define CONFIG_USB_ETHER_RNDIS
291#define CONFIG_USB_STORAGE
292#define CONGIG_CMD_STORAGE
293
Stefan Roesea9f52492013-12-04 09:27:34 +0100294/* Defines for SPL */
Stefan Roesea9f52492013-12-04 09:27:34 +0100295#define CONFIG_SPL_FRAMEWORK
296#define CONFIG_SPL_NAND_SIMPLE
297
298#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
299#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
Paul Kocialkowskie2ccdf82014-11-08 23:14:55 +0100300#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
Guillaume GARDET205b4f32014-10-15 17:53:11 +0200301#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Stefan Roesea9f52492013-12-04 09:27:34 +0100302
303#define CONFIG_SPL_BOARD_INIT
304#define CONFIG_SPL_LIBCOMMON_SUPPORT
305#define CONFIG_SPL_LIBDISK_SUPPORT
306#define CONFIG_SPL_I2C_SUPPORT
307#define CONFIG_SPL_LIBGENERIC_SUPPORT
308#define CONFIG_SPL_MMC_SUPPORT
309#define CONFIG_SPL_FAT_SUPPORT
310#define CONFIG_SPL_SERIAL_SUPPORT
311#define CONFIG_SPL_NAND_SUPPORT
312#define CONFIG_SPL_NAND_BASE
313#define CONFIG_SPL_NAND_DRIVERS
314#define CONFIG_SPL_NAND_ECC
315#define CONFIG_SPL_GPIO_SUPPORT
316#define CONFIG_SPL_POWER_SUPPORT
317#define CONFIG_SPL_OMAP3_ID_NAND
318#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
319
320/* NAND boot config */
321#define CONFIG_SYS_NAND_5_ADDR_CYCLE
322#define CONFIG_SYS_NAND_PAGE_COUNT 64
323#define CONFIG_SYS_NAND_PAGE_SIZE 2048
324#define CONFIG_SYS_NAND_OOBSIZE 64
325#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
326#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
327/*
328 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
329 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
330 */
331#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
332 10, 11, 12, 13 }
333#define CONFIG_SYS_NAND_ECCSIZE 512
334#define CONFIG_SYS_NAND_ECCBYTES 3
335#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
336
337#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
338#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
339
340#define CONFIG_SPL_TEXT_BASE 0x40200800
341#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
Stefan Roesea9f52492013-12-04 09:27:34 +0100342
343/*
344 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
345 * older x-loader implementations. And move the BSS area so that it
346 * doesn't overlap with TEXT_BASE.
347 */
348#define CONFIG_SYS_TEXT_BASE 0x80008000
349#define CONFIG_SPL_BSS_START_ADDR 0x80100000
350#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
351
352#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
353#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
354
Tapani Utriainen550e3752013-12-04 09:27:33 +0100355#endif /* __CONFIG_H */