| Stefan Roese | 4c835a6 | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | |
| 3 | / { |
| 4 | #address-cells = <1>; |
| 5 | #size-cells = <1>; |
| 6 | compatible = "ralink,mt7628a-soc"; |
| 7 | |
| 8 | cpus { |
| 9 | #address-cells = <1>; |
| 10 | #size-cells = <0>; |
| 11 | |
| 12 | cpu@0 { |
| 13 | compatible = "mti,mips24KEc"; |
| 14 | device_type = "cpu"; |
| 15 | reg = <0>; |
| 16 | }; |
| 17 | }; |
| 18 | |
| 19 | resetc: reset-controller { |
| 20 | compatible = "ralink,rt2880-reset"; |
| 21 | #reset-cells = <1>; |
| 22 | }; |
| 23 | |
| 24 | cpuintc: interrupt-controller { |
| 25 | #address-cells = <0>; |
| 26 | #interrupt-cells = <1>; |
| 27 | interrupt-controller; |
| 28 | compatible = "mti,cpu-interrupt-controller"; |
| 29 | }; |
| 30 | |
| 31 | palmbus@10000000 { |
| 32 | compatible = "palmbus", "simple-bus"; |
| 33 | reg = <0x10000000 0x200000>; |
| 34 | ranges = <0x0 0x10000000 0x1FFFFF>; |
| 35 | |
| 36 | #address-cells = <1>; |
| 37 | #size-cells = <1>; |
| 38 | |
| 39 | sysc: system-controller@0 { |
| 40 | compatible = "ralink,mt7620a-sysc", "syscon"; |
| 41 | reg = <0x0 0x100>; |
| 42 | }; |
| 43 | |
| Stefan Roese | 41f6e6e | 2018-08-16 15:27:32 +0200 | [diff] [blame] | 44 | syscon-reboot { |
| 45 | compatible = "syscon-reboot"; |
| 46 | regmap = <&sysc>; |
| 47 | offset = <0x34>; |
| 48 | mask = <0x1>; |
| 49 | }; |
| 50 | |
| Stefan Roese | 9a89b2b | 2018-10-09 08:59:08 +0200 | [diff] [blame^] | 51 | watchdog: watchdog@100 { |
| 52 | compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt"; |
| 53 | reg = <0x100 0x30>; |
| 54 | |
| 55 | resets = <&resetc 8>; |
| 56 | reset-names = "wdt"; |
| 57 | |
| 58 | interrupt-parent = <&intc>; |
| 59 | interrupts = <24>; |
| 60 | }; |
| 61 | |
| Stefan Roese | 4c835a6 | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 62 | intc: interrupt-controller@200 { |
| 63 | compatible = "ralink,rt2880-intc"; |
| 64 | reg = <0x200 0x100>; |
| 65 | |
| 66 | interrupt-controller; |
| 67 | #interrupt-cells = <1>; |
| 68 | |
| 69 | resets = <&resetc 9>; |
| 70 | reset-names = "intc"; |
| 71 | |
| 72 | interrupt-parent = <&cpuintc>; |
| 73 | interrupts = <2>; |
| 74 | |
| 75 | ralink,intc-registers = <0x9c 0xa0 |
| 76 | 0x6c 0xa4 |
| 77 | 0x80 0x78>; |
| 78 | }; |
| 79 | |
| 80 | memory-controller@300 { |
| 81 | compatible = "ralink,mt7620a-memc"; |
| 82 | reg = <0x300 0x100>; |
| 83 | }; |
| 84 | |
| Stefan Roese | 60f6be1 | 2018-10-09 08:59:07 +0200 | [diff] [blame] | 85 | gpio@600 { |
| 86 | #address-cells = <1>; |
| 87 | #size-cells = <0>; |
| 88 | |
| 89 | compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio"; |
| 90 | reg = <0x600 0x100>; |
| 91 | |
| 92 | interrupt-parent = <&intc>; |
| 93 | interrupts = <6>; |
| 94 | |
| 95 | gpio0: bank@0 { |
| 96 | reg = <0>; |
| 97 | compatible = "mtk,mt7621-gpio-bank"; |
| 98 | gpio-controller; |
| 99 | #gpio-cells = <2>; |
| 100 | }; |
| 101 | |
| 102 | gpio1: bank@1 { |
| 103 | reg = <1>; |
| 104 | compatible = "mtk,mt7621-gpio-bank"; |
| 105 | gpio-controller; |
| 106 | #gpio-cells = <2>; |
| 107 | }; |
| 108 | |
| 109 | gpio2: bank@2 { |
| 110 | reg = <2>; |
| 111 | compatible = "mtk,mt7621-gpio-bank"; |
| 112 | gpio-controller; |
| 113 | #gpio-cells = <2>; |
| 114 | }; |
| 115 | }; |
| 116 | |
| Stefan Roese | 4c835a6 | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 117 | spi0: spi@b00 { |
| 118 | compatible = "ralink,mt7621-spi"; |
| 119 | reg = <0xb00 0x40>; |
| 120 | #address-cells = <1>; |
| 121 | #size-cells = <0>; |
| Stefan Roese | fdd1a9f | 2018-08-16 15:27:33 +0200 | [diff] [blame] | 122 | |
| 123 | clock-frequency = <200000000>; |
| Stefan Roese | 4c835a6 | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 124 | }; |
| 125 | |
| 126 | uart0: uartlite@c00 { |
| 127 | compatible = "ns16550a"; |
| 128 | reg = <0xc00 0x100>; |
| 129 | |
| 130 | resets = <&resetc 12>; |
| 131 | reset-names = "uart0"; |
| 132 | |
| 133 | interrupt-parent = <&intc>; |
| 134 | interrupts = <20>; |
| 135 | |
| 136 | reg-shift = <2>; |
| 137 | }; |
| 138 | |
| 139 | uart1: uart1@d00 { |
| 140 | compatible = "ns16550a"; |
| 141 | reg = <0xd00 0x100>; |
| 142 | |
| 143 | resets = <&resetc 19>; |
| 144 | reset-names = "uart1"; |
| 145 | |
| 146 | interrupt-parent = <&intc>; |
| 147 | interrupts = <21>; |
| 148 | |
| 149 | reg-shift = <2>; |
| 150 | }; |
| 151 | |
| 152 | uart2: uart2@e00 { |
| 153 | compatible = "ns16550a"; |
| 154 | reg = <0xe00 0x100>; |
| 155 | |
| 156 | resets = <&resetc 20>; |
| 157 | reset-names = "uart2"; |
| 158 | |
| 159 | interrupt-parent = <&intc>; |
| 160 | interrupts = <22>; |
| 161 | |
| 162 | reg-shift = <2>; |
| 163 | }; |
| 164 | }; |
| 165 | |
| Stefan Roese | 82dbe64 | 2018-10-09 08:59:06 +0200 | [diff] [blame] | 166 | eth@10110000 { |
| 167 | compatible = "mediatek,mt7622-eth"; |
| 168 | reg = <0x10100000 0x10000 |
| 169 | 0x10110000 0x8000>; |
| 170 | |
| 171 | syscon = <&sysc>; |
| 172 | }; |
| 173 | |
| Stefan Roese | 4c835a6 | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 174 | usb_phy: usb-phy@10120000 { |
| 175 | compatible = "mediatek,mt7628-usbphy"; |
| 176 | reg = <0x10120000 0x1000>; |
| 177 | |
| 178 | #phy-cells = <0>; |
| 179 | |
| 180 | ralink,sysctl = <&sysc>; |
| 181 | resets = <&resetc 22 &resetc 25>; |
| 182 | reset-names = "host", "device"; |
| 183 | }; |
| 184 | |
| 185 | ehci@101c0000 { |
| 186 | compatible = "generic-ehci"; |
| 187 | reg = <0x101c0000 0x1000>; |
| 188 | |
| 189 | phys = <&usb_phy>; |
| 190 | phy-names = "usb"; |
| 191 | |
| 192 | interrupt-parent = <&intc>; |
| 193 | interrupts = <18>; |
| 194 | }; |
| 195 | }; |