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Rafal Jaworowski8993e542007-07-27 14:43:59 +02001/*
Wolfgang Denka927e492009-05-16 10:47:44 +02002 * (C) Copyright 2003 - 2009
Rafal Jaworowski8993e542007-07-27 14:43:59 +02003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Derived from the MPC8xx driver's header file.
6 */
7
8#ifndef __MPC512X_FEC_H
9#define __MPC512X_FEC_H
10
11#include <common.h>
Rafal Jaworowski8993e542007-07-27 14:43:59 +020012
Rafal Jaworowski8993e542007-07-27 14:43:59 +020013/* Receive & Transmit Buffer Descriptor definitions */
14typedef struct BufferDescriptor {
Wolfgang Denk3b74e7e2009-05-16 10:47:45 +020015 u16 status;
16 u16 dataLength;
17 u32 dataPointer;
Rafal Jaworowski8993e542007-07-27 14:43:59 +020018} FEC_RBD;
19
20typedef struct {
Wolfgang Denk3b74e7e2009-05-16 10:47:45 +020021 u16 status;
22 u16 dataLength;
23 u32 dataPointer;
Rafal Jaworowski8993e542007-07-27 14:43:59 +020024} FEC_TBD;
25
26/* private structure */
27typedef enum {
28 SEVENWIRE, /* 7-wire */
29 MII10, /* MII 10Mbps */
30 MII100 /* MII 100Mbps */
31} xceiver_type;
32
33/* BD Numer definitions */
34#define FEC_TBD_NUM 48 /* The user can adjust this value */
35#define FEC_RBD_NUM 32 /* The user can adjust this value */
36
37/* packet size limit */
Grzegorz Bernacki7a888d62007-09-10 17:39:08 +020038#define FEC_MAX_FRAME_LEN 1522 /* recommended default value */
39
40/* Buffer size must be evenly divisible by 16 */
41#define FEC_BUFFER_SIZE ((FEC_MAX_FRAME_LEN + 0x10) & (~0xf))
Rafal Jaworowski8993e542007-07-27 14:43:59 +020042
43typedef struct {
Wolfgang Denk3b74e7e2009-05-16 10:47:45 +020044 u8 frame[FEC_BUFFER_SIZE];
Rafal Jaworowski8993e542007-07-27 14:43:59 +020045} mpc512x_frame;
46
47typedef struct {
48 FEC_RBD rbd[FEC_RBD_NUM]; /* RBD ring */
49 FEC_TBD tbd[FEC_TBD_NUM]; /* TBD ring */
50 mpc512x_frame recv_frames[FEC_RBD_NUM]; /* receive buff */
51} mpc512x_buff_descs;
52
53typedef struct {
Wolfgang Denka927e492009-05-16 10:47:44 +020054 volatile fec512x_t *eth;
Rafal Jaworowski8993e542007-07-27 14:43:59 +020055 xceiver_type xcv_type; /* transceiver type */
56 mpc512x_buff_descs *bdBase; /* BD rings and recv buffer */
Wolfgang Denk3b74e7e2009-05-16 10:47:45 +020057 u16 rbdIndex; /* next receive BD to read */
58 u16 tbdIndex; /* next transmit BD to send */
59 u16 usedTbdIndex; /* next transmit BD to clean */
60 u16 cleanTbdNum; /* the number of available transmit BDs */
Rafal Jaworowski8993e542007-07-27 14:43:59 +020061} mpc512x_fec_priv;
62
63/* RBD bits definitions */
64#define FEC_RBD_EMPTY 0x8000 /* Buffer is empty */
65#define FEC_RBD_WRAP 0x2000 /* Last BD in ring */
66#define FEC_RBD_LAST 0x0800 /* Buffer is last in frame(useless) */
67#define FEC_RBD_MISS 0x0100 /* Miss bit for prom mode */
68#define FEC_RBD_BC 0x0080 /* The received frame is broadcast frame */
69#define FEC_RBD_MC 0x0040 /* The received frame is multicast frame */
70#define FEC_RBD_LG 0x0020 /* Frame length violation */
71#define FEC_RBD_NO 0x0010 /* Nonoctet align frame */
72#define FEC_RBD_SH 0x0008 /* Short frame */
73#define FEC_RBD_CR 0x0004 /* CRC error */
74#define FEC_RBD_OV 0x0002 /* Receive FIFO overrun */
75#define FEC_RBD_TR 0x0001 /* Frame is truncated */
76#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
77 FEC_RBD_OV | FEC_RBD_TR)
78
79/* TBD bits definitions */
80#define FEC_TBD_READY 0x8000 /* Buffer is ready */
81#define FEC_TBD_WRAP 0x2000 /* Last BD in ring */
82#define FEC_TBD_LAST 0x0800 /* Buffer is last in frame */
83#define FEC_TBD_TC 0x0400 /* Transmit the CRC */
84#define FEC_TBD_ABC 0x0200 /* Append bad CRC */
85
86/* MII-related definitios */
87#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
88#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
89#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
90#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
91#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
92#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */
93#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
94
95#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
96#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
97
98#endif /* __MPC512X_FEC_H */