blob: 1e6289290de209d28d5177ccc581e4d23165e0cc [file] [log] [blame]
Lei Wen3df619e2011-04-13 23:48:31 +05301/*
2 * (C) Copyright 2011
3 * Marvell Inc, <www.marvell.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Lei Wen3df619e2011-04-13 23:48:31 +05306 */
7
8#ifndef _MV_I2C_H_
9#define _MV_I2C_H_
10extern void i2c_clk_enable(void);
11
12/* Shall the current transfer have a start/stop condition? */
13#define I2C_COND_NORMAL 0
14#define I2C_COND_START 1
15#define I2C_COND_STOP 2
16
17/* Shall the current transfer be ack/nacked or being waited for it? */
18#define I2C_ACKNAK_WAITACK 1
19#define I2C_ACKNAK_SENDACK 2
20#define I2C_ACKNAK_SENDNAK 4
21
22/* Specify who shall transfer the data (master or slave) */
23#define I2C_READ 0
24#define I2C_WRITE 1
25
Lei Wen3df619e2011-04-13 23:48:31 +053026#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
Lei Wen3df619e2011-04-13 23:48:31 +053027
28#define I2C_ISR_INIT 0x7FF
29/* ----- Control register bits ---------------------------------------- */
30
31#define ICR_START 0x1 /* start bit */
32#define ICR_STOP 0x2 /* stop bit */
33#define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */
34#define ICR_TB 0x8 /* transfer byte bit */
35#define ICR_MA 0x10 /* master abort */
36#define ICR_SCLE 0x20 /* master clock enable, mona SCLEA */
37#define ICR_IUE 0x40 /* unit enable */
38#define ICR_GCD 0x80 /* general call disable */
39#define ICR_ITEIE 0x100 /* enable tx interrupts */
40#define ICR_IRFIE 0x200 /* enable rx interrupts, mona: DRFIE */
41#define ICR_BEIE 0x400 /* enable bus error ints */
42#define ICR_SSDIE 0x800 /* slave STOP detected int enable */
43#define ICR_ALDIE 0x1000 /* enable arbitration interrupt */
44#define ICR_SADIE 0x2000 /* slave address detected int enable */
45#define ICR_UR 0x4000 /* unit reset */
Stefan Roese9ad5a002016-09-16 15:07:53 +020046#ifdef CONFIG_ARMADA_3700
47#define ICR_SM 0x00000 /* Standard Mode */
48#define ICR_FM 0x10000 /* Fast Mode */
49#define ICR_MODE_MASK 0x30000 /* Mode mask */
50#else
51#define ICR_SM 0x00000 /* Standard Mode */
52#define ICR_FM 0x08000 /* Fast Mode */
53#define ICR_MODE_MASK 0x18000 /* Mode mask */
54#endif
Lei Wen3df619e2011-04-13 23:48:31 +053055
56/* ----- Status register bits ----------------------------------------- */
57
58#define ISR_RWM 0x1 /* read/write mode */
59#define ISR_ACKNAK 0x2 /* ack/nak status */
60#define ISR_UB 0x4 /* unit busy */
61#define ISR_IBB 0x8 /* bus busy */
62#define ISR_SSD 0x10 /* slave stop detected */
63#define ISR_ALD 0x20 /* arbitration loss detected */
64#define ISR_ITE 0x40 /* tx buffer empty */
65#define ISR_IRF 0x80 /* rx buffer full */
66#define ISR_GCAD 0x100 /* general call address detected */
67#define ISR_SAD 0x200 /* slave address detected */
68#define ISR_BED 0x400 /* bus error no ACK/NAK */
69
70#endif