blob: 4d9606e498b64f20ee9194cd48a22ab79172d8f5 [file] [log] [blame]
Jon Loeliger9553df82007-10-16 15:26:51 -05001/*
2 * Copyright 2007 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
9/*
10 * MPC8610HPCD board configuration file
Jon Loeliger9553df82007-10-16 15:26:51 -050011 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16/* High Level Configuration Options */
17#define CONFIG_MPC86xx 1 /* MPC86xx */
18#define CONFIG_MPC8610 1 /* MPC8610 specific */
19#define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */
Jon Loeliger9553df82007-10-16 15:26:51 -050020#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
21
York Suna8778802007-10-29 13:58:39 -050022#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
York Sun070ba562007-10-31 14:59:04 -050023
24/* video */
Jon Loeligercb06eb92008-02-20 12:24:11 -060025#undef CONFIG_VIDEO
York Sun070ba562007-10-31 14:59:04 -050026
27#if defined(CONFIG_VIDEO)
28#define CONFIG_CFB_CONSOLE
29#define CONFIG_VGA_AS_SINGLE_DEVICE
30#endif
31
Jon Loeliger9553df82007-10-16 15:26:51 -050032#ifdef RUN_DIAG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033#define CONFIG_SYS_DIAG_ADDR 0xff800000
Jon Loeliger9553df82007-10-16 15:26:51 -050034#endif
35
Becky Bruce1266df82008-11-03 15:44:01 -060036/*
37 * virtual address to be used for temporary mappings. There
38 * should be 128k free at this VA.
39 */
40#define CONFIG_SYS_SCRATCH_VA 0xc0000000
41
Jon Loeliger9553df82007-10-16 15:26:51 -050042#define CONFIG_PCI 1 /* Enable PCI/PCIE*/
43#define CONFIG_PCI1 1 /* PCI controler 1 */
44#define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
45#define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */
46#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Kumar Gala8ba93f62008-10-21 18:06:15 -050047#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Becky Bruce031976f2008-01-23 16:31:02 -060048#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Jon Loeliger9553df82007-10-16 15:26:51 -050049
50#define CONFIG_ENV_OVERWRITE
Jon Loeliger9553df82007-10-16 15:26:51 -050051#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
52
Becky Bruce31d82672008-05-08 19:02:12 -050053#define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */
Jon Loeliger9553df82007-10-16 15:26:51 -050054#define CONFIG_ALTIVEC 1
55
56/*
57 * L2CR setup -- make sure this is right for your board!
58 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_L2
Jon Loeliger9553df82007-10-16 15:26:51 -050060#define L2_INIT 0
York Suna8778802007-10-29 13:58:39 -050061#define L2_ENABLE (L2CR_L2E |0x00100000 )
Jon Loeliger9553df82007-10-16 15:26:51 -050062
63#ifndef CONFIG_SYS_CLK_FREQ
64#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
65#endif
66
67#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
York Suna8778802007-10-29 13:58:39 -050068#define CONFIG_MISC_INIT_R 1
Jon Loeliger9553df82007-10-16 15:26:51 -050069
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
71#define CONFIG_SYS_MEMTEST_END 0x00400000
Jon Loeliger9553df82007-10-16 15:26:51 -050072
73/*
74 * Base addresses -- Note these are effective addresses where the
75 * actual resources get mapped (not physical addresses)
76 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
78#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
79#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Jon Loeliger9553df82007-10-16 15:26:51 -050080
Jon Loeligerf6987382008-11-20 14:02:56 -060081#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
82#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
Kumar Galaad19e7a2009-08-05 07:59:35 -050083#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
Jon Loeligerf6987382008-11-20 14:02:56 -060084
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR+0x2c000)
Jon Loeliger9553df82007-10-16 15:26:51 -050086
Jon Loeliger39aa1a72008-08-26 15:01:36 -050087/* DDR Setup */
88#define CONFIG_FSL_DDR2
89#undef CONFIG_FSL_DDR_INTERACTIVE
90#define CONFIG_SPD_EEPROM /* Use SPD for DDR */
91#define CONFIG_DDR_SPD
92
93#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
94#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
95
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
97#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Becky Bruce1266df82008-11-03 15:44:01 -060098#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
Jon Loeliger9553df82007-10-16 15:26:51 -050099#define CONFIG_VERY_BIG_RAM
100
Jon Loeliger39aa1a72008-08-26 15:01:36 -0500101#define CONFIG_NUM_DDR_CONTROLLERS 1
102#define CONFIG_DIMM_SLOTS_PER_CTLR 1
103#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Jon Loeliger9553df82007-10-16 15:26:51 -0500104
Jon Loeliger39aa1a72008-08-26 15:01:36 -0500105#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
106
107/* These are used when DDR doesn't use SPD. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
Jon Loeliger9553df82007-10-16 15:26:51 -0500109
110#if 0 /* TODO */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
112#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
113#define CONFIG_SYS_DDR_TIMING_3 0x00000000
114#define CONFIG_SYS_DDR_TIMING_0 0x00260802
115#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
116#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
117#define CONFIG_SYS_DDR_MODE_1 0x00480432
118#define CONFIG_SYS_DDR_MODE_2 0x00000000
119#define CONFIG_SYS_DDR_INTERVAL 0x06180100
120#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
121#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
122#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
123#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
124#define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
125#define CONFIG_SYS_DDR_CONTROL2 0x04400010
Jon Loeliger9553df82007-10-16 15:26:51 -0500126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000
128#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
129#define CONFIG_SYS_DDR_SBE 0x000f0000
Jon Loeliger39aa1a72008-08-26 15:01:36 -0500130
Jon Loeliger9553df82007-10-16 15:26:51 -0500131#endif
Jon Loeliger39aa1a72008-08-26 15:01:36 -0500132
Jon Loeliger9553df82007-10-16 15:26:51 -0500133
Jon Loeligerad8f8682008-01-15 13:42:41 -0600134#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_I2C_EEPROM_NXID
Jean-Christophe PLAGNIOL-VILLARD32628c52008-08-30 23:54:58 +0200136#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
138#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
Jon Loeliger9553df82007-10-16 15:26:51 -0500139
140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */
142#define CONFIG_SYS_FLASH_BASE2 0xf8000000
Jon Loeliger9553df82007-10-16 15:26:51 -0500143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
Jon Loeliger9553df82007-10-16 15:26:51 -0500145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */
147#define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/
Jon Loeliger9553df82007-10-16 15:26:51 -0500148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */
150#define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */
Jon Loeliger9553df82007-10-16 15:26:51 -0500151#if 0 /* TODO */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_BR2_PRELIM 0xf0000000
153#define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */
Jon Loeliger9553df82007-10-16 15:26:51 -0500154#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */
156#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
Jon Loeliger9553df82007-10-16 15:26:51 -0500157
158
Jason Jin761421c2007-10-29 19:26:21 +0800159#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
Jon Loeliger9553df82007-10-16 15:26:51 -0500160#define PIXIS_BASE 0xe8000000 /* PIXIS registers */
161#define PIXIS_ID 0x0 /* Board ID at offset 0 */
162#define PIXIS_VER 0x1 /* Board version at offset 1 */
163#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
164#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
165#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */
166#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
York Suna8778802007-10-29 13:58:39 -0500167#define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/
Jon Loeliger9553df82007-10-16 15:26:51 -0500168#define PIXIS_VCTL 0x10 /* VELA Control Register */
169#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
170#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
171#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
172#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
173#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
174#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
175#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Timur Tabi2feb4af2010-03-31 17:44:13 -0500176#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */
Jon Loeliger9553df82007-10-16 15:26:51 -0500177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
179#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
Jon Loeliger9553df82007-10-16 15:26:51 -0500180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#undef CONFIG_SYS_FLASH_CHECKSUM
182#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
183#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
184#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
Becky Brucebf9a8c32008-11-05 14:55:35 -0600185#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
Jon Loeliger9553df82007-10-16 15:26:51 -0500186
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200187#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_FLASH_CFI
189#define CONFIG_SYS_FLASH_EMPTY_INFO
Jon Loeliger9553df82007-10-16 15:26:51 -0500190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
192#define CONFIG_SYS_RAMBOOT
Jon Loeliger9553df82007-10-16 15:26:51 -0500193#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#undef CONFIG_SYS_RAMBOOT
Jon Loeliger9553df82007-10-16 15:26:51 -0500195#endif
196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#if defined(CONFIG_SYS_RAMBOOT)
Jon Loeliger9553df82007-10-16 15:26:51 -0500198#undef CONFIG_SPD_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_SDRAM_SIZE 256
Jon Loeliger9553df82007-10-16 15:26:51 -0500200#endif
201
202#undef CONFIG_CLOCKS_IN_MHZ
203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_INIT_RAM_LOCK 1
205#ifndef CONFIG_SYS_INIT_RAM_LOCK
206#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Jon Loeliger9553df82007-10-16 15:26:51 -0500207#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */
Jon Loeliger9553df82007-10-16 15:26:51 -0500209#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
Jon Loeliger9553df82007-10-16 15:26:51 -0500211
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
213#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
214#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Jon Loeliger9553df82007-10-16 15:26:51 -0500215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
217#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
Jon Loeliger9553df82007-10-16 15:26:51 -0500218
219/* Serial Port */
220#define CONFIG_CONS_INDEX 1
221#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_NS16550
223#define CONFIG_SYS_NS16550_SERIAL
224#define CONFIG_SYS_NS16550_REG_SIZE 1
225#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Jon Loeliger9553df82007-10-16 15:26:51 -0500226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_BAUDRATE_TABLE \
Jon Loeliger9553df82007-10-16 15:26:51 -0500228 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
229
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
231#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Jon Loeliger9553df82007-10-16 15:26:51 -0500232
233/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_HUSH_PARSER
235#ifdef CONFIG_SYS_HUSH_PARSER
236#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Jon Loeliger9553df82007-10-16 15:26:51 -0500237#endif
238
239/*
240 * Pass open firmware flat tree to kernel
241 */
Jon Loeliger1df170f2008-01-04 12:07:27 -0600242#define CONFIG_OF_LIBFDT 1
243#define CONFIG_OF_BOARD_SETUP 1
244#define CONFIG_OF_STDOUT_VIA_ALIAS 1
245
Jon Loeliger9553df82007-10-16 15:26:51 -0500246
247/* maximum size of the flat tree (8K) */
248#define OF_FLAT_TREE_MAX_SIZE 8192
249
Jon Loeliger9553df82007-10-16 15:26:51 -0500250/*
251 * I2C
252 */
253#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
254#define CONFIG_HARD_I2C /* I2C with hardware support*/
255#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
257#define CONFIG_SYS_I2C_SLAVE 0x7F
258#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
259#define CONFIG_SYS_I2C_OFFSET 0x3000
Jon Loeliger9553df82007-10-16 15:26:51 -0500260
261/*
262 * General PCI
263 * Addresses are mapped 1-1.
264 */
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600265#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
266#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
267#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600269#define CONFIG_SYS_PCI1_IO_BUS 0x0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600271#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Jon Loeliger9553df82007-10-16 15:26:51 -0500273
Jon Loeliger9553df82007-10-16 15:26:51 -0500274/* controller 1, Base address 0xa000 */
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600275#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
276#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600278#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
280#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
Jon Loeliger9553df82007-10-16 15:26:51 -0500281
282/* controller 2, Base Address 0x9000 */
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600283#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
284#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600286#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000
288#define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */
Jon Loeliger9553df82007-10-16 15:26:51 -0500289
290
291#if defined(CONFIG_PCI)
292
293#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
294
295#define CONFIG_NET_MULTI
Roy Zang1d8a49e2007-09-13 18:52:28 +0800296#define CONFIG_CMD_NET
Jon Loeliger9553df82007-10-16 15:26:51 -0500297#define CONFIG_PCI_PNP /* do pci plug-and-play */
Becky Bruce4f93f8b2008-01-23 16:31:06 -0600298#define CONFIG_CMD_REGINFO
Jon Loeliger9553df82007-10-16 15:26:51 -0500299
Roy Zang7c2221e2008-01-15 16:38:38 +0800300#define CONFIG_ULI526X
301#ifdef CONFIG_ULI526X
Roy Zang1d8a49e2007-09-13 18:52:28 +0800302#define CONFIG_ETHADDR 00:E0:0C:00:00:01
303#endif
Jon Loeliger9553df82007-10-16 15:26:51 -0500304
Jon Loeliger9553df82007-10-16 15:26:51 -0500305/************************************************************
306 * USB support
307 ************************************************************/
York Sun070ba562007-10-31 14:59:04 -0500308#define CONFIG_PCI_OHCI 1
309#define CONFIG_USB_OHCI_NEW 1
Jon Loeliger9553df82007-10-16 15:26:51 -0500310#define CONFIG_USB_KEYBOARD 1
Jean-Christophe PLAGNIOL-VILLARD52cb4d42009-05-16 12:14:54 +0200311#define CONFIG_SYS_STDIO_DEREGISTER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_USB_EVENT_POLL 1
313#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
314#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
315#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
Jon Loeliger9553df82007-10-16 15:26:51 -0500316
317#if !defined(CONFIG_PCI_PNP)
318#define PCI_ENET0_IOADDR 0xe0000000
319#define PCI_ENET0_MEMADDR 0xe0000000
320#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
321#endif
322
323#define CONFIG_DOS_PARTITION
324#define CONFIG_SCSI_AHCI
325
326#ifdef CONFIG_SCSI_AHCI
327#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
329#define CONFIG_SYS_SCSI_MAX_LUN 1
330#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
331#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Jon Loeliger9553df82007-10-16 15:26:51 -0500332#endif
333
334#endif /* CONFIG_PCI */
335
336/*
337 * BAT0 2G Cacheable, non-guarded
338 * 0x0000_0000 2G DDR
339 */
Timur Tabi9ff32d82010-03-29 12:51:07 -0500340#define CONFIG_SYS_DBAT0L (BATL_PP_RW)
341#define CONFIG_SYS_IBAT0L (BATL_PP_RW)
Jon Loeliger9553df82007-10-16 15:26:51 -0500342
343/*
344 * BAT1 1G Cache-inhibited, guarded
345 * 0x8000_0000 256M PCI-1 Memory
346 * 0xa000_0000 256M PCI-Express 1 Memory
347 * 0x9000_0000 256M PCI-Express 2 Memory
348 */
349
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
Jon Loeliger9553df82007-10-16 15:26:51 -0500351 | BATL_GUARDEDSTORAGE)
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600352#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
354#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
Jon Loeliger9553df82007-10-16 15:26:51 -0500355
356/*
Jason Jinf3bceaa2007-10-26 18:31:59 +0800357 * BAT2 16M Cache-inhibited, guarded
Jon Loeliger9553df82007-10-16 15:26:51 -0500358 * 0xe100_0000 1M PCI-1 I/O
Jon Loeliger9553df82007-10-16 15:26:51 -0500359 */
360
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
Jon Loeliger9553df82007-10-16 15:26:51 -0500362 | BATL_GUARDEDSTORAGE)
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600363#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
365#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
Jon Loeliger9553df82007-10-16 15:26:51 -0500366
367/*
Becky Bruce104992f2008-11-02 18:19:32 -0600368 * BAT3 4M Cache-inhibited, guarded
369 * 0xe000_0000 4M CCSR
370 */
371
372#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
373 | BATL_GUARDEDSTORAGE)
374#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
375#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
376#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
377
Jon Loeligerf6987382008-11-20 14:02:56 -0600378#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
379#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
380 | BATL_PP_RW | BATL_CACHEINHIBIT \
381 | BATL_GUARDEDSTORAGE)
382#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
383 | BATU_BL_1M | BATU_VS | BATU_VP)
384#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
385 | BATL_PP_RW | BATL_CACHEINHIBIT)
386#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
387#endif
388
Becky Bruce104992f2008-11-02 18:19:32 -0600389/*
390 * BAT4 32M Cache-inhibited, guarded
Jason Jinf3bceaa2007-10-26 18:31:59 +0800391 * 0xe200_0000 1M PCI-Express 2 I/O
Jon Loeliger9553df82007-10-16 15:26:51 -0500392 * 0xe300_0000 1M PCI-Express 1 I/O
Jon Loeliger9553df82007-10-16 15:26:51 -0500393 */
394
Becky Bruce104992f2008-11-02 18:19:32 -0600395#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
Jon Loeliger9553df82007-10-16 15:26:51 -0500396 | BATL_GUARDEDSTORAGE)
Becky Bruce104992f2008-11-02 18:19:32 -0600397#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
398#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
Jon Loeliger9553df82007-10-16 15:26:51 -0500400
Becky Bruce104992f2008-11-02 18:19:32 -0600401
Jon Loeliger9553df82007-10-16 15:26:51 -0500402/*
403 * BAT5 128K Cacheable, non-guarded
404 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
405 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200406#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
407#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
408#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
409#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
Jon Loeliger9553df82007-10-16 15:26:51 -0500410
411/*
412 * BAT6 256M Cache-inhibited, guarded
413 * 0xf000_0000 256M FLASH
414 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
Jon Loeliger9553df82007-10-16 15:26:51 -0500416 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
418#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
419#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
Jon Loeliger9553df82007-10-16 15:26:51 -0500420
Becky Brucebf9a8c32008-11-05 14:55:35 -0600421/* Map the last 1M of flash where we're running from reset */
422#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
423 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
424#define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
425#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
426 | BATL_MEMCOHERENCE)
427#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
428
Jon Loeliger9553df82007-10-16 15:26:51 -0500429/*
430 * BAT7 4M Cache-inhibited, guarded
431 * 0xe800_0000 4M PIXIS
432 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433#define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
Jon Loeliger9553df82007-10-16 15:26:51 -0500434 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
436#define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
437#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
Jon Loeliger9553df82007-10-16 15:26:51 -0500438
439
440/*
441 * Environment
442 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200444#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200446#define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */
447#define CONFIG_ENV_SIZE 0x2000
Jon Loeliger9553df82007-10-16 15:26:51 -0500448#else
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200449#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200451#define CONFIG_ENV_SIZE 0x2000
Jon Loeliger9553df82007-10-16 15:26:51 -0500452#endif
453
454#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Jon Loeliger9553df82007-10-16 15:26:51 -0500456
457
458/*
459 * BOOTP options
460 */
461#define CONFIG_BOOTP_BOOTFILESIZE
462#define CONFIG_BOOTP_BOOTPATH
463#define CONFIG_BOOTP_GATEWAY
464#define CONFIG_BOOTP_HOSTNAME
465
466
467/*
468 * Command line configuration.
469 */
470#include <config_cmd_default.h>
471
472#define CONFIG_CMD_PING
473#define CONFIG_CMD_I2C
474#define CONFIG_CMD_MII
475
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200476#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500477#undef CONFIG_CMD_SAVEENV
Jon Loeliger9553df82007-10-16 15:26:51 -0500478#endif
479
480#if defined(CONFIG_PCI)
481#define CONFIG_CMD_PCI
482#define CONFIG_CMD_SCSI
483#define CONFIG_CMD_EXT2
York Sun070ba562007-10-31 14:59:04 -0500484#define CONFIG_CMD_USB
Jon Loeliger9553df82007-10-16 15:26:51 -0500485#endif
486
487
Jason Jin3473ab72008-05-13 11:50:36 +0800488#define CONFIG_WATCHDOG /* watchdog enabled */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200489#define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */
Jon Loeliger9553df82007-10-16 15:26:51 -0500490
York Suna8778802007-10-29 13:58:39 -0500491/*DIU Configuration*/
492#define DIU_CONNECT_TO_DVI /* DIU controller connects to DVI encoder*/
493
Jon Loeliger9553df82007-10-16 15:26:51 -0500494/*
495 * Miscellaneous configurable options
496 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200497#define CONFIG_SYS_LONGHELP /* undef to save memory */
Timur Tabi6bee7642008-01-16 15:48:12 -0600498#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200499#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
500#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger9553df82007-10-16 15:26:51 -0500501
502#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200503#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Jon Loeliger9553df82007-10-16 15:26:51 -0500504#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200505#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Jon Loeliger9553df82007-10-16 15:26:51 -0500506#endif
507
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200508#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
509#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
510#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
511#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Jon Loeliger9553df82007-10-16 15:26:51 -0500512
513/*
514 * For booting Linux, the board info and command line data
515 * have to be in the first 8 MB of memory, since this is
516 * the maximum mapped by the Linux kernel during initialization.
517 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200518#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Jon Loeliger9553df82007-10-16 15:26:51 -0500519
Jon Loeliger9553df82007-10-16 15:26:51 -0500520/*
521 * Internal Definitions
522 *
523 * Boot Flags
524 */
525#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
526#define BOOTFLAG_WARM 0x02 /* Software reboot */
527
528#if defined(CONFIG_CMD_KGDB)
529#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
530#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
531#endif
532
533/*
534 * Environment Configuration
535 */
536#define CONFIG_IPADDR 192.168.1.100
537
538#define CONFIG_HOSTNAME unknown
539#define CONFIG_ROOTPATH /opt/nfsroot
540#define CONFIG_BOOTFILE uImage
541#define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin
542
543#define CONFIG_SERVERIP 192.168.1.1
544#define CONFIG_GATEWAYIP 192.168.1.1
545#define CONFIG_NETMASK 255.255.255.0
546
547/* default location for tftp and bootm */
548#define CONFIG_LOADADDR 1000000
549
550#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
551#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
552
553#define CONFIG_BAUDRATE 115200
554
555#if defined(CONFIG_PCI1)
556#define PCI_ENV \
557 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
558 "echo e;md ${a}e00 9\0" \
559 "pci1regs=setenv a e0008; run pcireg\0" \
560 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
561 "pci d.w $b.0 56 1\0" \
562 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
563 "pci w.w $b.0 56 ffff\0" \
564 "pci1err=setenv a e0008; run pcierr\0" \
565 "pci1errc=setenv a e0008; run pcierrc\0"
566#else
567#define PCI_ENV ""
568#endif
569
570#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
571#define PCIE_ENV \
572 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
573 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
574 "pcie1regs=setenv a e000a; run pciereg\0" \
575 "pcie2regs=setenv a e0009; run pciereg\0" \
576 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
577 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
578 "pci d $b.0 130 1\0" \
579 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
580 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
581 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
582 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
583 "pcie1err=setenv a e000a; run pcieerr\0" \
584 "pcie2err=setenv a e0009; run pcieerr\0" \
585 "pcie1errc=setenv a e000a; run pcieerrc\0" \
586 "pcie2errc=setenv a e0009; run pcieerrc\0"
587#else
588#define PCIE_ENV ""
589#endif
590
591#define DMA_ENV \
592 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
593 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
594 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
595 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
596 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
597 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
598 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
599 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
600
York Sun18153382007-10-29 13:57:53 -0500601#ifdef ENV_DEBUG
Jon Loeliger9553df82007-10-16 15:26:51 -0500602#define CONFIG_EXTRA_ENV_SETTINGS \
603 "netdev=eth0\0" \
604 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
605 "tftpflash=tftpboot $loadaddr $uboot; " \
606 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
607 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
608 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
609 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
610 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
611 "consoledev=ttyS0\0" \
612 "ramdiskaddr=2000000\0" \
613 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
Jon Loeliger1df170f2008-01-04 12:07:27 -0600614 "fdtaddr=c00000\0" \
615 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
Jon Loeliger9553df82007-10-16 15:26:51 -0500616 "bdev=sda3\0" \
617 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
618 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
619 "maxcpus=1" \
620 "eoi=mw e00400b0 0\0" \
621 "iack=md e00400a0 1\0" \
622 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
623 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
624 "md ${a}f00 5\0" \
625 "ddr1regs=setenv a e0002; run ddrreg\0" \
626 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
627 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
628 "md ${a}e60 1; md ${a}ef0 1d\0" \
629 "guregs=setenv a e00e0; run gureg\0" \
630 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
631 "mcmregs=setenv a e0001; run mcmreg\0" \
632 "diuregs=md e002c000 1d\0" \
633 "dium=mw e002c01c\0" \
634 "diuerr=md e002c014 1\0" \
York Suna8778802007-10-29 13:58:39 -0500635 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 debug\0" \
636 "monitor=0-DVI\0" \
Jon Loeliger9553df82007-10-16 15:26:51 -0500637 "pmregs=md e00e1000 2b\0" \
638 "lawregs=md e0000c08 4b\0" \
639 "lbcregs=md e0005000 36\0" \
640 "dma0regs=md e0021100 12\0" \
641 "dma1regs=md e0021180 12\0" \
642 "dma2regs=md e0021200 12\0" \
643 "dma3regs=md e0021280 12\0" \
644 PCI_ENV \
645 PCIE_ENV \
646 DMA_ENV
York Sun18153382007-10-29 13:57:53 -0500647#else
648#define CONFIG_EXTRA_ENV_SETTINGS \
649 "netdev=eth0\0" \
650 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
651 "consoledev=ttyS0\0" \
652 "ramdiskaddr=2000000\0" \
653 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
Jon Loeliger1df170f2008-01-04 12:07:27 -0600654 "fdtaddr=c00000\0" \
655 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
York Suna8778802007-10-29 13:58:39 -0500656 "bdev=sda3\0" \
657 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0\0"\
658 "monitor=0-DVI\0"
York Sun18153382007-10-29 13:57:53 -0500659#endif
Jon Loeliger9553df82007-10-16 15:26:51 -0500660
661#define CONFIG_NFSBOOTCOMMAND \
662 "setenv bootargs root=/dev/nfs rw " \
663 "nfsroot=$serverip:$rootpath " \
664 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
665 "console=$consoledev,$baudrate $othbootargs;" \
666 "tftp $loadaddr $bootfile;" \
Jon Loeliger1df170f2008-01-04 12:07:27 -0600667 "tftp $fdtaddr $fdtfile;" \
668 "bootm $loadaddr - $fdtaddr"
Jon Loeliger9553df82007-10-16 15:26:51 -0500669
670#define CONFIG_RAMBOOTCOMMAND \
671 "setenv bootargs root=/dev/ram rw " \
672 "console=$consoledev,$baudrate $othbootargs;" \
673 "tftp $ramdiskaddr $ramdiskfile;" \
674 "tftp $loadaddr $bootfile;" \
Jon Loeliger1df170f2008-01-04 12:07:27 -0600675 "tftp $fdtaddr $fdtfile;" \
676 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Jon Loeliger9553df82007-10-16 15:26:51 -0500677
678#define CONFIG_BOOTCOMMAND \
679 "setenv bootargs root=/dev/$bdev rw " \
680 "console=$consoledev,$baudrate $othbootargs;" \
681 "tftp $loadaddr $bootfile;" \
Jon Loeliger1df170f2008-01-04 12:07:27 -0600682 "tftp $fdtaddr $fdtfile;" \
683 "bootm $loadaddr - $fdtaddr"
Jon Loeliger9553df82007-10-16 15:26:51 -0500684
685#endif /* __CONFIG_H */