blob: 64972317fba17f518a7e9724860a613ded4e1ada [file] [log] [blame]
Heiko Schocherde044362008-11-20 09:57:47 +01001/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
5 * Copyright (C) 2007 Logic Product Development, Inc.
6 * Peter Barada <peterb@logicpd.com>
7 *
8 * Copyright (C) 2007 MontaVista Software, Inc.
9 * Anton Vorontsov <avorontsov@ru.mvista.com>
10 *
11 * (C) Copyright 2008
12 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 */
19
20#ifndef __CONFIG_H
21#define __CONFIG_H
22
23/*
24 * High Level Configuration Options
25 */
26#define CONFIG_E300 1 /* E300 family */
27#define CONFIG_QE 1 /* Has QE */
Peter Tyser0f898602009-05-22 17:23:24 -050028#define CONFIG_MPC83xx 1 /* MPC83xx family */
Heiko Schocherde044362008-11-20 09:57:47 +010029#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
30#define CONFIG_KMETER1 1 /* KMETER1 board specific */
Heiko Schocher605f78e2009-02-24 11:30:44 +010031#define CONFIG_HOSTNAME kmeter1
Heiko Schocherde044362008-11-20 09:57:47 +010032
Heiko Schocher1e8f4e72008-11-20 09:59:09 +010033/* include common defines/options for all Keymile boards */
34#include "keymile-common.h"
35
Heiko Schocher8b1760e2010-01-20 09:05:32 +010036#define CONFIG_KM_UBI_PARTITION_NAME "ubi0"
37
Heiko Schocher4897ee32010-01-07 08:55:50 +010038#define MTDIDS_DEFAULT "nor0=boot"
39#define MTDPARTS_DEFAULT \
40 "mtdparts=boot:768k(u-boot),128k(env),128k(envred)," \
41 "-(" CONFIG_KM_UBI_PARTITION_NAME ")"
42
Heiko Schocher19f0e932009-02-24 11:30:34 +010043#define CONFIG_MISC_INIT_R 1
Heiko Schocherde044362008-11-20 09:57:47 +010044/*
45 * System Clock Setup
46 */
47#define CONFIG_83XX_CLKIN 66000000
48#define CONFIG_SYS_CLK_FREQ 66000000
49#define CONFIG_83XX_PCICLK 66000000
50
51/*
52 * Hardware Reset Configuration Word
53 */
54#define CONFIG_SYS_HRCW_LOW (\
55 HRCWL_CSB_TO_CLKIN_4X1 | \
56 HRCWL_CORE_TO_CSB_2X1 | \
57 HRCWL_CE_PLL_VCO_DIV_2 | \
58 HRCWL_CE_TO_PLL_1X6 )
59
60#define CONFIG_SYS_HRCW_HIGH (\
61 HRCWH_CORE_ENABLE | \
62 HRCWH_FROM_0X00000100 | \
Heiko Schocher605f78e2009-02-24 11:30:44 +010063 HRCWH_BOOTSEQ_DISABLE | \
Heiko Schocherde044362008-11-20 09:57:47 +010064 HRCWH_SW_WATCHDOG_DISABLE | \
65 HRCWH_ROM_LOC_LOCAL_16BIT | \
66 HRCWH_BIG_ENDIAN | \
Heiko Schocher605f78e2009-02-24 11:30:44 +010067 HRCWH_LALE_EARLY | \
Heiko Schocherde044362008-11-20 09:57:47 +010068 HRCWH_LDP_CLEAR )
69
70/*
71 * System IO Config
72 */
73#define CONFIG_SYS_SICRH 0x00000006
74#define CONFIG_SYS_SICRL 0x00000000
75
Heiko Schocherde044362008-11-20 09:57:47 +010076/*
77 * IMMR new address
78 */
79#define CONFIG_SYS_IMMR 0xE0000000
80
81/*
Heiko Schochera3f5da12010-01-07 08:56:00 +010082 * Bus Arbitration Configuration Register (ACR)
83 */
84#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
85#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
86#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
87#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
88
89/*
Heiko Schocherde044362008-11-20 09:57:47 +010090 * DDR Setup
91 */
92#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
93#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
94#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
95#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
96 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
97
98#define CFG_83XX_DDR_USES_CS0
99
100#undef CONFIG_DDR_ECC
101
102/*
103 * DDRCDR - DDR Control Driver Register
104 */
105
106#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */
107
108/*
109 * Manually set up DDR parameters
110 */
111#define CONFIG_DDR_II
Heiko Schocher118cbe32009-02-24 11:30:40 +0100112#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
113#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
Heiko Schocherde044362008-11-20 09:57:47 +0100114#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
115 CSCONFIG_ROW_BIT_13 | \
116 CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
117
118#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
119 SDRAM_CFG_SREN)
120#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
121#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
Heiko Schocher605f78e2009-02-24 11:30:44 +0100122#define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
123 (0x3cf << SDRAM_INTERVAL_REFINT_SHIFT))
Heiko Schocherde044362008-11-20 09:57:47 +0100124
Heiko Schocher605f78e2009-02-24 11:30:44 +0100125#define CONFIG_SYS_DDRCDR 0x40000001
126#define CONFIG_SYS_DDR_MODE 0x47860452
127#define CONFIG_SYS_DDR_MODE2 0x8080c000
Heiko Schocherde044362008-11-20 09:57:47 +0100128
129#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
130 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
131 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
132 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
133 (0 << TIMING_CFG0_WWT_SHIFT) | \
134 (0 << TIMING_CFG0_RRT_SHIFT) | \
135 (0 << TIMING_CFG0_WRT_SHIFT) | \
136 (0 << TIMING_CFG0_RWT_SHIFT))
137
Heiko Schocher605f78e2009-02-24 11:30:44 +0100138#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_50) | \
Heiko Schocherde044362008-11-20 09:57:47 +0100139 ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
Heiko Schocher605f78e2009-02-24 11:30:44 +0100140 ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
141 ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
142 ( 7 << TIMING_CFG1_REFREC_SHIFT) | \
143 ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
144 ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
145 ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
Heiko Schocherde044362008-11-20 09:57:47 +0100146
Heiko Schocher605f78e2009-02-24 11:30:44 +0100147#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
Heiko Schocherde044362008-11-20 09:57:47 +0100148 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
149 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
Heiko Schocher605f78e2009-02-24 11:30:44 +0100150 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
151 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
Heiko Schocherde044362008-11-20 09:57:47 +0100152 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
Heiko Schocher605f78e2009-02-24 11:30:44 +0100153 (5 << TIMING_CFG2_CPO_SHIFT))
Heiko Schocherde044362008-11-20 09:57:47 +0100154
155#define CONFIG_SYS_DDR_TIMING_3 0x00000000
156
157/*
Heiko Schocherde044362008-11-20 09:57:47 +0100158 * The reserved memory
159 */
160#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
161#define CONFIG_SYS_FLASH_BASE 0xF0000000
Heiko Schocher605f78e2009-02-24 11:30:44 +0100162#define CONFIG_SYS_PIGGY_BASE 0xE8000000
163#define CONFIG_SYS_PIGGY_SIZE 128
Heiko Schocherde044362008-11-20 09:57:47 +0100164#define CONFIG_SYS_PAXE_BASE 0xA0000000
Heiko Schocher605f78e2009-02-24 11:30:44 +0100165#define CONFIG_SYS_PAXE_SIZE 512
Heiko Schocherde044362008-11-20 09:57:47 +0100166
167#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
168#define CONFIG_SYS_RAMBOOT
169#else
170#undef CONFIG_SYS_RAMBOOT
171#endif
172
Kim Phillips4a9932a2009-07-07 18:04:21 -0500173#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
Heiko Schocherde044362008-11-20 09:57:47 +0100174
175/*
176 * Initial RAM Base Address Setup
177 */
178#define CONFIG_SYS_INIT_RAM_LOCK 1
179#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
180#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
181#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
182#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
183
184/*
185 * Local Bus Configuration & Clock Setup
186 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500187#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
188#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
189#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Heiko Schocherde044362008-11-20 09:57:47 +0100190
191/*
192 * Init Local Bus Memory Controller:
193 *
194 * Bank Bus Machine PortSz Size Device
195 * ---- --- ------- ------ ----- ------
196 * 0 Local GPCM 16 bit 256MB FLASH
Heiko Schocher605f78e2009-02-24 11:30:44 +0100197 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
198 * 3 Local GPCM 8 bit 512MB PAXE
Heiko Schocherde044362008-11-20 09:57:47 +0100199 *
200 */
201/*
202 * FLASH on the Local Bus
203 */
204#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
205#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
206#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
207#define CONFIG_SYS_FLASH_PROTECTION 1
208#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
209
210#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
211#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */
212
213#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
214 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
215 BR_V)
216
217#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
218 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
219 OR_GPCM_SCY_5 | \
220 OR_GPCM_TRLX | OR_GPCM_EAD)
221
Heiko Schocher4897ee32010-01-07 08:55:50 +0100222#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
Heiko Schocherde044362008-11-20 09:57:47 +0100223#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
Heiko Schocher4897ee32010-01-07 08:55:50 +0100224#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Heiko Schocherde044362008-11-20 09:57:47 +0100225
226#undef CONFIG_SYS_FLASH_CHECKSUM
227
228/*
229 * PRIO1/PIGGY on the local bus CS1
230 */
231#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE /* Window base at flash base */
Heiko Schocher605f78e2009-02-24 11:30:44 +0100232#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */
Heiko Schocherde044362008-11-20 09:57:47 +0100233
234#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \
235 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
236 BR_V)
Heiko Schocher605f78e2009-02-24 11:30:44 +0100237#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | /* 128MB */ \
Heiko Schocherde044362008-11-20 09:57:47 +0100238 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
239 OR_GPCM_SCY_2 | \
240 OR_GPCM_TRLX | OR_GPCM_EAD)
241
242/*
243 * PAXE on the local bus CS3
244 */
245#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE /* Window base at flash base */
Heiko Schocher605f78e2009-02-24 11:30:44 +0100246#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
Heiko Schocherde044362008-11-20 09:57:47 +0100247
248#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \
249 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
250 BR_V)
251#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
252 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
253 OR_GPCM_SCY_2 | \
254 OR_GPCM_TRLX | OR_GPCM_EAD)
255
256/*
257 * Serial Port
258 */
259#define CONFIG_CONS_INDEX 1
260#undef CONFIG_SERIAL_SOFTWARE_FIFO
261#define CONFIG_SYS_NS16550
262#define CONFIG_SYS_NS16550_SERIAL
263#define CONFIG_SYS_NS16550_REG_SIZE 1
264#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
265
Heiko Schocherde044362008-11-20 09:57:47 +0100266#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
267#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
268
269/* Pass open firmware flat tree */
270#define CONFIG_OF_LIBFDT 1
271#define CONFIG_OF_BOARD_SETUP 1
272#define CONFIG_OF_STDOUT_VIA_ALIAS
273
274/*
275 * General PCI
276 * Addresses are mapped 1-1.
277 */
278#undef CONFIG_PCI /* No PCI */
279
280#ifndef CONFIG_NET_MULTI
281#define CONFIG_NET_MULTI 1
282#endif
Heiko Schocherde044362008-11-20 09:57:47 +0100283/*
284 * QE UEC ethernet configuration
285 */
286#define CONFIG_UEC_ETH
287#define CONFIG_ETHPRIME "FSL UEC0"
288
289#define CONFIG_UEC_ETH1 /* GETH1 */
290#define UEC_VERBOSE_DEBUG 1
291
292#ifdef CONFIG_UEC_ETH1
293#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
294#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
295#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
296#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
297#define CONFIG_SYS_UEC1_PHY_ADDR 0
Heiko Schocher582c55a2010-01-20 09:04:28 +0100298#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII
299#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
Heiko Schocherde044362008-11-20 09:57:47 +0100300#endif
301
302/*
303 * Environment
304 */
305
306#ifndef CONFIG_SYS_RAMBOOT
307#define CONFIG_ENV_IS_IN_FLASH 1
308#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
309#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
Heiko Schocherde044362008-11-20 09:57:47 +0100310#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
311
312/* Address and size of Redundant Environment Sector */
313#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
314#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
315
316#else /* CFG_RAMBOOT */
317#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
318#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Heiko Schocher605f78e2009-02-24 11:30:44 +0100319#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Heiko Schocherde044362008-11-20 09:57:47 +0100320#define CONFIG_ENV_SIZE 0x2000
321#endif /* CFG_RAMBOOT */
322
Heiko Schocher19f0e932009-02-24 11:30:34 +0100323/* I2C */
324#define CONFIG_HARD_I2C /* I2C with hardware support */
325#undef CONFIG_SOFT_I2C /* I2C bit-banged */
326#define CONFIG_FSL_I2C
327#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */
328#define CONFIG_SYS_I2C_SLAVE 0x7F
329#define CONFIG_SYS_I2C_OFFSET 0x3000
330#define CONFIG_I2C_MULTI_BUS 1
Heiko Schocher19f0e932009-02-24 11:30:34 +0100331#define CONFIG_I2C_MUX 1
332
333/* EEprom support */
334#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Heiko Schocher19f0e932009-02-24 11:30:34 +0100335
336/* I2C SYSMON (LM75, AD7414 is almost compatible) */
337#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
338#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */
339#define CONFIG_SYS_DTT_MAX_TEMP 70
340#define CONFIG_SYS_DTT_LOW_TEMP -30
341#define CONFIG_SYS_DTT_HYSTERESIS 3
Heiko Schocherdc71b242009-07-09 12:04:18 +0200342#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
Heiko Schocher19f0e932009-02-24 11:30:34 +0100343
Heiko Schocherde425092009-07-21 17:13:40 +0200344#if defined(CONFIG_CMD_NAND)
345#define CONFIG_NAND_KMETER1
346#define CONFIG_SYS_MAX_NAND_DEVICE 1
347#define CONFIG_SYS_NAND_BASE CONFIG_SYS_PIGGY_BASE
348#endif
349
Heiko Schocherde044362008-11-20 09:57:47 +0100350#if defined(CONFIG_PCI)
351#define CONFIG_CMD_PCI
352#endif
353
354#if defined(CFG_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500355#undef CONFIG_CMD_SAVEENV
Heiko Schocherde044362008-11-20 09:57:47 +0100356#undef CONFIG_CMD_LOADS
357#endif
358
Heiko Schocherde044362008-11-20 09:57:47 +0100359/*
360 * For booting Linux, the board info and command line data
361 * have to be in the first 8 MB of memory, since this is
362 * the maximum mapped by the Linux kernel during initialization.
363 */
364#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
365
366/*
367 * Core HID Setup
368 */
369#define CONFIG_SYS_HID0_INIT 0x000000000
Kim Phillips1a2e2032010-04-20 19:37:54 -0500370#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
371 HID0_ENABLE_INSTRUCTION_CACHE)
Heiko Schocherde044362008-11-20 09:57:47 +0100372#define CONFIG_SYS_HID2 HID2_HBE
373
374/*
375 * MMU Setup
376 */
377
378#define CONFIG_HIGH_BATS 1 /* High BATs supported */
379
380/* DDR: cache cacheable */
381#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
382 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
383#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
384#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
385#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
386
387/* IMMRBAR & PCI IO: cache-inhibit and guarded */
388#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
389 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
390#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
391#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
392#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
393
394/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
395#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
Heiko Schocher605f78e2009-02-24 11:30:44 +0100396#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
Heiko Schocherde044362008-11-20 09:57:47 +0100397#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
398 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
399#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
400
401/* FLASH: icache cacheable, but dcache-inhibit and guarded */
402#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
403#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
404#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
405 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
406#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
407
408/* Stack in dcache: cacheable, no memory coherence */
409#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
410#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
411#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
412#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
413
414/* PAXE: icache cacheable, but dcache-inhibit and guarded */
415#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
Heiko Schocher605f78e2009-02-24 11:30:44 +0100416#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Heiko Schocherde044362008-11-20 09:57:47 +0100417#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
418 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
419#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
420
421#ifdef CONFIG_PCI
422/* PCI MEM space: cacheable */
423#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
424#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
425#define CFG_DBAT6L CFG_IBAT6L
426#define CFG_DBAT6U CFG_IBAT6U
427/* PCI MMIO space: cache-inhibit and guarded */
428#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
429 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
430#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
431#define CFG_DBAT7L CFG_IBAT7L
432#define CFG_DBAT7U CFG_IBAT7U
433#else /* CONFIG_PCI */
434#define CONFIG_SYS_IBAT6L (0)
435#define CONFIG_SYS_IBAT6U (0)
436#define CONFIG_SYS_IBAT7L (0)
437#define CONFIG_SYS_IBAT7U (0)
438#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
439#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
440#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
441#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
442#endif /* CONFIG_PCI */
443
444/*
445 * Internal Definitions
446 *
447 * Boot Flags
448 */
449#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
450#define BOOTFLAG_WARM 0x02 /* Software reboot */
451
Heiko Schocher605f78e2009-02-24 11:30:44 +0100452#define BOOTFLASH_START F0000000
453
454#define CONFIG_PRAM 512 /* protected RAM [KBytes] */
455
Heiko Schocherde044362008-11-20 09:57:47 +0100456/*
457 * Environment Configuration
458 */
459#define CONFIG_ENV_OVERWRITE
Heiko Schocher605f78e2009-02-24 11:30:44 +0100460#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
461#define CONFIG_KM_DEF_ENV "km-common=empty\0"
Heiko Schocherde044362008-11-20 09:57:47 +0100462#endif
463
Heiko Schocherde044362008-11-20 09:57:47 +0100464#define CONFIG_EXTRA_ENV_SETTINGS \
Heiko Schocher605f78e2009-02-24 11:30:44 +0100465 CONFIG_KM_DEF_ENV \
Heiko Schocherde044362008-11-20 09:57:47 +0100466 "rootpath=/opt/eldk/ppc_82xx\0" \
Heiko Schocher364123d2009-03-12 07:37:18 +0100467 "addcon=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
Heiko Schocherde044362008-11-20 09:57:47 +0100468 "ramdisk_file=/tftpboot/kmeter1/uRamdisk\0" \
Heiko Schocherde044362008-11-20 09:57:47 +0100469 "loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0" \
470 "loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0" \
Heiko Schocher364123d2009-03-12 07:37:18 +0100471 "loadkernel=tftp ${kernel_addr_r} ${bootfile}\0" \
Heiko Schocherde044362008-11-20 09:57:47 +0100472 "unlock=yes\0" \
Heiko Schocher364123d2009-03-12 07:37:18 +0100473 "fdt_addr=F0080000\0" \
474 "kernel_addr=F00a0000\0" \
475 "ramdisk_addr=F03a0000\0" \
476 "ramdisk_addr_r=F10000\0" \
Heiko Schocher19f0e932009-02-24 11:30:34 +0100477 "EEprom_ivm=pca9547:70:9\0" \
478 "dtt_bus=pca9547:70:a\0" \
Heiko Schocher605f78e2009-02-24 11:30:44 +0100479 "mtdids=nor0=app \0" \
480 "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \
Heiko Schocherde044362008-11-20 09:57:47 +0100481 ""
482
Heiko Schocher605f78e2009-02-24 11:30:44 +0100483#if defined(CONFIG_UEC_ETH)
484#define CONFIG_HAS_ETH0
485#endif
486
Heiko Schocherde044362008-11-20 09:57:47 +0100487#endif /* __CONFIG_H */