blob: 348630faf381d67275c75872ca051978f8bab717 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stephan Linz09aac752012-07-29 00:25:35 +02002/*
3 * Xilinx SPI driver
4 *
Jagan Tekia7b6ef02015-06-27 00:51:27 +05305 * Supports 8 bit SPI transfers only, with or w/o FIFO
Stephan Linz09aac752012-07-29 00:25:35 +02006 *
Jagan Tekia7b6ef02015-06-27 00:51:27 +05307 * Based on bfin_spi.c, by way of altera_spi.c
Jagan Teki9505c362015-06-29 13:15:18 +05308 * Copyright (c) 2015 Jagan Teki <jteki@openedev.com>
Stephan Linz09aac752012-07-29 00:25:35 +02009 * Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
Jagan Tekia7b6ef02015-06-27 00:51:27 +053010 * Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
11 * Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
12 * Copyright (c) 2005-2008 Analog Devices Inc.
Stephan Linz09aac752012-07-29 00:25:35 +020013 */
Jagan Tekia7b6ef02015-06-27 00:51:27 +053014
Stephan Linz09aac752012-07-29 00:25:35 +020015#include <config.h>
16#include <common.h>
Jagan Teki9505c362015-06-29 13:15:18 +053017#include <dm.h>
18#include <errno.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060019#include <log.h>
Stephan Linz09aac752012-07-29 00:25:35 +020020#include <malloc.h>
21#include <spi.h>
Jagan Teki5f24d122015-06-27 00:51:37 +053022#include <asm/io.h>
Vipul Kumar0c0de582018-06-30 08:15:18 +053023#include <wait_bit.h>
Simon Glasscd93d622020-05-10 11:40:13 -060024#include <linux/bitops.h>
Stephan Linz09aac752012-07-29 00:25:35 +020025
Jagan Tekif93542a2015-06-27 00:51:26 +053026/*
Jagan Tekia7b6ef02015-06-27 00:51:27 +053027 * [0]: http://www.xilinx.com/support/documentation
Jagan Tekif93542a2015-06-27 00:51:26 +053028 *
Jagan Tekia7b6ef02015-06-27 00:51:27 +053029 * Xilinx SPI Register Definitions
Jagan Tekif93542a2015-06-27 00:51:26 +053030 * [1]: [0]/ip_documentation/xps_spi.pdf
31 * page 8, Register Descriptions
32 * [2]: [0]/ip_documentation/axi_spi_ds742.pdf
33 * page 7, Register Overview Table
34 */
Jagan Tekif93542a2015-06-27 00:51:26 +053035
36/* SPI Control Register (spicr), [1] p9, [2] p8 */
Jagan Teki5ea392d2015-10-23 01:39:31 +053037#define SPICR_LSB_FIRST BIT(9)
38#define SPICR_MASTER_INHIBIT BIT(8)
39#define SPICR_MANUAL_SS BIT(7)
40#define SPICR_RXFIFO_RESEST BIT(6)
41#define SPICR_TXFIFO_RESEST BIT(5)
42#define SPICR_CPHA BIT(4)
43#define SPICR_CPOL BIT(3)
44#define SPICR_MASTER_MODE BIT(2)
45#define SPICR_SPE BIT(1)
46#define SPICR_LOOP BIT(0)
Jagan Tekif93542a2015-06-27 00:51:26 +053047
48/* SPI Status Register (spisr), [1] p11, [2] p10 */
Jagan Teki5ea392d2015-10-23 01:39:31 +053049#define SPISR_SLAVE_MODE_SELECT BIT(5)
50#define SPISR_MODF BIT(4)
51#define SPISR_TX_FULL BIT(3)
52#define SPISR_TX_EMPTY BIT(2)
53#define SPISR_RX_FULL BIT(1)
54#define SPISR_RX_EMPTY BIT(0)
Jagan Tekif93542a2015-06-27 00:51:26 +053055
56/* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
Jagan Tekid2436302015-10-23 01:03:44 +053057#define SPIDTR_8BIT_MASK GENMASK(7, 0)
58#define SPIDTR_16BIT_MASK GENMASK(15, 0)
59#define SPIDTR_32BIT_MASK GENMASK(31, 0)
Jagan Tekif93542a2015-06-27 00:51:26 +053060
61/* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */
Jagan Tekid2436302015-10-23 01:03:44 +053062#define SPIDRR_8BIT_MASK GENMASK(7, 0)
63#define SPIDRR_16BIT_MASK GENMASK(15, 0)
64#define SPIDRR_32BIT_MASK GENMASK(31, 0)
Jagan Tekif93542a2015-06-27 00:51:26 +053065
66/* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
67#define SPISSR_MASK(cs) (1 << (cs))
68#define SPISSR_ACT(cs) ~SPISSR_MASK(cs)
69#define SPISSR_OFF ~0UL
70
Jagan Tekif93542a2015-06-27 00:51:26 +053071/* SPI Software Reset Register (ssr) */
72#define SPISSR_RESET_VALUE 0x0a
73
Jagan Tekia7b6ef02015-06-27 00:51:27 +053074#define XILSPI_MAX_XFER_BITS 8
75#define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | SPICR_MASTER_MODE | \
76 SPICR_SPE)
77#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
78
Ashok Reddy Somaf44bd3b2020-05-18 01:11:00 -060079#define XILINX_SPI_IDLE_VAL GENMASK(7, 0)
Jagan Tekia7b6ef02015-06-27 00:51:27 +053080
Vipul Kumar0c0de582018-06-30 08:15:18 +053081#define XILINX_SPISR_TIMEOUT 10000 /* in milliseconds */
82
Jagan Tekia7b6ef02015-06-27 00:51:27 +053083/* xilinx spi register set */
Jagan Teki9505c362015-06-29 13:15:18 +053084struct xilinx_spi_regs {
Jagan Tekia7b6ef02015-06-27 00:51:27 +053085 u32 __space0__[7];
86 u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */
87 u32 ipisr; /* IP Interrupt Status Register (IPISR) */
88 u32 __space1__;
89 u32 ipier; /* IP Interrupt Enable Register (IPIER) */
90 u32 __space2__[5];
91 u32 srr; /* Softare Reset Register (SRR) */
92 u32 __space3__[7];
93 u32 spicr; /* SPI Control Register (SPICR) */
94 u32 spisr; /* SPI Status Register (SPISR) */
95 u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */
96 u32 spidrr; /* SPI Data Receive Register (SPIDRR) */
97 u32 spissr; /* SPI Slave Select Register (SPISSR) */
98 u32 spitfor; /* SPI Transmit FIFO Occupancy Register (SPITFOR) */
99 u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */
100};
101
Jagan Teki9505c362015-06-29 13:15:18 +0530102/* xilinx spi priv */
103struct xilinx_spi_priv {
104 struct xilinx_spi_regs *regs;
Jagan Tekif93542a2015-06-27 00:51:26 +0530105 unsigned int freq;
106 unsigned int mode;
Vipul Kumar0c0de582018-06-30 08:15:18 +0530107 unsigned int fifo_depth;
Vipul Kumar83ce6462018-06-30 08:15:19 +0530108 u8 startup;
Jagan Tekif93542a2015-06-27 00:51:26 +0530109};
110
Jagan Teki9505c362015-06-29 13:15:18 +0530111static int xilinx_spi_probe(struct udevice *bus)
Stephan Linz09aac752012-07-29 00:25:35 +0200112{
Jagan Teki9505c362015-06-29 13:15:18 +0530113 struct xilinx_spi_priv *priv = dev_get_priv(bus);
114 struct xilinx_spi_regs *regs = priv->regs;
Stephan Linz09aac752012-07-29 00:25:35 +0200115
Vipul Kumar6e9d9fc2018-06-30 08:15:20 +0530116 priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);
Stephan Linz09aac752012-07-29 00:25:35 +0200117
Vipul Kumar6e9d9fc2018-06-30 08:15:20 +0530118 priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);
Vipul Kumar0c0de582018-06-30 08:15:18 +0530119
Jagan Teki9505c362015-06-29 13:15:18 +0530120 writel(SPISSR_RESET_VALUE, &regs->srr);
Stephan Linz09aac752012-07-29 00:25:35 +0200121
Stephan Linz09aac752012-07-29 00:25:35 +0200122 return 0;
123}
124
Jagan Teki9505c362015-06-29 13:15:18 +0530125static void spi_cs_activate(struct udevice *dev, uint cs)
Stephan Linz09aac752012-07-29 00:25:35 +0200126{
Jagan Teki9505c362015-06-29 13:15:18 +0530127 struct udevice *bus = dev_get_parent(dev);
128 struct xilinx_spi_priv *priv = dev_get_priv(bus);
129 struct xilinx_spi_regs *regs = priv->regs;
Stephan Linz09aac752012-07-29 00:25:35 +0200130
Jagan Teki9505c362015-06-29 13:15:18 +0530131 writel(SPISSR_ACT(cs), &regs->spissr);
Stephan Linz09aac752012-07-29 00:25:35 +0200132}
133
Jagan Teki9505c362015-06-29 13:15:18 +0530134static void spi_cs_deactivate(struct udevice *dev)
Stephan Linz09aac752012-07-29 00:25:35 +0200135{
Jagan Teki9505c362015-06-29 13:15:18 +0530136 struct udevice *bus = dev_get_parent(dev);
137 struct xilinx_spi_priv *priv = dev_get_priv(bus);
138 struct xilinx_spi_regs *regs = priv->regs;
139
140 writel(SPISSR_OFF, &regs->spissr);
141}
142
143static int xilinx_spi_claim_bus(struct udevice *dev)
144{
145 struct udevice *bus = dev_get_parent(dev);
146 struct xilinx_spi_priv *priv = dev_get_priv(bus);
147 struct xilinx_spi_regs *regs = priv->regs;
148
149 writel(SPISSR_OFF, &regs->spissr);
150 writel(XILSPI_SPICR_DFLT_ON, &regs->spicr);
151
152 return 0;
153}
154
155static int xilinx_spi_release_bus(struct udevice *dev)
156{
157 struct udevice *bus = dev_get_parent(dev);
158 struct xilinx_spi_priv *priv = dev_get_priv(bus);
159 struct xilinx_spi_regs *regs = priv->regs;
160
161 writel(SPISSR_OFF, &regs->spissr);
162 writel(XILSPI_SPICR_DFLT_OFF, &regs->spicr);
163
164 return 0;
165}
166
Vipul Kumar0c0de582018-06-30 08:15:18 +0530167static u32 xilinx_spi_fill_txfifo(struct udevice *bus, const u8 *txp,
168 u32 txbytes)
169{
170 struct xilinx_spi_priv *priv = dev_get_priv(bus);
171 struct xilinx_spi_regs *regs = priv->regs;
172 unsigned char d;
173 u32 i = 0;
174
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) &&
176 i < priv->fifo_depth) {
Ashok Reddy Somaf44bd3b2020-05-18 01:11:00 -0600177 d = txp ? *txp++ : XILINX_SPI_IDLE_VAL;
Vipul Kumar0c0de582018-06-30 08:15:18 +0530178 debug("spi_xfer: tx:%x ", d);
179 /* write out and wait for processing (receive data) */
180 writel(d & SPIDTR_8BIT_MASK, &regs->spidtr);
181 txbytes--;
182 i++;
183 }
184
185 return i;
186}
187
188static u32 xilinx_spi_read_rxfifo(struct udevice *bus, u8 *rxp, u32 rxbytes)
189{
190 struct xilinx_spi_priv *priv = dev_get_priv(bus);
191 struct xilinx_spi_regs *regs = priv->regs;
192 unsigned char d;
193 unsigned int i = 0;
194
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) {
196 d = readl(&regs->spidrr) & SPIDRR_8BIT_MASK;
197 if (rxp)
198 *rxp++ = d;
199 debug("spi_xfer: rx:%x\n", d);
200 rxbytes--;
201 i++;
202 }
203 debug("Rx_done\n");
204
205 return i;
206}
207
Vipul Kumar83ce6462018-06-30 08:15:19 +0530208static void xilinx_spi_startup_block(struct udevice *dev, unsigned int bytes,
209 const void *dout, void *din)
210{
211 struct udevice *bus = dev_get_parent(dev);
212 struct xilinx_spi_priv *priv = dev_get_priv(bus);
213 struct xilinx_spi_regs *regs = priv->regs;
214 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
215 const unsigned char *txp = dout;
216 unsigned char *rxp = din;
217 u32 reg, count;
218 u32 txbytes = bytes;
219 u32 rxbytes = bytes;
220
221 /*
222 * This loop runs two times. First time to send the command.
223 * Second time to transfer data. After transferring data,
224 * it sets txp to the initial value for the normal operation.
225 */
226 for ( ; priv->startup < 2; priv->startup++) {
227 count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
228 reg = readl(&regs->spicr) & ~SPICR_MASTER_INHIBIT;
229 writel(reg, &regs->spicr);
230 count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
231 txp = din;
232
233 if (priv->startup) {
234 spi_cs_deactivate(dev);
235 spi_cs_activate(dev, slave_plat->cs);
236 txp = dout;
237 }
238 }
239}
240
Jagan Teki9505c362015-06-29 13:15:18 +0530241static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
242 const void *dout, void *din, unsigned long flags)
243{
244 struct udevice *bus = dev_get_parent(dev);
245 struct xilinx_spi_priv *priv = dev_get_priv(bus);
246 struct xilinx_spi_regs *regs = priv->regs;
247 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
Stephan Linz09aac752012-07-29 00:25:35 +0200248 /* assume spi core configured to do 8 bit transfers */
249 unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
250 const unsigned char *txp = dout;
251 unsigned char *rxp = din;
Vipul Kumar0c0de582018-06-30 08:15:18 +0530252 u32 txbytes = bytes;
253 u32 rxbytes = bytes;
254 u32 reg, count, timeout;
255 int ret;
Stephan Linz09aac752012-07-29 00:25:35 +0200256
Jagan Tekia7b6ef02015-06-27 00:51:27 +0530257 debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n",
Jagan Teki9505c362015-06-29 13:15:18 +0530258 bus->seq, slave_plat->cs, bitlen, bytes, flags);
Jagan Tekia7b6ef02015-06-27 00:51:27 +0530259
Stephan Linz09aac752012-07-29 00:25:35 +0200260 if (bitlen == 0)
261 goto done;
262
263 if (bitlen % XILSPI_MAX_XFER_BITS) {
Jagan Tekia7b6ef02015-06-27 00:51:27 +0530264 printf("XILSPI warning: Not a multiple of %d bits\n",
265 XILSPI_MAX_XFER_BITS);
Stephan Linz09aac752012-07-29 00:25:35 +0200266 flags |= SPI_XFER_END;
267 goto done;
268 }
269
Stephan Linz09aac752012-07-29 00:25:35 +0200270 if (flags & SPI_XFER_BEGIN)
Jagan Teki9505c362015-06-29 13:15:18 +0530271 spi_cs_activate(dev, slave_plat->cs);
Stephan Linz09aac752012-07-29 00:25:35 +0200272
Vipul Kumar83ce6462018-06-30 08:15:19 +0530273 /*
274 * This is the work around for the startup block issue in
275 * the spi controller. SPI clock is passing through STARTUP
276 * block to FLASH. STARTUP block don't provide clock as soon
277 * as QSPI provides command. So first command fails.
278 */
279 xilinx_spi_startup_block(dev, bytes, dout, din);
Stephan Linz09aac752012-07-29 00:25:35 +0200280
Vipul Kumar0c0de582018-06-30 08:15:18 +0530281 while (txbytes && rxbytes) {
282 count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
283 reg = readl(&regs->spicr) & ~SPICR_MASTER_INHIBIT;
284 writel(reg, &regs->spicr);
285 txbytes -= count;
286 if (txp)
287 txp += count;
Stephan Linz09aac752012-07-29 00:25:35 +0200288
Vipul Kumar0c0de582018-06-30 08:15:18 +0530289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true,
290 XILINX_SPISR_TIMEOUT, false);
291 if (ret < 0) {
Jagan Tekia7b6ef02015-06-27 00:51:27 +0530292 printf("XILSPI error: Xfer timeout\n");
Vipul Kumar0c0de582018-06-30 08:15:18 +0530293 return ret;
Stephan Linz09aac752012-07-29 00:25:35 +0200294 }
295
Vipul Kumar0c0de582018-06-30 08:15:18 +0530296 debug("txbytes:0x%x,txp:0x%p\n", txbytes, txp);
297 count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
298 rxbytes -= count;
Stephan Linz09aac752012-07-29 00:25:35 +0200299 if (rxp)
Vipul Kumar0c0de582018-06-30 08:15:18 +0530300 rxp += count;
301 debug("rxbytes:0x%x rxp:0x%p\n", rxbytes, rxp);
Stephan Linz09aac752012-07-29 00:25:35 +0200302 }
303
304 done:
305 if (flags & SPI_XFER_END)
Jagan Teki9505c362015-06-29 13:15:18 +0530306 spi_cs_deactivate(dev);
Stephan Linz09aac752012-07-29 00:25:35 +0200307
308 return 0;
309}
Jagan Teki9505c362015-06-29 13:15:18 +0530310
311static int xilinx_spi_set_speed(struct udevice *bus, uint speed)
312{
313 struct xilinx_spi_priv *priv = dev_get_priv(bus);
314
315 priv->freq = speed;
316
Jagan Tekid5f60732015-09-08 01:26:29 +0530317 debug("xilinx_spi_set_speed: regs=%p, speed=%d\n", priv->regs,
Jagan Teki9505c362015-06-29 13:15:18 +0530318 priv->freq);
319
320 return 0;
321}
322
323static int xilinx_spi_set_mode(struct udevice *bus, uint mode)
324{
325 struct xilinx_spi_priv *priv = dev_get_priv(bus);
326 struct xilinx_spi_regs *regs = priv->regs;
327 uint32_t spicr;
328
329 spicr = readl(&regs->spicr);
Jagan Tekid5f60732015-09-08 01:26:29 +0530330 if (mode & SPI_LSB_FIRST)
Jagan Teki9505c362015-06-29 13:15:18 +0530331 spicr |= SPICR_LSB_FIRST;
Jagan Tekid5f60732015-09-08 01:26:29 +0530332 if (mode & SPI_CPHA)
Jagan Teki9505c362015-06-29 13:15:18 +0530333 spicr |= SPICR_CPHA;
Jagan Tekid5f60732015-09-08 01:26:29 +0530334 if (mode & SPI_CPOL)
Jagan Teki9505c362015-06-29 13:15:18 +0530335 spicr |= SPICR_CPOL;
Jagan Tekid5f60732015-09-08 01:26:29 +0530336 if (mode & SPI_LOOP)
Jagan Teki9505c362015-06-29 13:15:18 +0530337 spicr |= SPICR_LOOP;
338
339 writel(spicr, &regs->spicr);
340 priv->mode = mode;
341
342 debug("xilinx_spi_set_mode: regs=%p, mode=%d\n", priv->regs,
343 priv->mode);
344
345 return 0;
346}
347
348static const struct dm_spi_ops xilinx_spi_ops = {
349 .claim_bus = xilinx_spi_claim_bus,
350 .release_bus = xilinx_spi_release_bus,
351 .xfer = xilinx_spi_xfer,
352 .set_speed = xilinx_spi_set_speed,
353 .set_mode = xilinx_spi_set_mode,
354};
355
356static const struct udevice_id xilinx_spi_ids[] = {
Michal Simek76de51a2015-12-11 12:41:14 +0100357 { .compatible = "xlnx,xps-spi-2.00.a" },
358 { .compatible = "xlnx,xps-spi-2.00.b" },
Jagan Teki9505c362015-06-29 13:15:18 +0530359 { }
360};
361
362U_BOOT_DRIVER(xilinx_spi) = {
363 .name = "xilinx_spi",
364 .id = UCLASS_SPI,
365 .of_match = xilinx_spi_ids,
366 .ops = &xilinx_spi_ops,
367 .priv_auto_alloc_size = sizeof(struct xilinx_spi_priv),
368 .probe = xilinx_spi_probe,
369};