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wdenk4e5ca3e2003-12-08 01:34:36 +00001/*
wdenkbf9e3b32004-02-12 00:47:09 +00002 * (C) Copyright 2003
3 * Josef Baumgartner <josef.baumgartner@telex.de>
wdenk4e5ca3e2003-12-08 01:34:36 +00004 *
TsiChungLiewa1436a82007-08-16 13:20:50 -05005 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * Hayden Fraser (Hayden.Fraser@freescale.com)
7 *
wdenk4e5ca3e2003-12-08 01:34:36 +00008 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <asm/processor.h>
TsiChungLiewa1436a82007-08-16 13:20:50 -050029#include <asm/immap.h>
wdenk4e5ca3e2003-12-08 01:34:36 +000030
Wolfgang Denkd87080b2006-03-31 18:32:53 +020031DECLARE_GLOBAL_DATA_PTR;
32
wdenkbf9e3b32004-02-12 00:47:09 +000033/*
34 * get_clocks() fills in gd->cpu_clock and gd->bus_clk
35 */
36int get_clocks (void)
wdenk4e5ca3e2003-12-08 01:34:36 +000037{
TsiChungLiewa1436a82007-08-16 13:20:50 -050038#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
39 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
40 unsigned long pllcr;
41
42#ifndef CFG_PLL_BYPASS
43
stroese8c725b92004-12-16 18:09:49 +000044#ifdef CONFIG_M5249
TsiChungLiewa1436a82007-08-16 13:20:50 -050045 /* Setup the PLL to run at the specified speed */
46#ifdef CFG_FAST_CLK
47 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
48#else
49 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
50#endif
51#endif /* CONFIG_M5249 */
52
53#ifdef CONFIG_M5253
54 pllcr = CFG_PLLCR;
55#endif /* CONFIG_M5253 */
56
57 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
58 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */
59 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */
60 pllcr ^= 0x00000001; /* Set pll bypass to 1 */
61 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
62 udelay(0x20); /* Wait for a lock ... */
63#endif /* #ifndef CFG_PLL_BYPASS */
64
65#endif /* CONFIG_M5249 || CONFIG_M5253 */
66
Matthew Fettkef71d9d92008-02-04 15:38:20 -060067#if defined(CONFIG_M5275)
68 volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
69
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -070070 /* Setup PLL */
71 pll->syncr = 0x01080000;
72 while (!(pll->synsr & FMPLL_SYNSR_LOCK)
73 ;
74 pll->syncr = 0x01000000;
75 while (!(pll->synsr & FMPLL_SYNSR_LOCK))
76 ;
Matthew Fettkef71d9d92008-02-04 15:38:20 -060077#endif
78
TsiChungLiewa1436a82007-08-16 13:20:50 -050079 gd->cpu_clk = CFG_CLK;
Matthew Fettkef71d9d92008-02-04 15:38:20 -060080#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275)
stroese8c725b92004-12-16 18:09:49 +000081 gd->bus_clk = gd->cpu_clk / 2;
82#else
wdenkbf9e3b32004-02-12 00:47:09 +000083 gd->bus_clk = gd->cpu_clk;
stroese8c725b92004-12-16 18:09:49 +000084#endif
wdenkbf9e3b32004-02-12 00:47:09 +000085 return (0);
wdenk4e5ca3e2003-12-08 01:34:36 +000086}