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Vikas Manochabf1ae442017-04-10 15:02:51 -07001/*
2 * (C) Copyright 2017
3 * Vikas Manocha, <vikas.manocha@st.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
Vikas Manochad0b24c12017-04-10 15:02:55 -07009#include <clk.h>
Vikas Manocha910a52e2017-04-10 15:02:52 -070010#include <dm.h>
11#include <ram.h>
Vikas Manochabf1ae442017-04-10 15:02:51 -070012#include <asm/io.h>
Vikas Manochabf1ae442017-04-10 15:02:51 -070013
Vikas Manocha6c9a1002017-04-10 15:02:56 -070014DECLARE_GLOBAL_DATA_PTR;
15
Patrice Chotard9242ece2017-07-18 17:37:24 +020016struct stm32_fmc_regs {
Patrice Chotard1421e0a2017-07-18 17:37:25 +020017 /* 0x0 */
18 u32 bcr1; /* NOR/PSRAM Chip select control register 1 */
19 u32 btr1; /* SRAM/NOR-Flash Chip select timing register 1 */
20 u32 bcr2; /* NOR/PSRAM Chip select Control register 2 */
21 u32 btr2; /* SRAM/NOR-Flash Chip select timing register 2 */
22 u32 bcr3; /* NOR/PSRAMChip select Control register 3 */
23 u32 btr3; /* SRAM/NOR-Flash Chip select timing register 3 */
24 u32 bcr4; /* NOR/PSRAM Chip select Control register 4 */
25 u32 btr4; /* SRAM/NOR-Flash Chip select timing register 4 */
26 u32 reserved1[24];
Patrice Chotard9242ece2017-07-18 17:37:24 +020027
Patrice Chotard1421e0a2017-07-18 17:37:25 +020028 /* 0x80 */
29 u32 pcr; /* NAND Flash control register */
30 u32 sr; /* FIFO status and interrupt register */
31 u32 pmem; /* Common memory space timing register */
32 u32 patt; /* Attribute memory space timing registers */
33 u32 reserved2[1];
34 u32 eccr; /* ECC result registers */
35 u32 reserved3[27];
36
37 /* 0x104 */
38 u32 bwtr1; /* SRAM/NOR-Flash write timing register 1 */
39 u32 reserved4[1];
40 u32 bwtr2; /* SRAM/NOR-Flash write timing register 2 */
41 u32 reserved5[1];
42 u32 bwtr3; /* SRAM/NOR-Flash write timing register 3 */
43 u32 reserved6[1];
44 u32 bwtr4; /* SRAM/NOR-Flash write timing register 4 */
45 u32 reserved7[8];
46
47 /* 0x140 */
48 u32 sdcr1; /* SDRAM Control register 1 */
49 u32 sdcr2; /* SDRAM Control register 2 */
50 u32 sdtr1; /* SDRAM Timing register 1 */
51 u32 sdtr2; /* SDRAM Timing register 2 */
52 u32 sdcmr; /* SDRAM Mode register */
53 u32 sdrtr; /* SDRAM Refresh timing register */
54 u32 sdsr; /* SDRAM Status register */
55};
Patrice Chotard9242ece2017-07-18 17:37:24 +020056
Patrice Chotard70166512017-07-18 17:37:29 +020057/*
58 * NOR/PSRAM Control register BCR1
59 * FMC controller Enable, only availabe for H7
60 */
61#define FMC_BCR1_FMCEN BIT(31)
62
Patrice Chotard9242ece2017-07-18 17:37:24 +020063/* Control register SDCR */
64#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
65#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */
66#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */
67#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */
68#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */
69#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */
70#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */
71#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */
72#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */
73
74/* Timings register SDTR */
75#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */
76#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */
77#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */
78#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */
79#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */
80#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */
81#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */
82
83#define FMC_SDCMR_NRFS_SHIFT 5
84
85#define FMC_SDCMR_MODE_NORMAL 0
86#define FMC_SDCMR_MODE_START_CLOCK 1
87#define FMC_SDCMR_MODE_PRECHARGE 2
88#define FMC_SDCMR_MODE_AUTOREFRESH 3
89#define FMC_SDCMR_MODE_WRITE_MODE 4
90#define FMC_SDCMR_MODE_SELFREFRESH 5
91#define FMC_SDCMR_MODE_POWERDOWN 6
92
93#define FMC_SDCMR_BANK_1 BIT(4)
94#define FMC_SDCMR_BANK_2 BIT(3)
95
96#define FMC_SDCMR_MODE_REGISTER_SHIFT 9
97
98#define FMC_SDSR_BUSY BIT(5)
99
Patrice Chotard1421e0a2017-07-18 17:37:25 +0200100#define FMC_BUSY_WAIT(regs) do { \
Patrice Chotard9242ece2017-07-18 17:37:24 +0200101 __asm__ __volatile__ ("dsb" : : : "memory"); \
Patrice Chotard1421e0a2017-07-18 17:37:25 +0200102 while (regs->sdsr & FMC_SDSR_BUSY) \
Patrice Chotard9242ece2017-07-18 17:37:24 +0200103 ; \
104 } while (0)
105
Vikas Manocha6c9a1002017-04-10 15:02:56 -0700106struct stm32_sdram_control {
107 u8 no_columns;
108 u8 no_rows;
109 u8 memory_width;
110 u8 no_banks;
111 u8 cas_latency;
Vikas Manochabfea69a2017-04-10 15:03:03 -0700112 u8 sdclk;
Vikas Manocha6c9a1002017-04-10 15:02:56 -0700113 u8 rd_burst;
114 u8 rd_pipe_delay;
115};
116
117struct stm32_sdram_timing {
118 u8 tmrd;
119 u8 txsr;
120 u8 tras;
121 u8 trc;
122 u8 trp;
Vikas Manochabfea69a2017-04-10 15:03:03 -0700123 u8 twr;
Vikas Manocha6c9a1002017-04-10 15:02:56 -0700124 u8 trcd;
125};
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200126enum stm32_fmc_bank {
127 SDRAM_BANK1,
128 SDRAM_BANK2,
129 MAX_SDRAM_BANK,
130};
131
Patrice Chotard70166512017-07-18 17:37:29 +0200132enum stm32_fmc_family {
133 STM32F7_FMC,
134 STM32H7_FMC,
135};
136
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200137struct bank_params {
Patrice Chotardf39b90d2017-07-18 17:37:26 +0200138 struct stm32_sdram_control *sdram_control;
139 struct stm32_sdram_timing *sdram_timing;
Vikas Manochabfea69a2017-04-10 15:03:03 -0700140 u32 sdram_ref_count;
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200141 enum stm32_fmc_bank target_bank;
142};
143
144struct stm32_sdram_params {
145 struct stm32_fmc_regs *base;
146 u8 no_sdram_banks;
147 struct bank_params bank_params[MAX_SDRAM_BANK];
Patrice Chotard70166512017-07-18 17:37:29 +0200148 enum stm32_fmc_family family;
Vikas Manocha6c9a1002017-04-10 15:02:56 -0700149};
Vikas Manochabf1ae442017-04-10 15:02:51 -0700150
151#define SDRAM_MODE_BL_SHIFT 0
152#define SDRAM_MODE_CAS_SHIFT 4
153#define SDRAM_MODE_BL 0
Vikas Manocha6c9a1002017-04-10 15:02:56 -0700154
155int stm32_sdram_init(struct udevice *dev)
Vikas Manochabf1ae442017-04-10 15:02:51 -0700156{
Vikas Manocha6c9a1002017-04-10 15:02:56 -0700157 struct stm32_sdram_params *params = dev_get_platdata(dev);
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200158 struct stm32_sdram_control *control;
159 struct stm32_sdram_timing *timing;
Patrice Chotard1421e0a2017-07-18 17:37:25 +0200160 struct stm32_fmc_regs *regs = params->base;
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200161 enum stm32_fmc_bank target_bank;
162 u32 ctb; /* SDCMR register: Command Target Bank */
163 u32 ref_count;
164 u8 i;
Vikas Manochabf1ae442017-04-10 15:02:51 -0700165
Patrice Chotard70166512017-07-18 17:37:29 +0200166 /* disable the FMC controller */
167 if (params->family == STM32H7_FMC)
168 clrbits_le32(&regs->bcr1, FMC_BCR1_FMCEN);
169
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200170 for (i = 0; i < params->no_sdram_banks; i++) {
171 control = params->bank_params[i].sdram_control;
172 timing = params->bank_params[i].sdram_timing;
173 target_bank = params->bank_params[i].target_bank;
174 ref_count = params->bank_params[i].sdram_ref_count;
Vikas Manochabf1ae442017-04-10 15:02:51 -0700175
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200176 writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT
177 | control->cas_latency << FMC_SDCR_CAS_SHIFT
178 | control->no_banks << FMC_SDCR_NB_SHIFT
179 | control->memory_width << FMC_SDCR_MWID_SHIFT
180 | control->no_rows << FMC_SDCR_NR_SHIFT
181 | control->no_columns << FMC_SDCR_NC_SHIFT
182 | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT
183 | control->rd_burst << FMC_SDCR_RBURST_SHIFT,
184 &regs->sdcr1);
Vikas Manochabf1ae442017-04-10 15:02:51 -0700185
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200186 if (target_bank == SDRAM_BANK2)
187 writel(control->cas_latency << FMC_SDCR_CAS_SHIFT
188 | control->no_banks << FMC_SDCR_NB_SHIFT
189 | control->memory_width << FMC_SDCR_MWID_SHIFT
190 | control->no_rows << FMC_SDCR_NR_SHIFT
191 | control->no_columns << FMC_SDCR_NC_SHIFT,
192 &regs->sdcr2);
Vikas Manochabf1ae442017-04-10 15:02:51 -0700193
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200194 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
195 | timing->trp << FMC_SDTR_TRP_SHIFT
196 | timing->twr << FMC_SDTR_TWR_SHIFT
197 | timing->trc << FMC_SDTR_TRC_SHIFT
198 | timing->tras << FMC_SDTR_TRAS_SHIFT
199 | timing->txsr << FMC_SDTR_TXSR_SHIFT
200 | timing->tmrd << FMC_SDTR_TMRD_SHIFT,
201 &regs->sdtr1);
Vikas Manochabf1ae442017-04-10 15:02:51 -0700202
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200203 if (target_bank == SDRAM_BANK2)
204 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
205 | timing->trp << FMC_SDTR_TRP_SHIFT
206 | timing->twr << FMC_SDTR_TWR_SHIFT
207 | timing->trc << FMC_SDTR_TRC_SHIFT
208 | timing->tras << FMC_SDTR_TRAS_SHIFT
209 | timing->txsr << FMC_SDTR_TXSR_SHIFT
210 | timing->tmrd << FMC_SDTR_TMRD_SHIFT,
211 &regs->sdtr2);
Patrice Chotard70166512017-07-18 17:37:29 +0200212
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200213 if (target_bank == SDRAM_BANK1)
214 ctb = FMC_SDCMR_BANK_1;
215 else
216 ctb = FMC_SDCMR_BANK_2;
Vikas Manochabf1ae442017-04-10 15:02:51 -0700217
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200218 writel(ctb | FMC_SDCMR_MODE_START_CLOCK, &regs->sdcmr);
219 udelay(200); /* 200 us delay, page 10, "Power-Up" */
220 FMC_BUSY_WAIT(regs);
Vikas Manochabf1ae442017-04-10 15:02:51 -0700221
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200222 writel(ctb | FMC_SDCMR_MODE_PRECHARGE, &regs->sdcmr);
223 udelay(100);
224 FMC_BUSY_WAIT(regs);
Vikas Manochabf1ae442017-04-10 15:02:51 -0700225
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200226 writel((ctb | FMC_SDCMR_MODE_AUTOREFRESH | 7 << FMC_SDCMR_NRFS_SHIFT),
227 &regs->sdcmr);
228 udelay(100);
229 FMC_BUSY_WAIT(regs);
230
231 writel(ctb | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
232 | control->cas_latency << SDRAM_MODE_CAS_SHIFT)
233 << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
234 &regs->sdcmr);
235 udelay(100);
236 FMC_BUSY_WAIT(regs);
237
238 writel(ctb | FMC_SDCMR_MODE_NORMAL, &regs->sdcmr);
239 FMC_BUSY_WAIT(regs);
240
241 /* Refresh timer */
242 writel(ref_count << 1, &regs->sdrtr);
243 }
Vikas Manochabf1ae442017-04-10 15:02:51 -0700244
Patrice Chotard70166512017-07-18 17:37:29 +0200245 /* enable the FMC controller */
246 if (params->family == STM32H7_FMC)
247 setbits_le32(&regs->bcr1, FMC_BCR1_FMCEN);
248
Vikas Manochabf1ae442017-04-10 15:02:51 -0700249 return 0;
250}
Vikas Manocha910a52e2017-04-10 15:02:52 -0700251
Vikas Manocha6c9a1002017-04-10 15:02:56 -0700252static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
253{
Vikas Manocha6c9a1002017-04-10 15:02:56 -0700254 struct stm32_sdram_params *params = dev_get_platdata(dev);
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200255 struct bank_params *bank_params;
256 ofnode bank_node;
257 char *bank_name;
258 u8 bank = 0;
Vikas Manocha6c9a1002017-04-10 15:02:56 -0700259
Patrice Chotardf39b90d2017-07-18 17:37:26 +0200260 dev_for_each_subnode(bank_node, dev) {
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200261 /* extract the bank index from DT */
262 bank_name = (char *)ofnode_get_name(bank_node);
263 strsep(&bank_name, "@");
264 if (!bank_name) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900265 pr_err("missing sdram bank index");
Patrice Chotardf39b90d2017-07-18 17:37:26 +0200266 return -EINVAL;
267 }
268
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200269 bank_params = &params->bank_params[bank];
270 strict_strtoul(bank_name, 10,
271 (long unsigned int *)&bank_params->target_bank);
Patrice Chotardf39b90d2017-07-18 17:37:26 +0200272
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200273 if (bank_params->target_bank >= MAX_SDRAM_BANK) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900274 pr_err("Found bank %d , but only bank 0 and 1 are supported",
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200275 bank_params->target_bank);
Patrice Chotardf39b90d2017-07-18 17:37:26 +0200276 return -EINVAL;
277 }
278
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200279 debug("Find bank %s %u\n", bank_name, bank_params->target_bank);
280
281 params->bank_params[bank].sdram_control =
282 (struct stm32_sdram_control *)
283 ofnode_read_u8_array_ptr(bank_node,
284 "st,sdram-control",
285 sizeof(struct stm32_sdram_control));
286
287 if (!params->bank_params[bank].sdram_control) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900288 pr_err("st,sdram-control not found for %s",
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200289 ofnode_get_name(bank_node));
290 return -EINVAL;
291 }
292
293
294 params->bank_params[bank].sdram_timing =
295 (struct stm32_sdram_timing *)
296 ofnode_read_u8_array_ptr(bank_node,
297 "st,sdram-timing",
298 sizeof(struct stm32_sdram_timing));
299
300 if (!params->bank_params[bank].sdram_timing) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900301 pr_err("st,sdram-timing not found for %s",
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200302 ofnode_get_name(bank_node));
303 return -EINVAL;
304 }
305
306
307 bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node,
Vikas Manochabfea69a2017-04-10 15:03:03 -0700308 "st,sdram-refcount", 8196);
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200309 bank++;
Vikas Manocha6c9a1002017-04-10 15:02:56 -0700310 }
311
Patrice Chotardf303aaf2017-07-18 17:37:27 +0200312 params->no_sdram_banks = bank;
313 debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
314
Vikas Manocha6c9a1002017-04-10 15:02:56 -0700315 return 0;
316}
317
Vikas Manocha910a52e2017-04-10 15:02:52 -0700318static int stm32_fmc_probe(struct udevice *dev)
319{
Patrice Chotard1421e0a2017-07-18 17:37:25 +0200320 struct stm32_sdram_params *params = dev_get_platdata(dev);
Vikas Manochad0b24c12017-04-10 15:02:55 -0700321 int ret;
Patrice Chotard1421e0a2017-07-18 17:37:25 +0200322 fdt_addr_t addr;
323
324 addr = dev_read_addr(dev);
325 if (addr == FDT_ADDR_T_NONE)
326 return -EINVAL;
327
328 params->base = (struct stm32_fmc_regs *)addr;
Patrice Chotard70166512017-07-18 17:37:29 +0200329 params->family = dev_get_driver_data(dev);
Patrice Chotard1421e0a2017-07-18 17:37:25 +0200330
Patrice Chotard14a50e32017-05-30 15:06:31 +0200331#ifdef CONFIG_CLK
Vikas Manochad0b24c12017-04-10 15:02:55 -0700332 struct clk clk;
Vikas Manocha6c9a1002017-04-10 15:02:56 -0700333
Vikas Manochad0b24c12017-04-10 15:02:55 -0700334 ret = clk_get_by_index(dev, 0, &clk);
335 if (ret < 0)
336 return ret;
337
338 ret = clk_enable(&clk);
339
340 if (ret) {
341 dev_err(dev, "failed to enable clock\n");
342 return ret;
343 }
344#endif
Vikas Manocha6c9a1002017-04-10 15:02:56 -0700345 ret = stm32_sdram_init(dev);
346 if (ret)
347 return ret;
348
Vikas Manocha910a52e2017-04-10 15:02:52 -0700349 return 0;
350}
351
352static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info)
353{
Vikas Manocha910a52e2017-04-10 15:02:52 -0700354 return 0;
355}
356
357static struct ram_ops stm32_fmc_ops = {
358 .get_info = stm32_fmc_get_info,
359};
360
361static const struct udevice_id stm32_fmc_ids[] = {
Patrice Chotard70166512017-07-18 17:37:29 +0200362 { .compatible = "st,stm32-fmc", .data = STM32F7_FMC },
363 { .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC },
Vikas Manocha910a52e2017-04-10 15:02:52 -0700364 { }
365};
366
367U_BOOT_DRIVER(stm32_fmc) = {
368 .name = "stm32_fmc",
369 .id = UCLASS_RAM,
370 .of_match = stm32_fmc_ids,
371 .ops = &stm32_fmc_ops,
Vikas Manocha6c9a1002017-04-10 15:02:56 -0700372 .ofdata_to_platdata = stm32_fmc_ofdata_to_platdata,
Vikas Manocha910a52e2017-04-10 15:02:52 -0700373 .probe = stm32_fmc_probe,
Vikas Manocha6c9a1002017-04-10 15:02:56 -0700374 .platdata_auto_alloc_size = sizeof(struct stm32_sdram_params),
Vikas Manocha910a52e2017-04-10 15:02:52 -0700375};