blob: 0766398605e4b265c2cb4f0ca179b358e71998e5 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Jagannadha Sutradharudu Teki9e0802b2014-01-09 01:48:29 +05302/*
3 * Xilinx MicroZED board DTS
4 *
Michal Simek371fc582016-01-12 08:06:36 +01005 * Copyright (C) 2013 - 2016 Xilinx, Inc.
Jagannadha Sutradharudu Teki9e0802b2014-01-09 01:48:29 +05306 */
7/dts-v1/;
8#include "zynq-7000.dtsi"
9
10/ {
11 model = "Zynq MicroZED Board";
Luis Aranedacd6160b2018-07-12 00:10:19 -040012 compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";
Masahiro Yamada7d34c5d2014-05-15 20:37:54 +090013
Masahiro Yamada9f9d41b2014-05-15 20:37:55 +090014 aliases {
15 serial0 = &uart1;
Jagan Teki659cc152015-08-15 23:08:51 +053016 spi0 = &qspi;
Michal Simek371fc582016-01-12 08:06:36 +010017 mmc0 = &sdhci0;
Masahiro Yamada9f9d41b2014-05-15 20:37:55 +090018 };
19
Michal Simekcc7978b2016-11-11 13:11:37 +010020 memory@0 {
Masahiro Yamada7d34c5d2014-05-15 20:37:54 +090021 device_type = "memory";
22 reg = <0 0x40000000>;
23 };
Michal Simek371fc582016-01-12 08:06:36 +010024
25 chosen {
26 bootargs = "earlyprintk";
27 stdout-path = "serial0:115200n8";
28 };
29
30 usb_phy0: phy0 {
31 compatible = "usb-nop-xceiv";
32 #phy-cells = <0>;
33 };
34};
35
36&clkc {
37 ps-clk-frequency = <33333333>;
Jagannadha Sutradharudu Teki9e0802b2014-01-09 01:48:29 +053038};
Jagan Teki659cc152015-08-15 23:08:51 +053039
40&qspi {
Nathan Rossicb204a62016-02-16 23:05:03 +100041 u-boot,dm-pre-reloc;
Jagan Teki659cc152015-08-15 23:08:51 +053042 status = "okay";
43};
Simon Glass035c6b22015-10-17 19:41:24 -060044
45&uart1 {
46 u-boot,dm-pre-reloc;
47 status = "okay";
48};
Michal Simek371fc582016-01-12 08:06:36 +010049
50&gem0 {
51 status = "okay";
52 phy-mode = "rgmii-id";
53 phy-handle = <&ethernet_phy>;
54
55 ethernet_phy: ethernet-phy@0 {
56 reg = <0>;
57 };
58};
59
60&sdhci0 {
61 u-boot,dm-pre-reloc;
62 status = "okay";
63};
64
65&usb0 {
66 status = "okay";
67 dr_mode = "host";
68 usb-phy = <&usb_phy0>;
69};