blob: cf3ff4d45f8149a1abe5d75163666cdc660b4dc3 [file] [log] [blame]
John Schmollerbfe18812010-10-22 00:20:34 -05001/*
2 * Copyright 2008 Extreme Engineering Solutions, Inc.
3 * Copyright 2008 Freescale Semiconductor, Inc.
4 *
5 * (C) Copyright 2000
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <asm/mmu.h>
29
30struct fsl_e_tlb_entry tlb_table[] = {
31 /* TLB 0 - for temp stack in cache */
32 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
33 MAS3_SX|MAS3_SW|MAS3_SR, 0,
34 0, 0, BOOKE_PAGESZ_4K, 0),
35 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
36 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
37 MAS3_SX|MAS3_SW|MAS3_SR, 0,
38 0, 0, BOOKE_PAGESZ_4K, 0),
39 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
40 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
41 MAS3_SX|MAS3_SW|MAS3_SR, 0,
42 0, 0, BOOKE_PAGESZ_4K, 0),
43 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
44 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
45 MAS3_SX|MAS3_SW|MAS3_SR, 0,
46 0, 0, BOOKE_PAGESZ_4K, 0),
47
48 /* W**G* - NOR flashes */
49 /* This will be changed to *I*G* after relocation to RAM. */
50 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
51 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
52 0, 0, BOOKE_PAGESZ_256M, 1),
53
54 /* *I*G* - CCSRBAR */
55 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
56 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
57 0, 1, BOOKE_PAGESZ_1M, 1),
58
59 /* *I*G* - NAND flash */
60 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
61 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
62 0, 2, BOOKE_PAGESZ_1M, 1),
63
64 /* **M** - Boot page for secondary processors */
65 SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
66 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
67 0, 3, BOOKE_PAGESZ_4K, 1),
68
69#ifdef CONFIG_PCIE1
70 /* *I*G* - PCIe */
71 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
72 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
73 0, 4, BOOKE_PAGESZ_1G, 1),
74#endif
75
76#ifdef CONFIG_PCIE2
77 /* *I*G* - PCIe */
78 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
79 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
80 0, 5, BOOKE_PAGESZ_256M, 1),
81#endif
82
83#ifdef CONFIG_PCIE3
84 /* *I*G* - PCIe */
85 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
86 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
87 0, 6, BOOKE_PAGESZ_256M, 1),
88#endif
89
90#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
91 /* *I*G* - PCIe */
92 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
93 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
94 0, 7, BOOKE_PAGESZ_64M, 1),
95#endif
96};
97
98int num_tlb_entries = ARRAY_SIZE(tlb_table);