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Jagannadha Sutradharudu Teki9e0802b2014-01-09 01:48:29 +05301/*
2 * Xilinx ZC770 XM013 board DTS
3 *
4 * Copyright (C) 2013 Xilinx, Inc.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8/dts-v1/;
9#include "zynq-7000.dtsi"
10
11/ {
Jagannadha Sutradharudu Teki9e0802b2014-01-09 01:48:29 +053012 compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
Michal Simek5c45b162015-07-22 11:36:32 +020013 model = "Xilinx Zynq";
Masahiro Yamada7d34c5d2014-05-15 20:37:54 +090014
Masahiro Yamada9f9d41b2014-05-15 20:37:55 +090015 aliases {
Michal Simek5c45b162015-07-22 11:36:32 +020016 ethernet0 = &gem1;
17 i2c0 = &i2c1;
Masahiro Yamada9f9d41b2014-05-15 20:37:55 +090018 serial0 = &uart0;
Michal Simek5c45b162015-07-22 11:36:32 +020019 spi0 = &spi0;
Masahiro Yamada9f9d41b2014-05-15 20:37:55 +090020 };
21
Michal Simek5c45b162015-07-22 11:36:32 +020022 chosen {
Michal Simek46919412016-01-12 13:56:44 +010023 bootargs = "root=/dev/ram rw earlyprintk";
24 stdout-path = "serial0:115200n8";
Masahiro Yamada7d34c5d2014-05-15 20:37:54 +090025 };
Michal Simek5c45b162015-07-22 11:36:32 +020026
Michal Simekf0600af2015-08-12 11:25:05 +020027 memory {
Michal Simek5c45b162015-07-22 11:36:32 +020028 device_type = "memory";
29 reg = <0x0 0x40000000>;
30 };
31};
32
Michal Simek5c45b162015-07-22 11:36:32 +020033&can1 {
34 status = "okay";
35};
36
37&gem1 {
38 status = "okay";
39 phy-mode = "rgmii-id";
40 phy-handle = <&ethernet_phy>;
41
42 ethernet_phy: ethernet-phy@7 {
43 reg = <7>;
44 };
45};
46
47&i2c1 {
48 status = "okay";
49 clock-frequency = <400000>;
50
51 si570: clock-generator@55 {
52 #clock-cells = <0>;
53 compatible = "silabs,si570";
54 temperature-stability = <50>;
55 reg = <0x55>;
56 factory-fout = <156250000>;
57 clock-frequency = <148500000>;
58 };
59};
60
Michal Simek7ebf67a2016-01-14 13:09:16 +010061&spi0 {
62 status = "okay";
63 num-cs = <4>;
64 is-decoded-cs = <0>;
65 eeprom: at25@0 {
66 at25,byte-len = <8192>;
67 at25,addr-mode = <2>;
68 at25,page-size = <32>;
69
70 compatible = "atmel,at25";
71 reg = <2>;
72 spi-max-frequency = <1000000>;
73 };
74};
75
Michal Simek5c45b162015-07-22 11:36:32 +020076&uart0 {
Simon Glass035c6b22015-10-17 19:41:24 -060077 u-boot,dm-pre-reloc;
Michal Simek5c45b162015-07-22 11:36:32 +020078 status = "okay";
Jagannadha Sutradharudu Teki9e0802b2014-01-09 01:48:29 +053079};