Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 1 | Introduction |
| 2 | ============ |
| 3 | |
| 4 | HiKey is the first certified 96Boards Consumer Edition board. The board/SoC has: - |
| 5 | * HiSilicon Kirin 6220 eight-core ARM Cortex-A53 64-bit SoC running at 1.2GHz. |
| 6 | * ARM Mali 450-MP4 GPU |
| 7 | * 1GB 800MHz LPDDR3 DRAM |
| 8 | * 4GB eMMC Flash Storage |
| 9 | * microSD |
| 10 | * 802.11a/b/g/n WiFi, Bluetooth |
| 11 | |
| 12 | The HiKey schematic can be found here: - |
| 13 | https://github.com/96boards/documentation/blob/master/hikey/96Boards-Hikey-Rev-A1.pdf |
| 14 | |
| 15 | A SoC datasheet can be found here: - |
| 16 | https://github.com/96boards/documentation/blob/master/hikey/ |
| 17 | Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf |
| 18 | |
| 19 | Currently the u-boot port supports: - |
| 20 | * USB |
| 21 | * eMMC |
| 22 | * SD card |
| 23 | * GPIO |
| 24 | |
| 25 | Compile u-boot |
| 26 | ============== |
| 27 | |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 28 | > mkdir -p ./aarch64/bin |
| 29 | > cd ./aarch64 |
| 30 | > git clone http://git.denx.de/u-boot.git |
| 31 | > make CROSS_COMPILE=aarch64-linux-gnu- hikey_config |
| 32 | > make CROSS_COMPILE=aarch64-linux-gnu- |
| 33 | > cp u-boot.bin ./aarch64/bin/u-boot-hikey.bin |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 34 | |
| 35 | ARM Trusted Firmware (ATF) & l-loader |
| 36 | ===================================== |
| 37 | |
| 38 | This u-boot port has been tested with l-loader, booting ATF, which then boots |
| 39 | u-boot as the bl33.bin executable. |
| 40 | |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 41 | Get the BL30 mcu binary. |
| 42 | > wget -P aarch64/bin https://builds.96boards.org/releases/hikey/linaro/binaries/15.05/mcuimage.bin |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 43 | |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 44 | 1. Get ATF source code |
| 45 | > cd ./aarch64 |
| 46 | > git clone https://github.com/96boards/arm-trusted-firmware.git |
| 47 | > cd ./arm-trusted-firmware |
| 48 | |
| 49 | 2. Compile ATF, I use the build-tf.mak in the directory with this README, and copy it to ATF directory |
| 50 | > cp ../u-boot/board/hisilicon/hikey/build-tf.mak . |
| 51 | > make -f build-tf.mak build |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 52 | |
| 53 | 3. Get l-loader |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 54 | > cd ../ |
| 55 | > git clone https://github.com/96boards/l-loader.git |
| 56 | > cd ./l-loader |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 57 | |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 58 | 4. Make sym links to ATF bl1 / fip binaries |
| 59 | > ln -s ../bin/bl1-hikey.bin bl1.bin |
| 60 | > ln -s ../bin/fip-hikey.bin fip.bin |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 61 | |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 62 | > arm-linux-gnueabihf-gcc -c -o start.o start.S |
| 63 | > arm-linux-gnueabihf-gcc -c -o debug.o debug.S |
| 64 | > arm-linux-gnueabihf-ld -Bstatic -Tl-loader.lds -Ttext 0xf9800800 start.o debug.o -o loader |
| 65 | > arm-linux-gnueabihf-objcopy -O binary loader temp |
| 66 | > python gen_loader.py -o ../bin/l-loader.bin --img_loader=temp --img_bl1=bl1.bin |
| 67 | > sudo bash -x generate_ptable.sh |
| 68 | > python gen_loader.py -o ../bin/ptable.img --img_prm_ptable=./prm_ptable.img --img_sec_ptable=./sec_ptable.img |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 69 | |
| 70 | These instructions are adapted from |
| 71 | https://github.com/96boards/documentation/wiki/HiKeyUEFI |
| 72 | |
| 73 | FLASHING |
| 74 | ======== |
| 75 | |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 76 | 1. Connect the second jumper on J15 BOOT SEL, to go into recovery mode and flash l-loader.bin with |
| 77 | fastboot using the hisi-idt.py utility. |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 78 | |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 79 | > cd ../ |
| 80 | > git clone https://github.com/96boards/burn-boot.git |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 81 | |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 82 | The command below assumes HiKey enumerated as the first USB serial port |
| 83 | > sudo ./burn-boot/hisi-idt.py -d /dev/ttyUSB0 --img1=./bin/l-loader.bin |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 84 | |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 85 | 2. Once LED 0 comes on solid, it should be detected as a fastboot device by plugging a USB A to mini B |
| 86 | cable from your PC to the USB OTG port of HiKey (on some boards I've found this to be unreliable). |
| 87 | |
| 88 | > sudo fastboot devices |
| 89 | |
| 90 | 0123456789ABCDEF fastboot |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 91 | |
| 92 | 3. Flash the images |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 93 | > wget -P aarch64/bin wget https://builds.96boards.org/releases/hikey/linaro/binaries/latest/nvme.img |
| 94 | > sudo fastboot flash ptable ./bin/ptable.img |
| 95 | > sudo fastboot flash fastboot ./bin/fip-hikey.bin |
| 96 | > sudo fastboot flash nvme ./bin/nvme.img |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 97 | |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 98 | 4. Disconnect second jumper on J15 BOOT SEL, and reset the board and you will now (hopefully) |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 99 | have ATF, booting u-boot from eMMC. On 'new' boards I've had to do the |
| 100 | flashing twice in the past to avoid an ATF error. |
| 101 | |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 102 | Note: To get USB host working, also disconnect the USB OTG cable used for flashing. Otherwise you |
| 103 | will get 'dwc_otg_core_host_init: Timeout!' errors. |
| 104 | |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 105 | See working boot trace below: - |
| 106 | |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 107 | debug EMMC boot: send RST_N . |
| 108 | debug EMMC boot: start eMMC boot...... |
| 109 | load fastboot1! |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 110 | |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 111 | Switch to aarch64 mode. CPU0 executes at 0xf9801000! |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 112 | |
| 113 | INFO: BL1: 0xf9810000 - 0xf9817000 [size = 28672] |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 114 | NOTICE: Booting Trusted Firmware |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 115 | NOTICE: BL1: v1.1(debug):e8b7174 |
| 116 | NOTICE: BL1: Built : 19:16:44, Sep 8 2015 |
| 117 | INFO: BL1: RAM 0xf9810000 - 0xf9817000 |
| 118 | NOTICE: syspll frequency:1190494208Hz |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 119 | NOTICE: succeed to init lpddr3 rank0 dram phy |
| 120 | INFO: lpddr3_freq_init, set ddrc 533mhz |
| 121 | INFO: init ddr3 rank0 |
| 122 | INFO: ddr3 rank1 init pass |
| 123 | INFO: lpddr3_freq_init, set ddrc 800mhz |
| 124 | INFO: init ddr3 rank0 |
| 125 | INFO: ddr3 rank1 init pass |
| 126 | INFO: Elpida DDR |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 127 | INFO: ddr test value:0xa5a55a5a |
| 128 | INFO: Hisilicon HiKey platform is initialized |
| 129 | INFO: Using FIP |
| 130 | INFO: Loading file 'bl2.bin' at address 0xf9818000 |
| 131 | INFO: File 'bl2.bin' loaded: 0xf9818000 - 0xf9821100 |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 132 | NOTICE: BL1: Booting BL2 |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 133 | INFO: BL1: BL2 address = 0xf9818000 |
| 134 | INFO: BL1: BL2 spsr = 0x3c5 |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 135 | INFO: [BDID] [fff91c18] midr: 0x410fd033 |
| 136 | INFO: [BDID] [fff91c1c] board type: 0 |
| 137 | INFO: [BDID] [fff91c20] board id: 0x2b |
| 138 | INFO: init_acpu_dvfs: pmic version 17 |
| 139 | INFO: init_acpu_dvfs: ACPU_CHIP_MAX_FREQ=0x186a00. |
| 140 | INFO: acpu_dvfs_volt_init: success! |
| 141 | INFO: acpu_dvfs_set_freq: support freq num is 5 |
| 142 | INFO: acpu_dvfs_set_freq: start prof is 0x4 |
| 143 | INFO: acpu_dvfs_set_freq: magic is 0x5a5ac5c5 |
| 144 | INFO: acpu_dvfs_set_freq: voltage: |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 145 | INFO: - 0: 0x49 |
| 146 | INFO: - 1: 0x49 |
| 147 | INFO: - 2: 0x50 |
| 148 | INFO: - 3: 0x60 |
| 149 | INFO: - 4: 0x78 |
| 150 | NOTICE: acpu_dvfs_set_freq: set acpu freq success!NOTICE: BL2: v1.1(debug):e8b7174 |
| 151 | NOTICE: BL2: Built : 19:16:46, Sep 8 2015 |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 152 | INFO: BL2: Loading BL3-0 |
| 153 | INFO: Using FIP |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 154 | INFO: Loading file 'bl30.bin' at address 0x1000000 |
| 155 | INFO: Skip reserving memory: 0x1000000 - 0x1023270 |
| 156 | INFO: File 'bl30.bin' loaded: 0x1000000 - 0x1023270 |
| 157 | INFO: bl2_plat_handle_bl30: [1000000] 3a334d43 34313032 2f38302f 30203133 |
| 158 | INFO: bl2_plat_handle_bl30: [10000c8] 0 0 b 0 |
| 159 | INFO: bl2_plat_handle_bl30: [1000190] 17 0 0 0 |
| 160 | INFO: bl2_plat_handle_bl30: [1023260] 0 0 0 0 |
| 161 | INFO: hisi_mcu_load_image: mcu sections 0: |
| 162 | INFO: hisi_mcu_load_image: src = 0x1000200 |
| 163 | INFO: hisi_mcu_load_image: dst = 0xf6000000 |
| 164 | INFO: hisi_mcu_load_image: size = 512 |
| 165 | INFO: hisi_mcu_load_image: [SRC 0x1000200] 0x7600 0x201 0x1eae1 0x1ea71 |
| 166 | INFO: hisi_mcu_load_image: [DST 0xf6000000] 0x7600 0x201 0x1eae1 0x1ea71 |
| 167 | INFO: hisi_mcu_load_image: mcu sections 1: |
| 168 | INFO: hisi_mcu_load_image: src = 0x1000400 |
| 169 | INFO: hisi_mcu_load_image: dst = 0xf6000200 |
| 170 | INFO: hisi_mcu_load_image: size = 27828 |
| 171 | INFO: hisi_mcu_load_image: [SRC 0x1000400] 0xbf00bf00 0x4815b672 0x48154780 0x60014915 |
| 172 | INFO: hisi_mcu_load_image: [DST 0xf6000200] 0xbf00bf00 0x4815b672 0x48154780 0x60014915 |
| 173 | INFO: hisi_mcu_load_image: mcu sections 2: |
| 174 | INFO: hisi_mcu_load_image: src = 0x10070b4 |
| 175 | INFO: hisi_mcu_load_image: dst = 0xf6007200 |
| 176 | INFO: hisi_mcu_load_image: size = 1024 |
| 177 | INFO: hisi_mcu_load_image: [SRC 0x10070b4] 0x55 0x0 0x0 0x0 |
| 178 | INFO: hisi_mcu_load_image: [DST 0xf6007200] 0x55 0x0 0x0 0x0 |
| 179 | INFO: hisi_mcu_load_image: mcu sections 3: |
| 180 | INFO: hisi_mcu_load_image: src = 0x10074b4 |
| 181 | INFO: hisi_mcu_load_image: dst = 0xfff8e000 |
| 182 | INFO: hisi_mcu_load_image: size = 12704 |
| 183 | INFO: hisi_mcu_load_image: [SRC 0x10074b4] 0x55 0x0 0x0 0x0 |
| 184 | INFO: hisi_mcu_load_image: [DST 0xfff8e000] 0x55 0x0 0x0 0x0 |
| 185 | INFO: hisi_mcu_load_image: mcu sections 4: |
| 186 | INFO: hisi_mcu_load_image: src = 0x100a654 |
| 187 | INFO: hisi_mcu_load_image: dst = 0x5e00000 |
| 188 | INFO: hisi_mcu_load_image: size = 82912 |
| 189 | INFO: hisi_mcu_load_image: [SRC 0x100a654] 0x4ff0e92d 0x2cc5f645 0x2600b0ab 0x2c7cf6c0 |
| 190 | INFO: hisi_mcu_load_image: [DST 0x5e00000] 0x4ff0e92d 0x2cc5f645 0x2600b0ab 0x2c7cf6c0 |
| 191 | INFO: hisi_mcu_load_image: mcu sections 5: |
| 192 | INFO: hisi_mcu_load_image: src = 0x101ea34 |
| 193 | INFO: hisi_mcu_load_image: dst = 0x5e143e0 |
| 194 | INFO: hisi_mcu_load_image: size = 12816 |
| 195 | INFO: hisi_mcu_load_image: [SRC 0x101ea34] 0x33323130 0x37363534 0x42413938 0x46454443 |
| 196 | INFO: hisi_mcu_load_image: [DST 0x5e143e0] 0x33323130 0x37363534 0x42413938 0x46454443 |
| 197 | INFO: hisi_mcu_load_image: mcu sections 6: |
| 198 | INFO: hisi_mcu_load_image: src = 0x1021c44 |
| 199 | INFO: hisi_mcu_load_image: dst = 0x5e1c1d0 |
| 200 | INFO: hisi_mcu_load_image: size = 3060 |
| 201 | INFO: hisi_mcu_load_image: [SRC 0x1021c44] 0x0 0x0 0x0 0x0 |
| 202 | INFO: hisi_mcu_load_image: [DST 0x5e1c1d0] 0x0 0x0 0x0 0x0 |
| 203 | INFO: hisi_mcu_load_image: mcu sections 7: |
| 204 | INFO: hisi_mcu_load_image: src = 0x1022838 |
| 205 | INFO: hisi_mcu_load_image: dst = 0x5e1cdc4 |
| 206 | INFO: hisi_mcu_load_image: size = 2616 |
| 207 | INFO: hisi_mcu_load_image: [SRC 0x1022838] 0xf80000a0 0x0 0xf80000ac 0x0 |
| 208 | INFO: hisi_mcu_load_image: [DST 0x5e1cdc4] 0xf80000a0 0x0 0xf80000ac 0x0 |
| 209 | INFO: hisi_mcu_start_run: AO_SC_SYS_CTRL2=0 |
| 210 | INFO: bl2_plat_handle_bl30: mcu pc is 42933301 |
| 211 | INFO: bl2_plat_handle_bl30: AO_SC_PERIPH_CLKSTAT4 is 39018f09 |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 212 | INFO: BL2: TrustZone: protecting 16777216 bytes of memory at 0x3f000000 |
| 213 | INFO: BL2: Loading BL3-1 |
| 214 | INFO: Using FIP |
| 215 | INFO: Loading file 'bl31.bin' at address 0xf9858000 |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 216 | INFO: File 'bl31.bin' loaded: 0xf9858000 - 0xf9861010 |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 217 | INFO: BL2: Loading BL3-2 |
| 218 | INFO: Using FIP |
| 219 | WARNING: Failed to access image 'bl32.bin' (-1) |
| 220 | WARNING: Failed to load BL3-2 (-1) |
| 221 | INFO: BL2: Loading BL3-3 |
| 222 | INFO: Using FIP |
| 223 | INFO: Loading file 'bl33.bin' at address 0x35000000 |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 224 | INFO: File 'bl33.bin' loaded: 0x35000000 - 0x3504c468 |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 225 | NOTICE: BL1: Booting BL3-1 |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 226 | INFO: BL1: BL3-1 address = 0xf9858000 |
| 227 | INFO: BL1: BL3-1 spsr = 0x3cd |
| 228 | INFO: BL1: BL3-1 params address = 0xf9821920 |
| 229 | INFO: BL1: BL3-1 plat params address = 0x0 |
| 230 | NOTICE: BL3-1: v1.1(debug):e8b7174 |
| 231 | NOTICE: BL3-1: Built : 19:16:49, Sep 8 2015 |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 232 | INFO: BL3-1: Initializing runtime services |
| 233 | INFO: BL3-1: Preparing for EL3 exit to normal world |
| 234 | INFO: BL3-1: Next image address = 0x35000000 |
| 235 | INFO: BL3-1: Next image spsr = 0x3c9 |
| 236 | |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 237 | U-Boot 2015.10-rc2 (Sep 08 2015 - 20:29:33 +0100)hikey |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 238 | |
| 239 | DRAM: 1008 MiB |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 240 | HI6553 PMIC init |
| 241 | MMC: config_sd_carddetect: SD card not present |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 242 | HiKey DWMMC: 0, HiKey DWMMC: 1 |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 243 | Card did not respond to voltage select! |
| 244 | ** Bad device mmc 1 ** |
| 245 | Using default environment |
| 246 | |
Peter Griffin | f9a9fc6 | 2015-07-30 18:55:24 +0100 | [diff] [blame] | 247 | In: serial |
| 248 | Out: serial |
| 249 | Err: serial |
| 250 | Net: Net Initialization Skipped |
| 251 | No ethernet found. |
| 252 | Hit any key to stop autoboot: 0 |
Peter Griffin | 9c71a21 | 2015-09-10 21:55:11 +0100 | [diff] [blame^] | 253 | starting USB... |
| 254 | USB0: Core Release: 3.00a |
| 255 | scanning bus 0 for devices... 2 USB Device(s) found |
| 256 | scanning usb for storage devices... 0 Storage Device(s) found |
| 257 | scanning usb for ethernet devices... 0 Ethernet Device(s) found |