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Heiko Schocher6341d9d2008-01-11 15:15:14 +01001/*
2 * (C) Copyright 2007
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocher6341d9d2008-01-11 15:15:14 +01006 */
7
8#include <common.h>
9#include <mpc5xxx.h>
10#include <pci.h>
11
12#include "mt48lc16m16a2-75.h"
13
Simon Glass088454c2017-03-31 08:40:25 -060014DECLARE_GLOBAL_DATA_PTR;
15
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020016#ifndef CONFIG_SYS_RAMBOOT
Heiko Schocher6341d9d2008-01-11 15:15:14 +010017static void sdram_start (int hi_addr)
18{
19 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
20
21 /* unlock mode register */
22 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
23 __asm__ volatile ("sync");
24
25 /* precharge all banks */
26 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
27 __asm__ volatile ("sync");
28
29#if SDRAM_DDR
30 /* set mode register: extended mode */
31 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
32 __asm__ volatile ("sync");
33
34 /* set mode register: reset DLL */
35 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
36 __asm__ volatile ("sync");
37#endif
38
39 /* precharge all banks */
40 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
41 __asm__ volatile ("sync");
42
43 /* auto refresh */
44 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
45 __asm__ volatile ("sync");
46
47 /* set mode register */
48 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
49 __asm__ volatile ("sync");
50
51 /* normal operation */
52 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
53 __asm__ volatile ("sync");
54}
55#endif
56
57/*
Simon Glassf1683aa2017-04-06 12:47:05 -060058 * ATTENTION: Although partially referenced dram_init does NOT make real use
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
Heiko Schocher6341d9d2008-01-11 15:15:14 +010060 * is something else than 0x00000000.
61 */
62
Simon Glassf1683aa2017-04-06 12:47:05 -060063int dram_init(void)
Heiko Schocher6341d9d2008-01-11 15:15:14 +010064{
65 ulong dramsize = 0;
66 ulong dramsize2 = 0;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#ifndef CONFIG_SYS_RAMBOOT
Heiko Schocher6341d9d2008-01-11 15:15:14 +010068 ulong test1, test2;
69
70 /* setup SDRAM chip selects */
71 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001b;/* 256MB at 0x0 */
72 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x10000000;/* disabled */
73 __asm__ volatile ("sync");
74
75 /* setup config registers */
76 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
77 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
78 __asm__ volatile ("sync");
79
80#if SDRAM_DDR && SDRAM_TAPDELAY
81 /* set tap delay */
82 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
83 __asm__ volatile ("sync");
84#endif
85
86 /* find RAM size using SDRAM CS0 only */
87 sdram_start(0);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088 test1 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000);
Heiko Schocher6341d9d2008-01-11 15:15:14 +010089 sdram_start(1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090 test2 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000);
Heiko Schocher6341d9d2008-01-11 15:15:14 +010091 if (test1 > test2) {
92 sdram_start(0);
93 dramsize = test1;
94 } else {
95 dramsize = test2;
96 }
97
98 /* memory smaller than 1MB is impossible */
99 if (dramsize < (1 << 20)) {
100 dramsize = 0;
101 }
102
103 /* set SDRAM CS0 size according to the amount of RAM found */
104 if (dramsize > 0) {
105 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
106 } else {
107 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
108 }
109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#else /* CONFIG_SYS_RAMBOOT */
Heiko Schocher6341d9d2008-01-11 15:15:14 +0100111
112 /* retrieve size of memory connected to SDRAM CS0 */
113 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
114 if (dramsize >= 0x13) {
115 dramsize = (1 << (dramsize - 0x13)) << 20;
116 } else {
117 dramsize = 0;
118 }
119
120 /* retrieve size of memory connected to SDRAM CS1 */
121 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
122 if (dramsize2 >= 0x13) {
123 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
124 } else {
125 dramsize2 = 0;
126 }
127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#endif /* CONFIG_SYS_RAMBOOT */
Heiko Schocher6341d9d2008-01-11 15:15:14 +0100129
Simon Glass088454c2017-03-31 08:40:25 -0600130 gd->ram_size = dramsize + dramsize2;
131
132 return 0;
Heiko Schocher6341d9d2008-01-11 15:15:14 +0100133}
134
135int checkboard (void)
136{
137 puts ("Board: MUNICes\n");
138 return 0;
139}
140
141#ifdef CONFIG_PCI
142static struct pci_controller hose;
143
144extern void pci_mpc5xxx_init(struct pci_controller *);
145
146void pci_init_board(void)
147{
148 pci_mpc5xxx_init(&hose);
149}
150#endif
151
Robert P. J. Day7ffe3cd2016-05-19 15:23:12 -0400152#ifdef CONFIG_OF_BOARD_SETUP
Simon Glasse895a4b2014-10-23 18:58:47 -0600153int ft_board_setup(void *blob, bd_t *bd)
Heiko Schocher6341d9d2008-01-11 15:15:14 +0100154{
155 ft_cpu_setup(blob, bd);
Simon Glasse895a4b2014-10-23 18:58:47 -0600156
157 return 0;
Heiko Schocher6341d9d2008-01-11 15:15:14 +0100158}
Robert P. J. Day7ffe3cd2016-05-19 15:23:12 -0400159#endif /* CONFIG_OF_BOARD_SETUP */