blob: ccd1f19903b40ed3871c9998dfb9ce97515c6055 [file] [log] [blame]
wdenkdb01a2e2004-04-15 23:14:49 +00001/*
2 * (C) Copyright 2003 Picture Elements, Inc.
3 * Stephen Williams <steve@icarus.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options for the JSE board
33 * (Theoretically easy to change, but the board is fixed.)
34 */
35
36#define CONFIG_JSE 1
37 /* JSE has a PPC405GPr */
38#define CONFIG_405GP 1
39 /* ... which is a 4xxx series */
40#define CONFIG_4xx 1
41 /* ... with a 33MHz OSC. connected to the SysCLK input */
42#define CONFIG_SYS_CLK_FREQ 33333333
43 /* ... with on-chip memory here (4KBytes) */
44#define CFG_OCM_DATA_ADDR 0xF4000000
45#define CFG_OCM_DATA_SIZE 0x00001000
46 /* Do not set up locked dcache as init ram. */
47#undef CFG_INIT_DCACHE_CS
48
49 /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */
50#define CONFIG_SYSTEMACE 1
51#define CFG_SYSTEMACE_BASE 0xf0000000
52#define CONFIG_DOS_PARTITION 1
53
54 /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
55#define CFG_TEMP_STACK_OCM 1
56 /* ... place INIT RAM in the OCM address */
57# define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR
58 /* ... give it the whole init ram */
59# define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE
60 /* ... Shave a bit off the end for global data */
61# define CFG_GBL_DATA_SIZE 128
62# define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
63 /* ... and place the stack pointer at the top of what's left. */
64# define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
65
66 /* Enable board_pre_init function */
67#define CONFIG_BOARD_PRE_INIT 1
68#define CONFIG_BOARD_EARLY_INIT_F 1
69 /* Disable post-clk setup init function */
70#undef CONFIG_BOARD_POSTCLK_INIT
71 /* Disable call to post_init_f: late init function. */
72#undef CONFIG_POST
73 /* Enable DRAM test. */
74#define CFG_DRAM_TEST 1
75 /* Enable misc_init_r function. */
76#define CONFIG_MISC_INIT_R 1
77
78 /* JSE has EEPROM chips that are good for environment. */
79#undef CFG_ENV_IS_IN_NVRAM
80#undef CFG_ENV_IS_IN_FLASH
81#define CFG_ENV_IS_IN_EEPROM 1
82#undef CFG_ENV_IS_NOWHERE
83
84 /* This is the 7bit address of the device, not including P. */
85#define CFG_I2C_EEPROM_ADDR 0x50
86 /* After the device address, need one more address byte. */
87#define CFG_I2C_EEPROM_ADDR_LEN 1
88 /* The EEPROM is 512 bytes. */
89#define CFG_EEPROM_SIZE 512
90 /* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
91#define CFG_EEPROM_PAGE_WRITE_BITS 4
92#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
93 /* Put the environment in the second half. */
94#define CFG_ENV_OFFSET 0x00
95#define CFG_ENV_SIZE 512
96
97
98 /* The JSE connects UART1 to the console tap connector. */
99#define CONFIG_UART1_CONSOLE 1
100 /* Set console baudrate to 9600 */
101#define CONFIG_BAUDRATE 9600
102
103/* Size (bytes) of interrupt driven serial port buffer.
104 * Set to 0 to use polling instead of interrupts.
105 * Setting to 0 will also disable RTS/CTS handshaking.
106 */
107#undef CONFIG_SERIAL_SOFTWARE_FIFO
108
109/*
110 * Configuration related to auto-boot.
111 *
112 * CONFIG_BOOTDELAY sets the delay (in seconds) that U-Boot will wait
113 * before resorting to autoboot. This value can be overridden by the
114 * bootdelay environment variable.
115 *
116 * CONFIG_AUTOBOOT_PROMPT is the string that U-Boot emits to warn the
117 * user that an autoboot will happen.
118 *
119 * CONFIG_BOOTCOMMAND is the sequence of commands that U-Boot will
120 * execute to boot the JSE. This loads the uimage and initrd.img files
121 * from CompactFlash into memory, then boots them from memory.
122 *
123 * CONFIG_BOOTARGS is the arguments passed to the Linux kernel to get
124 * it going on the JSE.
125 */
126#define CONFIG_BOOTDELAY 5
127#define CONFIG_BOOTARGS "root=/dev/ram0 init=/linuxrc rw"
128#define CONFIG_BOOTCOMMAND "fatload ace 0 2000000 uimage; fatload ace 0 2100000 initrd.img; bootm 2000000 2100000"
129
130
131#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
132#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
133
134#define CONFIG_MII 1 /* MII PHY management */
135#define CONFIG_PHY_ADDR 1 /* PHY address */
136
137#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
wdenkdb01a2e2004-04-15 23:14:49 +0000138 CFG_CMD_DHCP | \
wdenkdb01a2e2004-04-15 23:14:49 +0000139 CFG_CMD_EEPROM | \
Wolfgang Denk29ca46c2005-10-05 00:25:17 +0200140 CFG_CMD_ELF | \
wdenkdb01a2e2004-04-15 23:14:49 +0000141 CFG_CMD_FAT | \
Wolfgang Denk29ca46c2005-10-05 00:25:17 +0200142 CFG_CMD_FLASH | \
143 CFG_CMD_IRQ | \
144 CFG_CMD_MII | \
145 CFG_CMD_NET | \
146 CFG_CMD_PCI | \
147 CFG_CMD_PING )
wdenkdb01a2e2004-04-15 23:14:49 +0000148
149/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
150#include <cmd_confdefs.h>
151
152 /* watchdog disabled */
153#undef CONFIG_WATCHDOG
154 /* SPD EEPROM (sdram speed config) disabled */
wdenk24711112004-04-18 22:57:51 +0000155#undef CONFIG_SPD_EEPROM
wdenkdb01a2e2004-04-15 23:14:49 +0000156#undef SPD_EEPROM_ADDRESS
157
158/*
159 * Miscellaneous configurable options
160 */
161#define CFG_LONGHELP /* undef to save memory */
162#define CFG_PROMPT "=> " /* Monitor Command Prompt */
163
164#define CFG_HUSH_PARSER /* use "hush" command parser */
165#ifdef CFG_HUSH_PARSER
166#define CFG_PROMPT_HUSH_PS2 "> "
167#endif
168
169#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
170#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
171#else
172#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
173#endif
174#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
175#define CFG_MAXARGS 16 /* max number of command args */
176#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
177
178#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
179#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
180
181/*
182 * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
183 * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
184 * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
185 * The Linux BASE_BAUD define should match this configuration.
186 * baseBaud = cpuClock/(uartDivisor*16)
187 * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
188 * set Linux BASE_BAUD to 403200.
189 */
190#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
191#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
192#define CFG_BASE_BAUD 691200
193
194/* The following table includes the supported baudrates */
195#define CFG_BAUDRATE_TABLE \
196 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
197
198#define CFG_LOAD_ADDR 0x100000 /* default load address */
199#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
200
201#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
202
203#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
204#undef CONFIG_SOFT_I2C /* I2C bit-banged */
205#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
206#define CFG_I2C_SLAVE 0x7F
207
208
209/*-----------------------------------------------------------------------
210 * PCI stuff
211 *-----------------------------------------------------------------------
212 */
213#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
214#define PCI_HOST_FORCE 1 /* configure as pci host */
215#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
216
217#define CONFIG_PCI /* include pci support */
218#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
219#undef CONFIG_PCI_PNP /* do pci plug-and-play */
220 /* resource configuration */
221
222#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
223#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
224#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
225#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
226#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
227#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
228#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
229#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
230
231/*-----------------------------------------------------------------------
232 * External peripheral base address
233 *-----------------------------------------------------------------------
234 */
235#undef CONFIG_IDE_LED /* no led for ide supported */
236#undef CONFIG_IDE_RESET /* no reset for ide supported */
237
238#define CFG_KEY_REG_BASE_ADDR 0xF0100000
239#define CFG_IR_REG_BASE_ADDR 0xF0200000
240#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
241
242/*-----------------------------------------------------------------------
243 * Start addresses for the final memory configuration
244 * (Set up by the startup code)
245 * Please note that CFG_SDRAM_BASE _must_ start at 0
246 */
247#define CFG_SDRAM_BASE 0x00000000
248#define CFG_FLASH_BASE 0xFFF80000
249#define CFG_MONITOR_BASE CFG_FLASH_BASE
250#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
251#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
252
253/*
254 * For booting Linux, the board info and command line data
255 * have to be in the first 8 MB of memory, since this is
256 * the maximum mapped by the Linux kernel during initialization.
257 */
258#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
259
260/*-----------------------------------------------------------------------
261 * FLASH organization
262 */
263#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
264#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
265
266#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
267#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
268
269/*-----------------------------------------------------------------------
270 * Cache Configuration
271 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200272#define CFG_DCACHE_SIZE 16384 /* For AMCC 405GPr CPUs */
wdenkdb01a2e2004-04-15 23:14:49 +0000273#define CFG_CACHELINE_SIZE 32 /* ... */
274#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
275#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
276#endif
277
278/*
279 * Init Memory Controller:
280 *
281 * BR0/1 and OR0/1 (FLASH)
282 */
283
284#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
285#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
286
287
288/* Configuration Port location */
289#define CONFIG_PORT_ADDR 0xF0000500
290
291
292/*
293 * Internal Definitions
294 *
295 * Boot Flags
296 */
297#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
298#define BOOTFLAG_WARM 0x02 /* Software reboot */
299
300#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
301#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
302#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
303#endif
304#endif /* __CONFIG_H */