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wdenk7ca202f2004-08-28 22:45:57 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2005
wdenk7ca202f2004-08-28 22:45:57 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35#define CONFIG_MPC852T 1
36#define CONFIG_NC650 1
37
38#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
39#undef CONFIG_8xx_CONS_SMC2
40#undef CONFIG_8xx_CONS_NONE
41#define CONFIG_BAUDRATE 115200
42#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
43
44/*
45 * 10 MHz - PLL input clock
46 */
wdenkcce625e2004-09-28 19:00:19 +000047#define CONFIG_8xx_OSCLK 10000000
wdenk7ca202f2004-08-28 22:45:57 +000048
49/*
50 * 50 MHz - default CPU clock
51 */
wdenk66ca92a2004-09-28 17:59:53 +000052#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
wdenk7ca202f2004-08-28 22:45:57 +000053
54/*
55 * 15 MHz - CPU minimum clock
56 */
wdenk66ca92a2004-09-28 17:59:53 +000057#define CFG_8xx_CPUCLK_MIN 15000000
wdenk7ca202f2004-08-28 22:45:57 +000058
59/*
60 * 133 MHz - CPU maximum clock
61 */
wdenk66ca92a2004-09-28 17:59:53 +000062#define CFG_8xx_CPUCLK_MAX 133000000
wdenk7ca202f2004-08-28 22:45:57 +000063
64#define CFG_MEASURE_CPUCLK
wdenkcce625e2004-09-28 19:00:19 +000065#define CFG_8XX_XIN CONFIG_8xx_OSCLK
wdenk7ca202f2004-08-28 22:45:57 +000066
67#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
68
69#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
70
71#undef CONFIG_BOOTARGS
72#define CONFIG_BOOTCOMMAND \
73 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010074 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
75 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk7ca202f2004-08-28 22:45:57 +000076 "bootm"
77
78#undef CONFIG_WATCHDOG /* watchdog disabled */
79
80#undef CONFIG_STATUS_LED /* Status LED disabled */
81
82#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
83
84#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
85#define FEC_ENET
86#define CONFIG_MII
87#define CFG_DISCOVER_PHY 1
88
89
90/* enable I2C and select the hardware/software driver */
91#undef CONFIG_HARD_I2C /* I2C with hardware support */
92#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
93#define CFG_I2C_SPEED 100000 /* 100 kHz */
94#define CFG_I2C_SLAVE 0x7f
95
96/*
97 * Software (bit-bang) I2C driver configuration
98 */
wdenk4cfaf552004-10-11 23:03:10 +000099#define SCL 0x1000 /* PA 3 */
100#define SDA 0x2000 /* PA 2 */
wdenk7ca202f2004-08-28 22:45:57 +0000101
Wolfgang Denkf57f70a2005-10-13 01:45:54 +0200102#define __I2C_DIR immr->im_ioport.iop_padir
103#define __I2C_DAT immr->im_ioport.iop_padat
104#define __I2C_PAR immr->im_ioport.iop_papar
105#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \
106 __I2C_DIR |= (SDA|SCL); }
107#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0)
108#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
109#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
110#define I2C_DELAY { udelay(5); }
111#define I2C_ACTIVE { __I2C_DIR |= SDA; }
112#define I2C_TRISTATE { __I2C_DIR &= ~SDA; }
wdenk7ca202f2004-08-28 22:45:57 +0000113
wdenk4cfaf552004-10-11 23:03:10 +0000114#define CONFIG_RTC_PCF8563
115#define CFG_I2C_RTC_ADDR 0x51
wdenk7ca202f2004-08-28 22:45:57 +0000116
117#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
118 CFG_CMD_ASKENV | \
wdenk414eec32005-04-02 22:37:54 +0000119 CFG_CMD_DATE | \
wdenk7ca202f2004-08-28 22:45:57 +0000120 CFG_CMD_DHCP | \
wdenk7ca202f2004-08-28 22:45:57 +0000121 CFG_CMD_I2C | \
wdenk4cfaf552004-10-11 23:03:10 +0000122 CFG_CMD_NAND | \
wdenk07cc0992005-05-05 00:04:14 +0000123 CFG_CMD_JFFS2 | \
wdenk414eec32005-04-02 22:37:54 +0000124 CFG_CMD_NFS | \
125 CFG_CMD_SNTP )
wdenk7ca202f2004-08-28 22:45:57 +0000126
127/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
128#include <cmd_confdefs.h>
129
130/*
131 * Miscellaneous configurable options
132 */
133#define CFG_LONGHELP /* undef to save memory */
134#define CFG_PROMPT "=> " /* Monitor Command Prompt */
135#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
136#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
137#else
138#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
139#endif
140#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
141#define CFG_MAXARGS 16 /* max number of command args */
142#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
143
144#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
145#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
146
147#define CFG_LOAD_ADDR 0x00100000
148
149#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
150
151#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
152
153/*
154 * Low Level Configuration Settings
155 * (address mappings, register initial values, etc.)
156 * You should know what you are doing if you make changes here.
157 */
158/*-----------------------------------------------------------------------
159 * Internal Memory Mapped Register
160 */
161#define CFG_IMMR 0xF0000000
162#define CFG_IMMR_SIZE ((uint)(64 * 1024))
163
164/*-----------------------------------------------------------------------
165 * Definitions for initial stack pointer and data area (in DPRAM)
166 */
167#define CFG_INIT_RAM_ADDR CFG_IMMR
168#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
169#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
170#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
171#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
172
173/*-----------------------------------------------------------------------
174 * Start addresses for the final memory configuration
175 * (Set up by the startup code)
176 * Please note that CFG_SDRAM_BASE _must_ start at 0
177 */
178#define CFG_SDRAM_BASE 0x00000000
179#define CFG_FLASH_BASE 0x40000000
180
181#define CFG_RESET_ADDRESS 0xFFF00100
182
183#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
184#define CFG_MONITOR_BASE TEXT_BASE
185#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
186
187/*
188 * For booting Linux, the board info and command line data
189 * have to be in the first 8 MB of memory, since this is
190 * the maximum mapped by the Linux kernel during initialization.
191 */
192#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
193/*-----------------------------------------------------------------------
194 * FLASH organization
195 */
196#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
197#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
198
199#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
200#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
201
202
203#define CFG_ENV_IS_IN_FLASH 1
204#define CFG_ENV_OFFSET 0x00740000
205
206#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */
207#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */
208
209/*-----------------------------------------------------------------------
210 * Cache Configuration
211 */
212#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
213#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
214#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
215#endif
216
wdenk4cfaf552004-10-11 23:03:10 +0000217/*
218 * NAND flash support
219 */
220#define CFG_MAX_NAND_DEVICE 1
221#define NAND_ChipID_UNKNOWN 0x00
222#define SECTORSIZE 512
223#define NAND_MAX_FLOORS 1
224#define NAND_MAX_CHIPS 1
225#define ADDR_PAGE 2
226#define ADDR_COLUMN_PAGE 3
227#define ADDR_COLUMN 1
228#define NAND_NO_RB
229
230#define NAND_WAIT_READY(nand) udelay(12)
231#define WRITE_NAND_COMMAND(d, adr) WRITE_NAND(d, adr + 2)
232#define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND(d, adr + 1)
233#define WRITE_NAND(d, adr) (*(volatile uint8_t *)(adr) = (uint8_t)(d))
234#define READ_NAND(adr) (*(volatile uint8_t *)(adr))
235#define NAND_DISABLE_CE(nand) /* nop */
236#define NAND_ENABLE_CE(nand) /* nop */
237#define NAND_CTL_CLRALE(nandptr) /* nop */
238#define NAND_CTL_SETALE(nandptr) /* nop */
239#define NAND_CTL_CLRCLE(nandptr) /* nop */
240#define NAND_CTL_SETCLE(nandptr) /* nop */
241
wdenk7ca202f2004-08-28 22:45:57 +0000242/*-----------------------------------------------------------------------
243 * SYPCR - System Protection Control 11-9
244 * SYPCR can only be written once after reset!
245 *-----------------------------------------------------------------------
246 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
247 */
248#if defined(CONFIG_WATCHDOG)
249#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
250 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
251#else
252#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
253#endif
254
255/*-----------------------------------------------------------------------
256 * SIUMCR - SIU Module Configuration 11-6
257 *-----------------------------------------------------------------------
258 */
259#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
260
261/*-----------------------------------------------------------------------
262 * TBSCR - Time Base Status and Control 11-26
263 *-----------------------------------------------------------------------
264 * Clear Reference Interrupt Status, Timebase freezing enabled
265 */
266#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
267
268/*-----------------------------------------------------------------------
269 * PISCR - Periodic Interrupt Status and Control 11-31
270 *-----------------------------------------------------------------------
271 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
272 */
273#define CFG_PISCR (PISCR_PS | PISCR_PITF)
274
275/*-----------------------------------------------------------------------
276 * SCCR - System Clock and reset Control Register 15-27
277 *-----------------------------------------------------------------------
278 * Set clock output, timebase and RTC source and divider,
279 * power management and some other internal clocks
280 */
281#define SCCR_MASK SCCR_EBDF11
282#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | \
283 SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
284 SCCR_DFLCD000 | SCCR_DFALCD00)
285
286 /*-----------------------------------------------------------------------
287 *
288 *-----------------------------------------------------------------------
289 *
290 */
291#define CFG_DER 0
292
293/*
294 * Init Memory Controller:
295 *
296 * BR0 and OR0 (FLASH)
297 */
298
299#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
300
301#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
302#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
303
304/* FLASH timing: Default value of OR0 after reset */
305#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
306 OR_SCY_15_CLK | OR_TRLX)
307
308#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
309#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
310#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
311
312/*
wdenkc3fafec2005-03-14 23:01:03 +0000313 * BR2 and OR2 (NAND Flash) - now addressed through UPMB
wdenk4cfaf552004-10-11 23:03:10 +0000314 */
315#define CFG_NAND_BASE 0x50000000
316#define CFG_NAND_SIZE 0x04000000
317
318#define CFG_OR_TIMING_NAND (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
319 OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
320
wdenkc3fafec2005-03-14 23:01:03 +0000321#define CFG_BR2_PRELIM ((CFG_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_UPMB | BR_V )
wdenk8f0b7cb2005-03-27 23:41:39 +0000322#define CFG_OR2_PRELIM (((-CFG_NAND_SIZE) & OR_AM_MSK) | OR_BI )
wdenk4cfaf552004-10-11 23:03:10 +0000323
324/*
wdenk7ca202f2004-08-28 22:45:57 +0000325 * BR3 and OR3 (SDRAM)
326 */
327#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
328#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
329
330 /*
331 * SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)
332 */
333#define CFG_OR_TIMING_SDRAM 0x00000A00
334
335#define CFG_OR3_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
336#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
337
338/*
wdenkcacfab52004-11-17 20:44:20 +0000339 * BR5 and OR5 (SRAM)
340 */
341#define CFG_SRAM_BASE 0x60000000
342#define CFG_SRAM_SIZE 0x00080000
343
344#define CFG_OR_TIMING_SRAM (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
345 OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
346
347#define CFG_BR5_PRELIM ((CFG_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
348#define CFG_OR5_PRELIM (((-CFG_SRAM_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_SRAM)
349
350
wdenkcacfab52004-11-17 20:44:20 +0000351/*
wdenk7ca202f2004-08-28 22:45:57 +0000352 * 4096 Rows from SDRAM example configuration
353 * 1000 factor s -> ms
354 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
355 * 4 Number of refresh cycles per period
356 * 64 Refresh cycle in ms per number of rows
357 */
wdenk66ca92a2004-09-28 17:59:53 +0000358#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
wdenk7ca202f2004-08-28 22:45:57 +0000359
360/*
361 * Memory Periodic Timer Prescaler
362 */
363
364/* periodic timer for refresh */
365#define CFG_MAMR_PTA 39
366
367/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
368#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
369#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
370
371/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
372#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
373#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
374
375/*
376 * MAMR settings for SDRAM
377 */
378
379#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
380 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
381 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
382#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
383 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
384 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
385
386/*
wdenkc3fafec2005-03-14 23:01:03 +0000387 * MBMR settings for NAND flash
388 */
389
390#define CFG_MBMR_NAND ( MBMR_WLFB_5X )
391
392/*
wdenk7ca202f2004-08-28 22:45:57 +0000393 * Internal Definitions
394 *
395 * Boot Flags
396 */
397#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
398#define BOOTFLAG_WARM 0x02 /* Software reboot */
399
wdenk07cc0992005-05-05 00:04:14 +0000400#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
wdenk07cc0992005-05-05 00:04:14 +0000401#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
wdenk7ca202f2004-08-28 22:45:57 +0000402
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200403/*
404 * JFFS2 partitions
405 */
406
407/* No command line, one static partition */
408#undef CONFIG_JFFS2_CMDLINE
409#define CONFIG_JFFS2_DEV "nand0"
410#define CONFIG_JFFS2_PART_SIZE 0x00400000
411#define CONFIG_JFFS2_PART_OFFSET 0x00000000
412
413/* mtdparts command line support */
414/*
415#define CONFIG_JFFS2_CMDLINE
416#define MTDIDS_DEFAULT "nor0=nc650-0,nand0=nc650-nand"
417
418#define MTDPARTS_DEFAULT "mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \
419 "2560k(cramfs1),2560k(cramfs2)," \
420 "256k(u-boot),256k(env);" \
421 "nc650-nand:4m(nand1),28m(nand2)"
422*/
423
wdenk7ca202f2004-08-28 22:45:57 +0000424#endif /* __CONFIG_H */