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wdenk149dded2003-09-10 18:20:28 +00001/*
2 * URB OHCI HCD (Host Controller Driver) for USB on the S3C2400.
3 *
4 * (C) Copyright 2003
5 * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
6 *
wdenk9d46ea42005-03-14 23:56:42 +00007 * Note: Much of this code has been derived from Linux 2.4
8 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
9 * (C) Copyright 2000-2002 David Brownell
10 *
wdenk149dded2003-09-10 18:20:28 +000011 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 *
wdenk149dded2003-09-10 18:20:28 +000029 */
30/*
31 * IMPORTANT NOTES
32 * 1 - you MUST define LITTLEENDIAN in the configuration file for the
33 * board or this driver will NOT work!
34 * 2 - this driver is intended for use with USB Mass Storage Devices
35 * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
36 */
37
38#include <common.h>
wdenka2663ea2003-12-07 18:32:37 +000039/* #include <pci.h> no PCI on the S3C24X0 */
wdenk149dded2003-09-10 18:20:28 +000040
41#ifdef CONFIG_USB_OHCI
42
wdenka2663ea2003-12-07 18:32:37 +000043#if defined(CONFIG_S3C2400)
wdenk149dded2003-09-10 18:20:28 +000044#include <s3c2400.h>
wdenka2663ea2003-12-07 18:32:37 +000045#elif defined(CONFIG_S3C2410)
46#include <s3c2410.h>
47#endif
48
wdenk149dded2003-09-10 18:20:28 +000049#include <malloc.h>
50#include <usb.h>
51#include "usb_ohci.h"
52
53#define OHCI_USE_NPS /* force NoPowerSwitching mode */
54#undef OHCI_VERBOSE_DEBUG /* not always helpful */
55
56
57/* For initializing controller (mask in an HCFS mode too) */
58#define OHCI_CONTROL_INIT \
59 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
60
wdenk149dded2003-09-10 18:20:28 +000061#define readl(a) (*((vu_long *)(a)))
62#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
63
64#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
65
66#undef DEBUG
67#ifdef DEBUG
68#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
69#else
70#define dbg(format, arg...) do {} while(0)
71#endif /* DEBUG */
72#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
73#undef SHOW_INFO
74#ifdef SHOW_INFO
75#define info(format, arg...) printf("INFO: " format "\n", ## arg)
76#else
77#define info(format, arg...) do {} while(0)
78#endif
79
80#define m16_swap(x) swap_16(x)
81#define m32_swap(x) swap_32(x)
82
83/* global ohci_t */
84static ohci_t gohci;
85/* this must be aligned to a 256 byte boundary */
86struct ohci_hcca ghcca[1];
87/* a pointer to the aligned storage */
88struct ohci_hcca *phcca;
89/* this allocates EDs for all possible endpoints */
90struct ohci_device ohci_dev;
91/* urb_priv */
92urb_priv_t urb_priv;
dzu8a42eac2003-09-29 21:55:54 +000093/* RHSC flag */
94int got_rhsc;
95/* device which was disconnected */
96struct usb_device *devgone;
wdenk149dded2003-09-10 18:20:28 +000097
98/*-------------------------------------------------------------------------*/
99
100/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
101 * The erratum (#4) description is incorrect. AMD's workaround waits
102 * till some bits (mostly reserved) are clear; ok for all revs.
103 */
104#define OHCI_QUIRK_AMD756 0xabcd
105#define read_roothub(hc, register, mask) ({ \
106 u32 temp = readl (&hc->regs->roothub.register); \
107 if (hc->flags & OHCI_QUIRK_AMD756) \
108 while (temp & mask) \
109 temp = readl (&hc->regs->roothub.register); \
110 temp; })
111
112static u32 roothub_a (struct ohci *hc)
113 { return read_roothub (hc, a, 0xfc0fe000); }
114static inline u32 roothub_b (struct ohci *hc)
115 { return readl (&hc->regs->roothub.b); }
116static inline u32 roothub_status (struct ohci *hc)
117 { return readl (&hc->regs->roothub.status); }
118static u32 roothub_portstatus (struct ohci *hc, int i)
119 { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
120
121
122/* forward declaration */
123static int hc_interrupt (void);
124static void
125td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
126 int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
127
128/*-------------------------------------------------------------------------*
129 * URB support functions
130 *-------------------------------------------------------------------------*/
131
132/* free HCD-private data associated with this URB */
133
134static void urb_free_priv (urb_priv_t * urb)
135{
136 int i;
137 int last;
138 struct td * td;
139
140 last = urb->length - 1;
141 if (last >= 0) {
142 for (i = 0; i <= last; i++) {
143 td = urb->td[i];
144 if (td) {
145 td->usb_dev = NULL;
146 urb->td[i] = NULL;
147 }
148 }
149 }
150}
151
152/*-------------------------------------------------------------------------*/
153
154#ifdef DEBUG
155static int sohci_get_current_frame_number (struct usb_device * dev);
156
157/* debug| print the main components of an URB
158 * small: 0) header + data packets 1) just header */
159
160static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
161 int transfer_len, struct devrequest * setup, char * str, int small)
162{
163 urb_priv_t * purb = &urb_priv;
164
165 dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
166 str,
wdenk42d1f032003-10-15 23:53:47 +0000167 sohci_get_current_frame_number (dev),
168 usb_pipedevice (pipe),
169 usb_pipeendpoint (pipe),
170 usb_pipeout (pipe)? 'O': 'I',
171 usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
172 (usb_pipecontrol (pipe)? "CTRL": "BULK"),
173 purb->actual_length,
174 transfer_len, dev->status);
wdenk149dded2003-09-10 18:20:28 +0000175#ifdef OHCI_VERBOSE_DEBUG
176 if (!small) {
177 int i, len;
178
179 if (usb_pipecontrol (pipe)) {
180 printf (__FILE__ ": cmd(8):");
181 for (i = 0; i < 8 ; i++)
182 printf (" %02x", ((__u8 *) setup) [i]);
183 printf ("\n");
184 }
185 if (transfer_len > 0 && buffer) {
186 printf (__FILE__ ": data(%d/%d):",
187 purb->actual_length,
188 transfer_len);
189 len = usb_pipeout (pipe)?
190 transfer_len: purb->actual_length;
191 for (i = 0; i < 16 && i < len; i++)
192 printf (" %02x", ((__u8 *) buffer) [i]);
193 printf ("%s\n", i < len? "...": "");
194 }
195 }
196#endif
197}
198
199/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
200void ep_print_int_eds (ohci_t *ohci, char * str) {
201 int i, j;
202 __u32 * ed_p;
203 for (i= 0; i < 32; i++) {
204 j = 5;
205 ed_p = &(ohci->hcca->int_table [i]);
206 if (*ed_p == 0)
207 continue;
208 printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
209 while (*ed_p != 0 && j--) {
210 ed_t *ed = (ed_t *)m32_swap(ed_p);
211 printf (" ed: %4x;", ed->hwINFO);
212 ed_p = &ed->hwNextED;
213 }
214 printf ("\n");
215 }
216}
217
218static void ohci_dump_intr_mask (char *label, __u32 mask)
219{
220 dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
221 label,
222 mask,
223 (mask & OHCI_INTR_MIE) ? " MIE" : "",
224 (mask & OHCI_INTR_OC) ? " OC" : "",
225 (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
226 (mask & OHCI_INTR_FNO) ? " FNO" : "",
227 (mask & OHCI_INTR_UE) ? " UE" : "",
228 (mask & OHCI_INTR_RD) ? " RD" : "",
229 (mask & OHCI_INTR_SF) ? " SF" : "",
230 (mask & OHCI_INTR_WDH) ? " WDH" : "",
231 (mask & OHCI_INTR_SO) ? " SO" : ""
232 );
233}
234
235static void maybe_print_eds (char *label, __u32 value)
236{
237 ed_t *edp = (ed_t *)value;
238
239 if (value) {
240 dbg ("%s %08x", label, value);
241 dbg ("%08x", edp->hwINFO);
242 dbg ("%08x", edp->hwTailP);
243 dbg ("%08x", edp->hwHeadP);
244 dbg ("%08x", edp->hwNextED);
245 }
246}
247
248static char * hcfs2string (int state)
249{
250 switch (state) {
251 case OHCI_USB_RESET: return "reset";
252 case OHCI_USB_RESUME: return "resume";
253 case OHCI_USB_OPER: return "operational";
254 case OHCI_USB_SUSPEND: return "suspend";
255 }
256 return "?";
257}
258
259/* dump control and status registers */
260static void ohci_dump_status (ohci_t *controller)
261{
262 struct ohci_regs *regs = controller->regs;
263 __u32 temp;
264
265 temp = readl (&regs->revision) & 0xff;
266 if (temp != 0x10)
267 dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
268
269 temp = readl (&regs->control);
270 dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
271 (temp & OHCI_CTRL_RWE) ? " RWE" : "",
272 (temp & OHCI_CTRL_RWC) ? " RWC" : "",
273 (temp & OHCI_CTRL_IR) ? " IR" : "",
274 hcfs2string (temp & OHCI_CTRL_HCFS),
275 (temp & OHCI_CTRL_BLE) ? " BLE" : "",
276 (temp & OHCI_CTRL_CLE) ? " CLE" : "",
277 (temp & OHCI_CTRL_IE) ? " IE" : "",
278 (temp & OHCI_CTRL_PLE) ? " PLE" : "",
279 temp & OHCI_CTRL_CBSR
280 );
281
282 temp = readl (&regs->cmdstatus);
283 dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
284 (temp & OHCI_SOC) >> 16,
285 (temp & OHCI_OCR) ? " OCR" : "",
286 (temp & OHCI_BLF) ? " BLF" : "",
287 (temp & OHCI_CLF) ? " CLF" : "",
288 (temp & OHCI_HCR) ? " HCR" : ""
289 );
290
291 ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
292 ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
293
294 maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
295
296 maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
297 maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
298
299 maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
300 maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
301
302 maybe_print_eds ("donehead", readl (&regs->donehead));
303}
304
305static void ohci_dump_roothub (ohci_t *controller, int verbose)
306{
307 __u32 temp, ndp, i;
308
309 temp = roothub_a (controller);
310 ndp = (temp & RH_A_NDP);
311
312 if (verbose) {
313 dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
314 ((temp & RH_A_POTPGT) >> 24) & 0xff,
315 (temp & RH_A_NOCP) ? " NOCP" : "",
316 (temp & RH_A_OCPM) ? " OCPM" : "",
317 (temp & RH_A_DT) ? " DT" : "",
318 (temp & RH_A_NPS) ? " NPS" : "",
319 (temp & RH_A_PSM) ? " PSM" : "",
320 ndp
321 );
322 temp = roothub_b (controller);
323 dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
324 temp,
325 (temp & RH_B_PPCM) >> 16,
326 (temp & RH_B_DR)
327 );
328 temp = roothub_status (controller);
329 dbg ("roothub.status: %08x%s%s%s%s%s%s",
330 temp,
331 (temp & RH_HS_CRWE) ? " CRWE" : "",
332 (temp & RH_HS_OCIC) ? " OCIC" : "",
333 (temp & RH_HS_LPSC) ? " LPSC" : "",
334 (temp & RH_HS_DRWE) ? " DRWE" : "",
335 (temp & RH_HS_OCI) ? " OCI" : "",
336 (temp & RH_HS_LPS) ? " LPS" : ""
337 );
338 }
339
340 for (i = 0; i < ndp; i++) {
341 temp = roothub_portstatus (controller, i);
342 dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
343 i,
344 temp,
345 (temp & RH_PS_PRSC) ? " PRSC" : "",
346 (temp & RH_PS_OCIC) ? " OCIC" : "",
347 (temp & RH_PS_PSSC) ? " PSSC" : "",
348 (temp & RH_PS_PESC) ? " PESC" : "",
349 (temp & RH_PS_CSC) ? " CSC" : "",
350
351 (temp & RH_PS_LSDA) ? " LSDA" : "",
352 (temp & RH_PS_PPS) ? " PPS" : "",
353 (temp & RH_PS_PRS) ? " PRS" : "",
354 (temp & RH_PS_POCI) ? " POCI" : "",
355 (temp & RH_PS_PSS) ? " PSS" : "",
356
357 (temp & RH_PS_PES) ? " PES" : "",
358 (temp & RH_PS_CCS) ? " CCS" : ""
359 );
360 }
361}
362
363static void ohci_dump (ohci_t *controller, int verbose)
364{
365 dbg ("OHCI controller usb-%s state", controller->slot_name);
366
367 /* dumps some of the state we know about */
368 ohci_dump_status (controller);
369 if (verbose)
370 ep_print_int_eds (controller, "hcca");
371 dbg ("hcca frame #%04x", controller->hcca->frame_no);
372 ohci_dump_roothub (controller, 1);
373}
374
375
376#endif /* DEBUG */
377
378/*-------------------------------------------------------------------------*
379 * Interface functions (URB)
380 *-------------------------------------------------------------------------*/
381
382/* get a transfer request */
383
384int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
385 int transfer_len, struct devrequest *setup, int interval)
386{
387 ohci_t *ohci;
388 ed_t * ed;
389 urb_priv_t *purb_priv;
390 int i, size = 0;
391
392 ohci = &gohci;
393
394 /* when controller's hung, permit only roothub cleanup attempts
395 * such as powering down ports */
396 if (ohci->disabled) {
397 err("sohci_submit_job: EPIPE");
398 return -1;
399 }
400
401 /* every endpoint has a ed, locate and fill it */
402 if (!(ed = ep_add_ed (dev, pipe))) {
403 err("sohci_submit_job: ENOMEM");
404 return -1;
405 }
406
407 /* for the private part of the URB we need the number of TDs (size) */
408 switch (usb_pipetype (pipe)) {
409 case PIPE_BULK: /* one TD for every 4096 Byte */
410 size = (transfer_len - 1) / 4096 + 1;
411 break;
412 case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
413 size = (transfer_len == 0)? 2:
414 (transfer_len - 1) / 4096 + 3;
415 break;
416 }
417
418 if (size >= (N_URB_TD - 1)) {
419 err("need %d TDs, only have %d", size, N_URB_TD);
420 return -1;
421 }
422 purb_priv = &urb_priv;
423 purb_priv->pipe = pipe;
424
425 /* fill the private part of the URB */
426 purb_priv->length = size;
427 purb_priv->ed = ed;
428 purb_priv->actual_length = 0;
429
430 /* allocate the TDs */
431 /* note that td[0] was allocated in ep_add_ed */
432 for (i = 0; i < size; i++) {
433 purb_priv->td[i] = td_alloc (dev);
434 if (!purb_priv->td[i]) {
435 purb_priv->length = i;
436 urb_free_priv (purb_priv);
437 err("sohci_submit_job: ENOMEM");
438 return -1;
439 }
440 }
441
442 if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
443 urb_free_priv (purb_priv);
444 err("sohci_submit_job: EINVAL");
445 return -1;
446 }
447
448 /* link the ed into a chain if is not already */
449 if (ed->state != ED_OPER)
450 ep_link (ohci, ed);
451
452 /* fill the TDs and link it to the ed */
453 td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
454
455 return 0;
456}
457
458/*-------------------------------------------------------------------------*/
459
460#ifdef DEBUG
461/* tell us the current USB frame number */
462
463static int sohci_get_current_frame_number (struct usb_device *usb_dev)
464{
465 ohci_t *ohci = &gohci;
466
467 return m16_swap (ohci->hcca->frame_no);
468}
469#endif
470
471/*-------------------------------------------------------------------------*
472 * ED handling functions
473 *-------------------------------------------------------------------------*/
474
475/* link an ed into one of the HC chains */
476
477static int ep_link (ohci_t *ohci, ed_t *edi)
478{
479 volatile ed_t *ed = edi;
480
481 ed->state = ED_OPER;
482
483 switch (ed->type) {
484 case PIPE_CONTROL:
485 ed->hwNextED = 0;
486 if (ohci->ed_controltail == NULL) {
487 writel (ed, &ohci->regs->ed_controlhead);
488 } else {
489 ohci->ed_controltail->hwNextED = m32_swap (ed);
490 }
491 ed->ed_prev = ohci->ed_controltail;
492 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
493 !ohci->ed_rm_list[1] && !ohci->sleeping) {
494 ohci->hc_control |= OHCI_CTRL_CLE;
495 writel (ohci->hc_control, &ohci->regs->control);
496 }
497 ohci->ed_controltail = edi;
498 break;
499
500 case PIPE_BULK:
501 ed->hwNextED = 0;
502 if (ohci->ed_bulktail == NULL) {
503 writel (ed, &ohci->regs->ed_bulkhead);
504 } else {
505 ohci->ed_bulktail->hwNextED = m32_swap (ed);
506 }
507 ed->ed_prev = ohci->ed_bulktail;
508 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
509 !ohci->ed_rm_list[1] && !ohci->sleeping) {
510 ohci->hc_control |= OHCI_CTRL_BLE;
511 writel (ohci->hc_control, &ohci->regs->control);
512 }
513 ohci->ed_bulktail = edi;
514 break;
515 }
516 return 0;
517}
518
519/*-------------------------------------------------------------------------*/
520
521/* unlink an ed from one of the HC chains.
522 * just the link to the ed is unlinked.
523 * the link from the ed still points to another operational ed or 0
524 * so the HC can eventually finish the processing of the unlinked ed */
525
526static int ep_unlink (ohci_t *ohci, ed_t *ed)
527{
528 ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
529
530 switch (ed->type) {
531 case PIPE_CONTROL:
532 if (ed->ed_prev == NULL) {
533 if (!ed->hwNextED) {
534 ohci->hc_control &= ~OHCI_CTRL_CLE;
535 writel (ohci->hc_control, &ohci->regs->control);
536 }
537 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
538 } else {
539 ed->ed_prev->hwNextED = ed->hwNextED;
540 }
541 if (ohci->ed_controltail == ed) {
542 ohci->ed_controltail = ed->ed_prev;
543 } else {
544 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
545 }
546 break;
547
548 case PIPE_BULK:
549 if (ed->ed_prev == NULL) {
550 if (!ed->hwNextED) {
551 ohci->hc_control &= ~OHCI_CTRL_BLE;
552 writel (ohci->hc_control, &ohci->regs->control);
553 }
554 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
555 } else {
556 ed->ed_prev->hwNextED = ed->hwNextED;
557 }
558 if (ohci->ed_bulktail == ed) {
559 ohci->ed_bulktail = ed->ed_prev;
560 } else {
561 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
562 }
563 break;
564 }
565 ed->state = ED_UNLINK;
566 return 0;
567}
568
569
570/*-------------------------------------------------------------------------*/
571
572/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
573 * but the USB stack is a little bit stateless so we do it at every transaction
574 * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
575 * in all other cases the state is left unchanged
576 * the ed info fields are setted anyway even though most of them should not change */
577
578static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
579{
580 td_t *td;
581 ed_t *ed_ret;
582 volatile ed_t *ed;
583
584 ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
585 (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
586
587 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
588 err("ep_add_ed: pending delete");
589 /* pending delete request */
590 return NULL;
591 }
592
593 if (ed->state == ED_NEW) {
594 ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
wdenk42d1f032003-10-15 23:53:47 +0000595 /* dummy td; end of td list for ed */
wdenk149dded2003-09-10 18:20:28 +0000596 td = td_alloc (usb_dev);
597 ed->hwTailP = m32_swap (td);
598 ed->hwHeadP = ed->hwTailP;
599 ed->state = ED_UNLINK;
600 ed->type = usb_pipetype (pipe);
601 ohci_dev.ed_cnt++;
602 }
603
604 ed->hwINFO = m32_swap (usb_pipedevice (pipe)
605 | usb_pipeendpoint (pipe) << 7
606 | (usb_pipeisoc (pipe)? 0x8000: 0)
607 | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
608 | usb_pipeslow (pipe) << 13
609 | usb_maxpacket (usb_dev, pipe) << 16);
610
611 return ed_ret;
612}
613
614/*-------------------------------------------------------------------------*
615 * TD handling functions
616 *-------------------------------------------------------------------------*/
617
618/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
619
620static void td_fill (ohci_t *ohci, unsigned int info,
621 void *data, int len,
622 struct usb_device *dev, int index, urb_priv_t *urb_priv)
623{
624 volatile td_t *td, *td_pt;
625#ifdef OHCI_FILL_TRACE
626 int i;
627#endif
628
629 if (index > urb_priv->length) {
630 err("index > length");
631 return;
632 }
633 /* use this td as the next dummy */
634 td_pt = urb_priv->td [index];
635 td_pt->hwNextTD = 0;
636
637 /* fill the old dummy TD */
638 td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
639
640 td->ed = urb_priv->ed;
641 td->next_dl_td = NULL;
642 td->index = index;
643 td->data = (__u32)data;
644#ifdef OHCI_FILL_TRACE
645 if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
646 for (i = 0; i < len; i++)
647 printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
648 printf("\n");
649 }
650#endif
651 if (!len)
652 data = 0;
653
654 td->hwINFO = m32_swap (info);
655 td->hwCBP = m32_swap (data);
656 if (data)
657 td->hwBE = m32_swap (data + len - 1);
658 else
659 td->hwBE = 0;
660 td->hwNextTD = m32_swap (td_pt);
661 td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
662
663 /* append to queue */
664 td->ed->hwTailP = td->hwNextTD;
665}
666
667/*-------------------------------------------------------------------------*/
668
669/* prepare all TDs of a transfer */
670
671static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
672 int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
673{
674 ohci_t *ohci = &gohci;
675 int data_len = transfer_len;
676 void *data;
677 int cnt = 0;
678 __u32 info = 0;
wdenk42d1f032003-10-15 23:53:47 +0000679 unsigned int toggle = 0;
wdenk149dded2003-09-10 18:20:28 +0000680
681 /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
wdenk42d1f032003-10-15 23:53:47 +0000682 if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
683 toggle = TD_T_TOGGLE;
wdenk149dded2003-09-10 18:20:28 +0000684 } else {
wdenk42d1f032003-10-15 23:53:47 +0000685 toggle = TD_T_DATA0;
wdenk149dded2003-09-10 18:20:28 +0000686 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
687 }
688 urb->td_cnt = 0;
689 if (data_len)
690 data = buffer;
691 else
692 data = 0;
693
694 switch (usb_pipetype (pipe)) {
695 case PIPE_BULK:
696 info = usb_pipeout (pipe)?
697 TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
698 while(data_len > 4096) {
699 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
700 data += 4096; data_len -= 4096; cnt++;
701 }
702 info = usb_pipeout (pipe)?
703 TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
704 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
705 cnt++;
706
707 if (!ohci->sleeping)
708 writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
709 break;
710
711 case PIPE_CONTROL:
712 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
713 td_fill (ohci, info, setup, 8, dev, cnt++, urb);
714 if (data_len > 0) {
715 info = usb_pipeout (pipe)?
716 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
717 /* NOTE: mishandles transfers >8K, some >4K */
718 td_fill (ohci, info, data, data_len, dev, cnt++, urb);
719 }
720 info = usb_pipeout (pipe)?
721 TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
722 td_fill (ohci, info, data, 0, dev, cnt++, urb);
723 if (!ohci->sleeping)
724 writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
725 break;
726 }
727 if (urb->length != cnt)
728 dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
729}
730
731/*-------------------------------------------------------------------------*
732 * Done List handling functions
733 *-------------------------------------------------------------------------*/
734
735
736/* calculate the transfer length and update the urb */
737
738static void dl_transfer_length(td_t * td)
739{
740 __u32 tdINFO, tdBE, tdCBP;
wdenk42d1f032003-10-15 23:53:47 +0000741 urb_priv_t *lurb_priv = &urb_priv;
wdenk149dded2003-09-10 18:20:28 +0000742
743 tdINFO = m32_swap (td->hwINFO);
wdenk42d1f032003-10-15 23:53:47 +0000744 tdBE = m32_swap (td->hwBE);
745 tdCBP = m32_swap (td->hwCBP);
wdenk149dded2003-09-10 18:20:28 +0000746
747
748 if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
749 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
750 if (tdBE != 0) {
751 if (td->hwCBP == 0)
752 lurb_priv->actual_length += tdBE - td->data + 1;
753 else
754 lurb_priv->actual_length += tdCBP - td->data;
755 }
756 }
757}
758
759/*-------------------------------------------------------------------------*/
760
761/* replies to the request have to be on a FIFO basis so
762 * we reverse the reversed done-list */
763
764static td_t * dl_reverse_done_list (ohci_t *ohci)
765{
766 __u32 td_list_hc;
767 td_t *td_rev = NULL;
768 td_t *td_list = NULL;
wdenk42d1f032003-10-15 23:53:47 +0000769 urb_priv_t *lurb_priv = NULL;
wdenk149dded2003-09-10 18:20:28 +0000770
771 td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
772 ohci->hcca->done_head = 0;
773
774 while (td_list_hc) {
775 td_list = (td_t *)td_list_hc;
776
777 if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
778 lurb_priv = &urb_priv;
779 dbg(" USB-error/status: %x : %p",
780 TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
781 if (td_list->ed->hwHeadP & m32_swap (0x1)) {
782 if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
783 td_list->ed->hwHeadP =
784 (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
785 (td_list->ed->hwHeadP & m32_swap (0x2));
786 lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
787 } else
788 td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
789 }
790 }
791
792 td_list->next_dl_td = td_rev;
793 td_rev = td_list;
794 td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
795 }
796 return td_list;
797}
798
799/*-------------------------------------------------------------------------*/
800
801/* td done list */
802static int dl_done_list (ohci_t *ohci, td_t *td_list)
803{
wdenk42d1f032003-10-15 23:53:47 +0000804 td_t *td_list_next = NULL;
wdenk149dded2003-09-10 18:20:28 +0000805 ed_t *ed;
806 int cc = 0;
807 int stat = 0;
808 /* urb_t *urb; */
809 urb_priv_t *lurb_priv;
wdenk42d1f032003-10-15 23:53:47 +0000810 __u32 tdINFO, edHeadP, edTailP;
wdenk149dded2003-09-10 18:20:28 +0000811
wdenk42d1f032003-10-15 23:53:47 +0000812 while (td_list) {
813 td_list_next = td_list->next_dl_td;
wdenk149dded2003-09-10 18:20:28 +0000814
wdenk42d1f032003-10-15 23:53:47 +0000815 lurb_priv = &urb_priv;
816 tdINFO = m32_swap (td_list->hwINFO);
wdenk149dded2003-09-10 18:20:28 +0000817
wdenk42d1f032003-10-15 23:53:47 +0000818 ed = td_list->ed;
wdenk149dded2003-09-10 18:20:28 +0000819
wdenk42d1f032003-10-15 23:53:47 +0000820 dl_transfer_length(td_list);
wdenk149dded2003-09-10 18:20:28 +0000821
wdenk42d1f032003-10-15 23:53:47 +0000822 /* error code of transfer */
823 cc = TD_CC_GET (tdINFO);
wdenk149dded2003-09-10 18:20:28 +0000824 if (cc != 0) {
825 dbg("ConditionCode %#x", cc);
826 stat = cc_to_error[cc];
827 }
828
wdenk42d1f032003-10-15 23:53:47 +0000829 if (ed->state != ED_NEW) {
830 edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
831 edTailP = m32_swap (ed->hwTailP);
wdenk149dded2003-09-10 18:20:28 +0000832
833 /* unlink eds if they are not busy */
wdenk42d1f032003-10-15 23:53:47 +0000834 if ((edHeadP == edTailP) && (ed->state == ED_OPER))
835 ep_unlink (ohci, ed);
836 }
wdenk149dded2003-09-10 18:20:28 +0000837
wdenk42d1f032003-10-15 23:53:47 +0000838 td_list = td_list_next;
839 }
wdenk149dded2003-09-10 18:20:28 +0000840 return stat;
841}
842
843/*-------------------------------------------------------------------------*
844 * Virtual Root Hub
845 *-------------------------------------------------------------------------*/
846
847/* Device descriptor */
848static __u8 root_hub_dev_des[] =
849{
850 0x12, /* __u8 bLength; */
851 0x01, /* __u8 bDescriptorType; Device */
852 0x10, /* __u16 bcdUSB; v1.1 */
853 0x01,
854 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
855 0x00, /* __u8 bDeviceSubClass; */
856 0x00, /* __u8 bDeviceProtocol; */
857 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
858 0x00, /* __u16 idVendor; */
859 0x00,
860 0x00, /* __u16 idProduct; */
wdenk42d1f032003-10-15 23:53:47 +0000861 0x00,
wdenk149dded2003-09-10 18:20:28 +0000862 0x00, /* __u16 bcdDevice; */
wdenk42d1f032003-10-15 23:53:47 +0000863 0x00,
wdenk149dded2003-09-10 18:20:28 +0000864 0x00, /* __u8 iManufacturer; */
865 0x01, /* __u8 iProduct; */
866 0x00, /* __u8 iSerialNumber; */
867 0x01 /* __u8 bNumConfigurations; */
868};
869
870
871/* Configuration descriptor */
872static __u8 root_hub_config_des[] =
873{
874 0x09, /* __u8 bLength; */
875 0x02, /* __u8 bDescriptorType; Configuration */
876 0x19, /* __u16 wTotalLength; */
877 0x00,
878 0x01, /* __u8 bNumInterfaces; */
879 0x01, /* __u8 bConfigurationValue; */
880 0x00, /* __u8 iConfiguration; */
881 0x40, /* __u8 bmAttributes;
wdenk42d1f032003-10-15 23:53:47 +0000882 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
wdenk149dded2003-09-10 18:20:28 +0000883 0x00, /* __u8 MaxPower; */
884
885 /* interface */
886 0x09, /* __u8 if_bLength; */
887 0x04, /* __u8 if_bDescriptorType; Interface */
888 0x00, /* __u8 if_bInterfaceNumber; */
889 0x00, /* __u8 if_bAlternateSetting; */
890 0x01, /* __u8 if_bNumEndpoints; */
891 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
892 0x00, /* __u8 if_bInterfaceSubClass; */
893 0x00, /* __u8 if_bInterfaceProtocol; */
894 0x00, /* __u8 if_iInterface; */
895
896 /* endpoint */
897 0x07, /* __u8 ep_bLength; */
898 0x05, /* __u8 ep_bDescriptorType; Endpoint */
899 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
wdenk42d1f032003-10-15 23:53:47 +0000900 0x03, /* __u8 ep_bmAttributes; Interrupt */
901 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
902 0x00,
wdenk149dded2003-09-10 18:20:28 +0000903 0xff /* __u8 ep_bInterval; 255 ms */
904};
905
906static unsigned char root_hub_str_index0[] =
907{
908 0x04, /* __u8 bLength; */
909 0x03, /* __u8 bDescriptorType; String-descriptor */
910 0x09, /* __u8 lang ID */
911 0x04, /* __u8 lang ID */
912};
913
914static unsigned char root_hub_str_index1[] =
915{
916 28, /* __u8 bLength; */
917 0x03, /* __u8 bDescriptorType; String-descriptor */
918 'O', /* __u8 Unicode */
919 0, /* __u8 Unicode */
920 'H', /* __u8 Unicode */
921 0, /* __u8 Unicode */
922 'C', /* __u8 Unicode */
923 0, /* __u8 Unicode */
924 'I', /* __u8 Unicode */
925 0, /* __u8 Unicode */
926 ' ', /* __u8 Unicode */
927 0, /* __u8 Unicode */
928 'R', /* __u8 Unicode */
929 0, /* __u8 Unicode */
930 'o', /* __u8 Unicode */
931 0, /* __u8 Unicode */
932 'o', /* __u8 Unicode */
933 0, /* __u8 Unicode */
934 't', /* __u8 Unicode */
935 0, /* __u8 Unicode */
936 ' ', /* __u8 Unicode */
937 0, /* __u8 Unicode */
938 'H', /* __u8 Unicode */
939 0, /* __u8 Unicode */
940 'u', /* __u8 Unicode */
941 0, /* __u8 Unicode */
942 'b', /* __u8 Unicode */
943 0, /* __u8 Unicode */
944};
945
946/* Hub class-specific descriptor is constructed dynamically */
947
948
949/*-------------------------------------------------------------------------*/
950
951#define OK(x) len = (x); break
952#ifdef DEBUG
953#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
954#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
955#else
956#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
957#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
958#endif
959#define RD_RH_STAT roothub_status(&gohci)
960#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
961
962/* request to virtual root hub */
963
dzu8a42eac2003-09-29 21:55:54 +0000964int rh_check_port_status(ohci_t *controller)
965{
966 __u32 temp, ndp, i;
967 int res;
968
969 res = -1;
970 temp = roothub_a (controller);
971 ndp = (temp & RH_A_NDP);
972 for (i = 0; i < ndp; i++) {
973 temp = roothub_portstatus (controller, i);
974 /* check for a device disconnect */
975 if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
976 (RH_PS_PESC | RH_PS_CSC)) &&
977 ((temp & RH_PS_CCS) == 0)) {
978 res = i;
979 break;
980 }
981 }
982 return res;
983}
984
985static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
986 void *buffer, int transfer_len, struct devrequest *cmd)
wdenk149dded2003-09-10 18:20:28 +0000987{
988 void * data = buffer;
989 int leni = transfer_len;
990 int len = 0;
991 int stat = 0;
992 __u32 datab[4];
993 __u8 *data_buf = (__u8 *)datab;
wdenk42d1f032003-10-15 23:53:47 +0000994 __u16 bmRType_bReq;
wdenk149dded2003-09-10 18:20:28 +0000995 __u16 wValue;
996 __u16 wIndex;
997 __u16 wLength;
998
999#ifdef DEBUG
1000urb_priv.actual_length = 0;
1001pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
1002#else
1003 wait_ms(1);
1004#endif
1005 if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
1006 info("Root-Hub submit IRQ: NOT implemented");
1007 return 0;
1008 }
1009
1010 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
1011 wValue = m16_swap (cmd->value);
1012 wIndex = m16_swap (cmd->index);
1013 wLength = m16_swap (cmd->length);
1014
1015 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
1016 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
1017
1018 switch (bmRType_bReq) {
1019 /* Request Destination:
1020 without flags: Device,
1021 RH_INTERFACE: interface,
1022 RH_ENDPOINT: endpoint,
1023 RH_CLASS means HUB here,
1024 RH_OTHER | RH_CLASS almost ever means HUB_PORT here
1025 */
1026
1027 case RH_GET_STATUS:
1028 *(__u16 *) data_buf = m16_swap (1); OK (2);
1029 case RH_GET_STATUS | RH_INTERFACE:
1030 *(__u16 *) data_buf = m16_swap (0); OK (2);
1031 case RH_GET_STATUS | RH_ENDPOINT:
1032 *(__u16 *) data_buf = m16_swap (0); OK (2);
1033 case RH_GET_STATUS | RH_CLASS:
1034 *(__u32 *) data_buf = m32_swap (
1035 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
1036 OK (4);
1037 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
1038 *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
1039
1040 case RH_CLEAR_FEATURE | RH_ENDPOINT:
1041 switch (wValue) {
1042 case (RH_ENDPOINT_STALL): OK (0);
1043 }
1044 break;
1045
1046 case RH_CLEAR_FEATURE | RH_CLASS:
1047 switch (wValue) {
1048 case RH_C_HUB_LOCAL_POWER:
1049 OK(0);
1050 case (RH_C_HUB_OVER_CURRENT):
1051 WR_RH_STAT(RH_HS_OCIC); OK (0);
1052 }
1053 break;
1054
1055 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
1056 switch (wValue) {
1057 case (RH_PORT_ENABLE):
1058 WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
1059 case (RH_PORT_SUSPEND):
1060 WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
1061 case (RH_PORT_POWER):
1062 WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
1063 case (RH_C_PORT_CONNECTION):
1064 WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
1065 case (RH_C_PORT_ENABLE):
1066 WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
1067 case (RH_C_PORT_SUSPEND):
1068 WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
1069 case (RH_C_PORT_OVER_CURRENT):
1070 WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
1071 case (RH_C_PORT_RESET):
1072 WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
1073 }
1074 break;
1075
1076 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
1077 switch (wValue) {
1078 case (RH_PORT_SUSPEND):
1079 WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
1080 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
1081 if (RD_RH_PORTSTAT & RH_PS_CCS)
1082 WR_RH_PORTSTAT (RH_PS_PRS);
1083 OK (0);
1084 case (RH_PORT_POWER):
1085 WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
1086 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
1087 if (RD_RH_PORTSTAT & RH_PS_CCS)
1088 WR_RH_PORTSTAT (RH_PS_PES );
1089 OK (0);
1090 }
1091 break;
1092
1093 case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
1094
1095 case RH_GET_DESCRIPTOR:
1096 switch ((wValue & 0xff00) >> 8) {
1097 case (0x01): /* device descriptor */
1098 len = min_t(unsigned int,
1099 leni,
1100 min_t(unsigned int,
1101 sizeof (root_hub_dev_des),
1102 wLength));
1103 data_buf = root_hub_dev_des; OK(len);
1104 case (0x02): /* configuration descriptor */
1105 len = min_t(unsigned int,
1106 leni,
1107 min_t(unsigned int,
1108 sizeof (root_hub_config_des),
1109 wLength));
1110 data_buf = root_hub_config_des; OK(len);
1111 case (0x03): /* string descriptors */
1112 if(wValue==0x0300) {
1113 len = min_t(unsigned int,
1114 leni,
1115 min_t(unsigned int,
1116 sizeof (root_hub_str_index0),
1117 wLength));
1118 data_buf = root_hub_str_index0;
1119 OK(len);
1120 }
1121 if(wValue==0x0301) {
1122 len = min_t(unsigned int,
1123 leni,
1124 min_t(unsigned int,
1125 sizeof (root_hub_str_index1),
1126 wLength));
1127 data_buf = root_hub_str_index1;
1128 OK(len);
1129 }
1130 default:
1131 stat = USB_ST_STALLED;
1132 }
1133 break;
1134
1135 case RH_GET_DESCRIPTOR | RH_CLASS:
1136 {
1137 __u32 temp = roothub_a (&gohci);
1138
1139 data_buf [0] = 9; /* min length; */
1140 data_buf [1] = 0x29;
1141 data_buf [2] = temp & RH_A_NDP;
1142 data_buf [3] = 0;
1143 if (temp & RH_A_PSM) /* per-port power switching? */
1144 data_buf [3] |= 0x1;
1145 if (temp & RH_A_NOCP) /* no overcurrent reporting? */
1146 data_buf [3] |= 0x10;
1147 else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
1148 data_buf [3] |= 0x8;
1149
1150 /* corresponds to data_buf[4-7] */
1151 datab [1] = 0;
1152 data_buf [5] = (temp & RH_A_POTPGT) >> 24;
1153 temp = roothub_b (&gohci);
1154 data_buf [7] = temp & RH_B_DR;
1155 if (data_buf [2] < 7) {
1156 data_buf [8] = 0xff;
1157 } else {
1158 data_buf [0] += 2;
1159 data_buf [8] = (temp & RH_B_DR) >> 8;
1160 data_buf [10] = data_buf [9] = 0xff;
1161 }
1162
1163 len = min_t(unsigned int, leni,
1164 min_t(unsigned int, data_buf [0], wLength));
1165 OK (len);
1166 }
1167
1168 case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
1169
1170 case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
1171
1172 default:
1173 dbg ("unsupported root hub command");
1174 stat = USB_ST_STALLED;
1175 }
1176
1177#ifdef DEBUG
1178 ohci_dump_roothub (&gohci, 1);
1179#else
1180 wait_ms(1);
1181#endif
1182
1183 len = min_t(int, len, leni);
1184 if (data != data_buf)
1185 memcpy (data, data_buf, len);
wdenk42d1f032003-10-15 23:53:47 +00001186 dev->act_len = len;
wdenk149dded2003-09-10 18:20:28 +00001187 dev->status = stat;
1188
1189#ifdef DEBUG
1190 if (transfer_len)
1191 urb_priv.actual_length = transfer_len;
1192 pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
1193#else
1194 wait_ms(1);
1195#endif
1196
1197 return stat;
1198}
1199
1200/*-------------------------------------------------------------------------*/
1201
1202/* common code for handling submit messages - used for all but root hub */
1203/* accesses. */
1204int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1205 int transfer_len, struct devrequest *setup, int interval)
1206{
1207 int stat = 0;
1208 int maxsize = usb_maxpacket(dev, pipe);
1209 int timeout;
1210
dzu8a42eac2003-09-29 21:55:54 +00001211 /* device pulled? Shortcut the action. */
1212 if (devgone == dev) {
1213 dev->status = USB_ST_CRC_ERR;
1214 return 0;
1215 }
1216
wdenk149dded2003-09-10 18:20:28 +00001217#ifdef DEBUG
1218 urb_priv.actual_length = 0;
1219 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1220#else
1221 wait_ms(1);
1222#endif
1223 if (!maxsize) {
1224 err("submit_common_message: pipesize for pipe %lx is zero",
1225 pipe);
1226 return -1;
1227 }
1228
1229 if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
1230 err("sohci_submit_job failed");
1231 return -1;
1232 }
1233
1234 wait_ms(10);
1235 /* ohci_dump_status(&gohci); */
wdenk42d1f032003-10-15 23:53:47 +00001236
wdenka43278a2003-09-11 19:48:06 +00001237 /* allow more time for a BULK device to react - some are slow */
wdenkb0639ca2003-09-17 22:48:07 +00001238#define BULK_TO 5000 /* timeout in milliseconds */
wdenka43278a2003-09-11 19:48:06 +00001239 if (usb_pipetype (pipe) == PIPE_BULK)
1240 timeout = BULK_TO;
1241 else
1242 timeout = 100;
1243
wdenk149dded2003-09-10 18:20:28 +00001244 /* wait for it to complete */
wdenk149dded2003-09-10 18:20:28 +00001245 for (;;) {
1246 /* check whether the controller is done */
1247 stat = hc_interrupt();
1248 if (stat < 0) {
dzu8a42eac2003-09-29 21:55:54 +00001249 stat = USB_ST_CRC_ERR;
wdenk149dded2003-09-10 18:20:28 +00001250 break;
1251 }
1252 if (stat >= 0 && stat != 0xff) {
1253 /* 0xff is returned for an SF-interrupt */
1254 break;
1255 }
1256 if (--timeout) {
1257 wait_ms(1);
1258 } else {
dzu8a42eac2003-09-29 21:55:54 +00001259 err("CTL:TIMEOUT ");
1260 stat = USB_ST_CRC_ERR;
wdenk149dded2003-09-10 18:20:28 +00001261 break;
1262 }
1263 }
dzu8a42eac2003-09-29 21:55:54 +00001264 /* we got an Root Hub Status Change interrupt */
1265 if (got_rhsc) {
1266#ifdef DEBUG
1267 ohci_dump_roothub (&gohci, 1);
1268#endif
1269 got_rhsc = 0;
1270 /* abuse timeout */
1271 timeout = rh_check_port_status(&gohci);
1272 if (timeout >= 0) {
1273#if 0 /* this does nothing useful, but leave it here in case that changes */
1274 /* the called routine adds 1 to the passed value */
1275 usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
1276#endif
1277 /*
1278 * XXX
1279 * This is potentially dangerous because it assumes
1280 * that only one device is ever plugged in!
1281 */
1282 devgone = dev;
1283 }
1284 }
1285
wdenk149dded2003-09-10 18:20:28 +00001286 dev->status = stat;
wdenk42d1f032003-10-15 23:53:47 +00001287 dev->act_len = transfer_len;
wdenk149dded2003-09-10 18:20:28 +00001288
1289#ifdef DEBUG
1290 pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
1291#else
1292 wait_ms(1);
1293#endif
1294
1295 /* free TDs in urb_priv */
1296 urb_free_priv (&urb_priv);
1297 return 0;
1298}
1299
1300/* submit routines called from usb.c */
1301int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1302 int transfer_len)
1303{
1304 info("submit_bulk_msg");
1305 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
1306}
1307
1308int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1309 int transfer_len, struct devrequest *setup)
1310{
1311 int maxsize = usb_maxpacket(dev, pipe);
1312
1313 info("submit_control_msg");
1314#ifdef DEBUG
1315 urb_priv.actual_length = 0;
1316 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1317#else
1318 wait_ms(1);
1319#endif
1320 if (!maxsize) {
1321 err("submit_control_message: pipesize for pipe %lx is zero",
1322 pipe);
1323 return -1;
1324 }
dzu8a42eac2003-09-29 21:55:54 +00001325 if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
1326 gohci.rh.dev = dev;
wdenk149dded2003-09-10 18:20:28 +00001327 /* root hub - redirect */
1328 return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
1329 setup);
dzu8a42eac2003-09-29 21:55:54 +00001330 }
wdenk149dded2003-09-10 18:20:28 +00001331
1332 return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
1333}
1334
1335int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1336 int transfer_len, int interval)
1337{
1338 info("submit_int_msg");
1339 return -1;
1340}
1341
1342/*-------------------------------------------------------------------------*
1343 * HC functions
1344 *-------------------------------------------------------------------------*/
1345
1346/* reset the HC and BUS */
1347
1348static int hc_reset (ohci_t *ohci)
1349{
1350 int timeout = 30;
1351 int smm_timeout = 50; /* 0,5 sec */
1352
1353 if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
1354 writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
1355 info("USB HC TakeOver from SMM");
1356 while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
1357 wait_ms (10);
1358 if (--smm_timeout == 0) {
1359 err("USB HC TakeOver failed!");
1360 return -1;
1361 }
1362 }
1363 }
1364
1365 /* Disable HC interrupts */
1366 writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
1367
1368 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
1369 ohci->slot_name,
1370 readl (&ohci->regs->control));
1371
wdenk42d1f032003-10-15 23:53:47 +00001372 /* Reset USB (needed by some controllers) */
wdenk149dded2003-09-10 18:20:28 +00001373 writel (0, &ohci->regs->control);
1374
1375 /* HC Reset requires max 10 us delay */
1376 writel (OHCI_HCR, &ohci->regs->cmdstatus);
1377 while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1378 if (--timeout == 0) {
1379 err("USB HC reset timed out!");
1380 return -1;
1381 }
1382 udelay (1);
1383 }
1384 return 0;
1385}
1386
1387/*-------------------------------------------------------------------------*/
1388
1389/* Start an OHCI controller, set the BUS operational
1390 * enable interrupts
1391 * connect the virtual root hub */
1392
1393static int hc_start (ohci_t * ohci)
1394{
wdenk42d1f032003-10-15 23:53:47 +00001395 __u32 mask;
1396 unsigned int fminterval;
wdenk149dded2003-09-10 18:20:28 +00001397
1398 ohci->disabled = 1;
1399
1400 /* Tell the controller where the control and bulk lists are
1401 * The lists are empty now. */
1402
1403 writel (0, &ohci->regs->ed_controlhead);
1404 writel (0, &ohci->regs->ed_bulkhead);
1405
1406 writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
1407
wdenk42d1f032003-10-15 23:53:47 +00001408 fminterval = 0x2edf;
wdenk149dded2003-09-10 18:20:28 +00001409 writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
1410 fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
1411 writel (fminterval, &ohci->regs->fminterval);
1412 writel (0x628, &ohci->regs->lsthresh);
1413
wdenk42d1f032003-10-15 23:53:47 +00001414 /* start controller operations */
1415 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
wdenk149dded2003-09-10 18:20:28 +00001416 ohci->disabled = 0;
wdenk42d1f032003-10-15 23:53:47 +00001417 writel (ohci->hc_control, &ohci->regs->control);
wdenk149dded2003-09-10 18:20:28 +00001418
dzu8a42eac2003-09-29 21:55:54 +00001419 /* disable all interrupts */
1420 mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
1421 OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
1422 OHCI_INTR_OC | OHCI_INTR_MIE);
1423 writel (mask, &ohci->regs->intrdisable);
1424 /* clear all interrupts */
1425 mask &= ~OHCI_INTR_MIE;
wdenk149dded2003-09-10 18:20:28 +00001426 writel (mask, &ohci->regs->intrstatus);
dzu8a42eac2003-09-29 21:55:54 +00001427 /* Choose the interrupts we care about now - but w/o MIE */
1428 mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
1429 writel (mask, &ohci->regs->intrenable);
wdenk149dded2003-09-10 18:20:28 +00001430
1431#ifdef OHCI_USE_NPS
1432 /* required for AMD-756 and some Mac platforms */
1433 writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
1434 &ohci->regs->roothub.a);
1435 writel (RH_HS_LPSC, &ohci->regs->roothub.status);
1436#endif /* OHCI_USE_NPS */
1437
1438#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
1439 /* POTPGT delay is bits 24-31, in 2 ms units. */
1440 mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
1441
1442 /* connect the virtual root hub */
1443 ohci->rh.devnum = 0;
1444
1445 return 0;
1446}
1447
1448/*-------------------------------------------------------------------------*/
1449
1450/* an interrupt happens */
1451
1452static int
1453hc_interrupt (void)
1454{
1455 ohci_t *ohci = &gohci;
1456 struct ohci_regs *regs = ohci->regs;
wdenk42d1f032003-10-15 23:53:47 +00001457 int ints;
wdenk149dded2003-09-10 18:20:28 +00001458 int stat = -1;
1459
1460 if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
1461 ints = OHCI_INTR_WDH;
1462 } else {
1463 ints = readl (&regs->intrstatus);
1464 }
1465
1466 /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
1467
dzu8a42eac2003-09-29 21:55:54 +00001468 if (ints & OHCI_INTR_RHSC) {
1469 got_rhsc = 1;
1470 }
1471
wdenk149dded2003-09-10 18:20:28 +00001472 if (ints & OHCI_INTR_UE) {
1473 ohci->disabled++;
1474 err ("OHCI Unrecoverable Error, controller usb-%s disabled",
1475 ohci->slot_name);
1476 /* e.g. due to PCI Master/Target Abort */
1477
1478#ifdef DEBUG
1479 ohci_dump (ohci, 1);
1480#else
1481 wait_ms(1);
1482#endif
1483 /* FIXME: be optimistic, hope that bug won't repeat often. */
1484 /* Make some non-interrupt context restart the controller. */
1485 /* Count and limit the retries though; either hardware or */
1486 /* software errors can go forever... */
1487 hc_reset (ohci);
1488 return -1;
1489 }
1490
1491 if (ints & OHCI_INTR_WDH) {
1492 wait_ms(1);
1493 writel (OHCI_INTR_WDH, &regs->intrdisable);
1494 stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
1495 writel (OHCI_INTR_WDH, &regs->intrenable);
1496 }
1497
1498 if (ints & OHCI_INTR_SO) {
1499 dbg("USB Schedule overrun\n");
1500 writel (OHCI_INTR_SO, &regs->intrenable);
1501 stat = -1;
1502 }
1503
1504 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
1505 if (ints & OHCI_INTR_SF) {
1506 unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
1507 wait_ms(1);
1508 writel (OHCI_INTR_SF, &regs->intrdisable);
1509 if (ohci->ed_rm_list[frame] != NULL)
1510 writel (OHCI_INTR_SF, &regs->intrenable);
1511 stat = 0xff;
1512 }
1513
1514 writel (ints, &regs->intrstatus);
1515 return stat;
1516}
1517
1518/*-------------------------------------------------------------------------*/
1519
1520/*-------------------------------------------------------------------------*/
1521
1522/* De-allocate all resources.. */
1523
1524static void hc_release_ohci (ohci_t *ohci)
1525{
1526 dbg ("USB HC release ohci usb-%s", ohci->slot_name);
1527
1528 if (!ohci->disabled)
1529 hc_reset (ohci);
1530}
1531
1532/*-------------------------------------------------------------------------*/
1533
1534/*
1535 * low level initalisation routine, called from usb.c
1536 */
1537static char ohci_inited = 0;
1538
1539int usb_lowlevel_init(void)
1540{
1541 S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
1542 S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
1543
wdenk42d1f032003-10-15 23:53:47 +00001544 /*
1545 * Set the 48 MHz UPLL clocking. Values are taken from
1546 * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
1547 */
1548 clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
1549 gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
wdenk149dded2003-09-10 18:20:28 +00001550
wdenk42d1f032003-10-15 23:53:47 +00001551 /*
1552 * Enable USB host clock.
1553 */
1554 clk_power->CLKCON |= (1 << 4);
wdenk149dded2003-09-10 18:20:28 +00001555
1556 memset (&gohci, 0, sizeof (ohci_t));
1557 memset (&urb_priv, 0, sizeof (urb_priv_t));
1558
1559 /* align the storage */
1560 if ((__u32)&ghcca[0] & 0xff) {
1561 err("HCCA not aligned!!");
1562 return -1;
1563 }
1564 phcca = &ghcca[0];
1565 info("aligned ghcca %p", phcca);
1566 memset(&ohci_dev, 0, sizeof(struct ohci_device));
1567 if ((__u32)&ohci_dev.ed[0] & 0x7) {
1568 err("EDs not aligned!!");
1569 return -1;
1570 }
1571 memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
1572 if ((__u32)gtd & 0x7) {
1573 err("TDs not aligned!!");
1574 return -1;
1575 }
1576 ptd = gtd;
1577 gohci.hcca = phcca;
wdenk42d1f032003-10-15 23:53:47 +00001578 memset (phcca, 0, sizeof (struct ohci_hcca));
wdenk149dded2003-09-10 18:20:28 +00001579
1580 gohci.disabled = 1;
1581 gohci.sleeping = 0;
1582 gohci.irq = -1;
1583 gohci.regs = (struct ohci_regs *)S3C24X0_USB_HOST_BASE;
1584
1585 gohci.flags = 0;
1586 gohci.slot_name = "s3c2400";
1587
1588 if (hc_reset (&gohci) < 0) {
1589 hc_release_ohci (&gohci);
wdenk42d1f032003-10-15 23:53:47 +00001590 /* Initialization failed */
1591 clk_power->CLKCON &= ~(1 << 4);
wdenk149dded2003-09-10 18:20:28 +00001592 return -1;
1593 }
1594
1595 /* FIXME this is a second HC reset; why?? */
1596 writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
1597 wait_ms (10);
1598
1599 if (hc_start (&gohci) < 0) {
1600 err ("can't start usb-%s", gohci.slot_name);
1601 hc_release_ohci (&gohci);
wdenk42d1f032003-10-15 23:53:47 +00001602 /* Initialization failed */
1603 clk_power->CLKCON &= ~(1 << 4);
wdenk149dded2003-09-10 18:20:28 +00001604 return -1;
1605 }
1606
1607#ifdef DEBUG
1608 ohci_dump (&gohci, 1);
1609#else
1610 wait_ms(1);
1611#endif
1612 ohci_inited = 1;
1613 return 0;
1614}
1615
1616int usb_lowlevel_stop(void)
1617{
1618 S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
1619
1620 /* this gets called really early - before the controller has */
1621 /* even been initialized! */
1622 if (!ohci_inited)
1623 return 0;
1624 /* TODO release any interrupts, etc. */
1625 /* call hc_release_ohci() here ? */
1626 hc_reset (&gohci);
1627 /* may not want to do this */
1628 clk_power->CLKCON &= ~(1 << 4);
1629 return 0;
1630}
1631
1632#endif /* CONFIG_USB_OHCI */