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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 9d82388d5043d09fe37b7fe48471d3419e404fa8 / . / arch / m68k / include / asm / immap.h
blob: 411b00899c25813e3721ee5adfdef68d21e806c7 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
TsiChungLiew48dbfea2007-07-05 22:39:07 -0500[diff] [blame]2/*
3 * ColdFire Internal Memory Map and Defines
4 *
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame]5 * Copyright 2004-2012 Freescale Semiconductor, Inc.
TsiChungLiew48dbfea2007-07-05 22:39:07 -0500[diff] [blame]6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChungLiew48dbfea2007-07-05 22:39:07 -0500[diff] [blame]7 */
8
9#ifndef __IMMAP_H
10#define __IMMAP_H
Stefan Roesec883f6e2007-07-16 13:11:12 +0200[diff] [blame]11
Tom Rini07011892023-10-12 19:03:56 -0400[diff] [blame]12#include <config.h>
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]13#if defined(CONFIG_MCF520x)
14#include <asm/immap_520x.h>
15#include <asm/m520x.h>
16
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]17#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]18
19/* Timer */
Marek Vasut35d48ea2023-03-23 01:20:39 +0100[diff] [blame]20#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]21#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
22#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
23#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
24#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
25#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
26#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
27#define CFG_SYS_TMRINTR_PRI (6)
28#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Marek Vasut56c3aa92023-03-23 01:20:40 +0100[diff] [blame]29#else
30#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]31#endif
32
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]33#define CFG_SYS_INTR_BASE (MMAP_INTC0)
34#define CFG_SYS_NUM_IRQS (128)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]35#endif /* CONFIG_M520x */
36
TsiChungLiew4a442d32007-08-16 19:23:50 -0500[diff] [blame]37#ifdef CONFIG_M5235
38#include <asm/immap_5235.h>
39#include <asm/m5235.h>
40
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]41#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
TsiChungLiew4a442d32007-08-16 19:23:50 -0500[diff] [blame]42
43/* Timer */
Marek Vasut35d48ea2023-03-23 01:20:39 +0100[diff] [blame]44#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]45#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
46#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
47#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
48#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
49#define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
50#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
51#define CFG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
52#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Marek Vasut56c3aa92023-03-23 01:20:40 +0100[diff] [blame]53#else
54#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
TsiChungLiew4a442d32007-08-16 19:23:50 -0500[diff] [blame]55#endif
56
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]57#define CFG_SYS_INTR_BASE (MMAP_INTC0)
58#define CFG_SYS_NUM_IRQS (128)
TsiChungLiew4a442d32007-08-16 19:23:50 -0500[diff] [blame]59#endif /* CONFIG_M5235 */
60
TsiChungLiew56115662007-08-15 19:38:15 -0500[diff] [blame]61#ifdef CONFIG_M5249
62#include <asm/immap_5249.h>
63#include <asm/m5249.h>
64
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]65#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
TsiChungLiew56115662007-08-15 19:38:15 -0500[diff] [blame]66
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]67#define CFG_SYS_INTR_BASE (MMAP_INTC)
68#define CFG_SYS_NUM_IRQS (64)
TsiChungLiew56115662007-08-15 19:38:15 -0500[diff] [blame]69
70/* Timer */
Marek Vasut35d48ea2023-03-23 01:20:39 +0100[diff] [blame]71#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]72#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
73#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
74#define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
75#define CFG_SYS_TMRINTR_NO (31)
76#define CFG_SYS_TMRINTR_MASK (0x00000400)
77#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
78#define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
79#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
Marek Vasut56c3aa92023-03-23 01:20:40 +0100[diff] [blame]80#else
81#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
TsiChungLiew56115662007-08-15 19:38:15 -0500[diff] [blame]82#endif
83#endif /* CONFIG_M5249 */
84
TsiChungLiewa1436a82007-08-16 13:20:50 -0500[diff] [blame]85#ifdef CONFIG_M5253
86#include <asm/immap_5253.h>
87#include <asm/m5249.h>
88#include <asm/m5253.h>
89
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]90#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
TsiChungLiewa1436a82007-08-16 13:20:50 -0500[diff] [blame]91
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]92#define CFG_SYS_INTR_BASE (MMAP_INTC)
93#define CFG_SYS_NUM_IRQS (64)
TsiChungLiewa1436a82007-08-16 13:20:50 -0500[diff] [blame]94
95/* Timer */
Marek Vasut35d48ea2023-03-23 01:20:39 +0100[diff] [blame]96#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]97#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
98#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
99#define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
100#define CFG_SYS_TMRINTR_NO (27)
101#define CFG_SYS_TMRINTR_MASK (0x00000400)
102#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
103#define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
104#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
Marek Vasut56c3aa92023-03-23 01:20:40 +0100[diff] [blame]105#else
106#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
TsiChungLiewa1436a82007-08-16 13:20:50 -0500[diff] [blame]107#endif
108#endif /* CONFIG_M5253 */
109
TsiChungLiew56115662007-08-15 19:38:15 -0500[diff] [blame]110#ifdef CONFIG_M5271
111#include <asm/immap_5271.h>
112#include <asm/m5271.h>
113
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]114#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
TsiChungLiew56115662007-08-15 19:38:15 -0500[diff] [blame]115
116/* Timer */
Marek Vasut35d48ea2023-03-23 01:20:39 +0100[diff] [blame]117#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]118#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
119#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
120#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
121#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
122#define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
123#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
124#define CFG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */
125#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Marek Vasut56c3aa92023-03-23 01:20:40 +0100[diff] [blame]126#else
127#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
TsiChungLiew56115662007-08-15 19:38:15 -0500[diff] [blame]128#endif
129
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]130#define CFG_SYS_INTR_BASE (MMAP_INTC0)
131#define CFG_SYS_NUM_IRQS (128)
TsiChungLiew56115662007-08-15 19:38:15 -0500[diff] [blame]132#endif /* CONFIG_M5271 */
133
134#ifdef CONFIG_M5272
135#include <asm/immap_5272.h>
136#include <asm/m5272.h>
137
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]138#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
TsiChungLiew56115662007-08-15 19:38:15 -0500[diff] [blame]139
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]140#define CFG_SYS_INTR_BASE (MMAP_INTC)
141#define CFG_SYS_NUM_IRQS (64)
TsiChungLiew56115662007-08-15 19:38:15 -0500[diff] [blame]142
143/* Timer */
Marek Vasut35d48ea2023-03-23 01:20:39 +0100[diff] [blame]144#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]145#define CFG_SYS_UDELAY_BASE (MMAP_TMR0)
146#define CFG_SYS_TMR_BASE (MMAP_TMR3)
147#define CFG_SYS_TMRPND_REG (((volatile intctrl_t *)(CFG_SYS_INTR_BASE))->int_isr)
148#define CFG_SYS_TMRINTR_NO (INT_TMR3)
149#define CFG_SYS_TMRINTR_MASK (INT_ISR_INT24)
150#define CFG_SYS_TMRINTR_PEND (0)
151#define CFG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
152#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Marek Vasut56c3aa92023-03-23 01:20:40 +0100[diff] [blame]153#else
154#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
TsiChungLiew56115662007-08-15 19:38:15 -0500[diff] [blame]155#endif
156#endif /* CONFIG_M5272 */
157
Matthew Fettkef71d9d92008-02-04 15:38:20 -0600[diff] [blame]158#ifdef CONFIG_M5275
159#include <asm/immap_5275.h>
160#include <asm/m5275.h>
161
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]162#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
Matthew Fettkef71d9d92008-02-04 15:38:20 -0600[diff] [blame]163
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]164#define CFG_SYS_INTR_BASE (MMAP_INTC0)
165#define CFG_SYS_NUM_IRQS (192)
Matthew Fettkef71d9d92008-02-04 15:38:20 -0600[diff] [blame]166
167/* Timer */
Marek Vasut35d48ea2023-03-23 01:20:39 +0100[diff] [blame]168#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]169#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
170#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
171#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
172#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
173#define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
174#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
175#define CFG_SYS_TMRINTR_PRI (0x1E)
176#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Marek Vasut56c3aa92023-03-23 01:20:40 +0100[diff] [blame]177#else
178#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
Matthew Fettkef71d9d92008-02-04 15:38:20 -0600[diff] [blame]179#endif
180#endif /* CONFIG_M5275 */
181
TsiChungLiew56115662007-08-15 19:38:15 -0500[diff] [blame]182#ifdef CONFIG_M5282
183#include <asm/immap_5282.h>
184#include <asm/m5282.h>
185
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]186#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
TsiChungLiew56115662007-08-15 19:38:15 -0500[diff] [blame]187
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]188#define CFG_SYS_INTR_BASE (MMAP_INTC0)
189#define CFG_SYS_NUM_IRQS (128)
TsiChungLiew56115662007-08-15 19:38:15 -0500[diff] [blame]190
191/* Timer */
Marek Vasut35d48ea2023-03-23 01:20:39 +0100[diff] [blame]192#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]193#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
194#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
195#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
196#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
197#define CFG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3)
198#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
199#define CFG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
200#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Marek Vasut56c3aa92023-03-23 01:20:40 +0100[diff] [blame]201#else
202#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
TsiChungLiew56115662007-08-15 19:38:15 -0500[diff] [blame]203#endif
204#endif /* CONFIG_M5282 */
205
angelo@sysam.ite77e65d2015-02-12 01:40:00 +0100[diff] [blame]206#ifdef CONFIG_M5307
207#include <asm/immap_5307.h>
208#include <asm/m5307.h>
209
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]210#define CFG_SYS_UART_BASE (MMAP_UART0 + \
Tom Rini65cc0e22022-11-16 13:10:41 -0500[diff] [blame]211 (CFG_SYS_UART_PORT * 0x40))
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]212#define CFG_SYS_INTR_BASE (MMAP_INTC)
213#define CFG_SYS_NUM_IRQS (64)
angelo@sysam.ite77e65d2015-02-12 01:40:00 +0100[diff] [blame]214
215/* Timer */
Marek Vasut35d48ea2023-03-23 01:20:39 +0100[diff] [blame]216#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]217#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
218#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
219#define CFG_SYS_TMRPND_REG (((volatile intctrl_t *) \
220 (CFG_SYS_INTR_BASE))->ipr)
221#define CFG_SYS_TMRINTR_NO (31)
222#define CFG_SYS_TMRINTR_MASK (0x00000400)
223#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
224#define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \
angelo@sysam.ite77e65d2015-02-12 01:40:00 +0100[diff] [blame]225 MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]226#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Marek Vasut56c3aa92023-03-23 01:20:40 +0100[diff] [blame]227#else
228#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
angelo@sysam.ite77e65d2015-02-12 01:40:00 +0100[diff] [blame]229#endif
230#endif /* CONFIG_M5307 */
231
TsiChung Liew536e7da2008-10-22 11:38:21 +0000[diff] [blame]232#if defined(CONFIG_MCF5301x)
233#include <asm/immap_5301x.h>
234#include <asm/m5301x.h>
235
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]236#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
TsiChung Liew536e7da2008-10-22 11:38:21 +0000[diff] [blame]237
TsiChung Liew536e7da2008-10-22 11:38:21 +0000[diff] [blame]238/* Timer */
Marek Vasut35d48ea2023-03-23 01:20:39 +0100[diff] [blame]239#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]240#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
241#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
242#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
243#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
244#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
245#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
246#define CFG_SYS_TMRINTR_PRI (6)
247#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Marek Vasut56c3aa92023-03-23 01:20:40 +0100[diff] [blame]248#else
249#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000[diff] [blame]250#endif
251
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]252#define CFG_SYS_INTR_BASE (MMAP_INTC0)
253#define CFG_SYS_NUM_IRQS (128)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000[diff] [blame]254#endif /* CONFIG_M5301x */
255
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600[diff] [blame]256#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
TsiChungLiew48dbfea2007-07-05 22:39:07 -0500[diff] [blame]257#include <asm/immap_5329.h>
258#include <asm/m5329.h>
259
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]260#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
TsiChungLiew48dbfea2007-07-05 22:39:07 -0500[diff] [blame]261
262/* Timer */
Marek Vasut35d48ea2023-03-23 01:20:39 +0100[diff] [blame]263#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]264#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
265#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
266#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
267#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
268#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
269#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
270#define CFG_SYS_TMRINTR_PRI (6)
271#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Marek Vasut56c3aa92023-03-23 01:20:40 +0100[diff] [blame]272#else
273#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
TsiChungLiew48dbfea2007-07-05 22:39:07 -0500[diff] [blame]274#endif
275
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]276#define CFG_SYS_INTR_BASE (MMAP_INTC0)
277#define CFG_SYS_NUM_IRQS (128)
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600[diff] [blame]278#endif /* CONFIG_M5329 && CONFIG_M5373 */
Stefan Roesec883f6e2007-07-16 13:11:12 +0200[diff] [blame]279
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame]280#if defined(CONFIG_M54418)
281#include <asm/immap_5441x.h>
282#include <asm/m5441x.h>
283
Tom Rini65cc0e22022-11-16 13:10:41 -0500[diff] [blame]284#if (CFG_SYS_UART_PORT < 4)
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]285#define CFG_SYS_UART_BASE (MMAP_UART0 + \
Tom Rini65cc0e22022-11-16 13:10:41 -0500[diff] [blame]286 (CFG_SYS_UART_PORT * 0x4000))
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame]287#else
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]288#define CFG_SYS_UART_BASE (MMAP_UART4 + \
Tom Rini65cc0e22022-11-16 13:10:41 -0500[diff] [blame]289 ((CFG_SYS_UART_PORT - 4) * 0x4000))
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame]290#endif
291
292#define MMAP_DSPI MMAP_DSPI0
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame]293
294/* Timer */
Marek Vasut35d48ea2023-03-23 01:20:39 +0100[diff] [blame]295#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]296#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
297#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
298#define CFG_SYS_TMRPND_REG (((int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
299#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
300#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
301#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
302#define CFG_SYS_TMRINTR_PRI (6)
303#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Marek Vasut56c3aa92023-03-23 01:20:40 +0100[diff] [blame]304#else
305#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame]306#endif
307
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]308#define CFG_SYS_INTR_BASE (MMAP_INTC0)
309#define CFG_SYS_NUM_IRQS (192)
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame]310
311#endif /* CONFIG_M54418 */
312
TsiChungLiew4621fc32008-01-15 13:39:44 -0600[diff] [blame]313#ifdef CONFIG_M547x
314#include <asm/immap_547x_8x.h>
315#include <asm/m547x_8x.h>
316
317#ifdef CONFIG_FSLDMAFEC
TsiChungLiew4621fc32008-01-15 13:39:44 -0600[diff] [blame]318#define FEC0_RX_TASK 0
319#define FEC0_TX_TASK 1
320#define FEC0_RX_PRIORITY 6
321#define FEC0_TX_PRIORITY 7
322#define FEC0_RX_INIT 16
323#define FEC0_TX_INIT 17
324#define FEC1_RX_TASK 2
325#define FEC1_TX_TASK 3
326#define FEC1_RX_PRIORITY 6
327#define FEC1_TX_PRIORITY 7
328#define FEC1_RX_INIT 30
329#define FEC1_TX_INIT 31
330#endif
331
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]332#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100))
TsiChungLiew4621fc32008-01-15 13:39:44 -0600[diff] [blame]333
334#ifdef CONFIG_SLTTMR
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]335#define CFG_SYS_UDELAY_BASE (MMAP_SLT1)
336#define CFG_SYS_TMR_BASE (MMAP_SLT0)
337#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
338#define CFG_SYS_TMRINTR_NO (INT0_HI_SLT0)
339#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
340#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
341#define CFG_SYS_TMRINTR_PRI (0x1E)
342#define CFG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
TsiChungLiew4621fc32008-01-15 13:39:44 -0600[diff] [blame]343#endif
344
Tom Rini6e7df1d2023-01-10 11:19:45 -0500[diff] [blame]345#define CFG_SYS_INTR_BASE (MMAP_INTC0)
346#define CFG_SYS_NUM_IRQS (128)
TsiChungLiew4621fc32008-01-15 13:39:44 -0600[diff] [blame]347
348#ifdef CONFIG_PCI
Tom Riniecc8d422022-11-16 13:10:33 -0500[diff] [blame]349#define CFG_SYS_PCI_BAR0 (0x40000000)
Tom Riniaa6e94d2022-11-16 13:10:37 -0500[diff] [blame]350#define CFG_SYS_PCI_BAR1 (CFG_SYS_SDRAM_BASE)
Tom Rini65cc0e22022-11-16 13:10:41 -0500[diff] [blame]351#define CFG_SYS_PCI_TBATR0 (CFG_SYS_MBAR)
Tom Riniaa6e94d2022-11-16 13:10:37 -0500[diff] [blame]352#define CFG_SYS_PCI_TBATR1 (CFG_SYS_SDRAM_BASE)
TsiChungLiew4621fc32008-01-15 13:39:44 -0600[diff] [blame]353#endif
354#endif /* CONFIG_M547x */
355
TsiChungLiew48dbfea2007-07-05 22:39:07 -0500[diff] [blame]356#endif /* __IMMAP_H */