| Bryan Brattlof | ee31be4 | 2022-10-24 16:53:28 -0500 | [diff] [blame] | 1 | /* SPDX-License-Identifier: BSD-3-Clause */ |
| 2 | /* |
| 3 | * Cadence DDR Driver |
| 4 | * |
| 5 | * Copyright (C) 2012-2022 Cadence Design Systems, Inc. |
| 6 | * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ |
| 7 | */ |
| 8 | |
| 9 | #ifndef LPDDR4_AM6X_H |
| 10 | #define LPDDR4_AM6X_H |
| 11 | |
| 12 | #ifdef CONFIG_K3_AM64_DDRSS |
| 13 | #include "lpddr4_am64_ctl_regs_rw_masks.h" |
| 14 | #elif CONFIG_K3_AM62A_DDRSS |
| 15 | #include "lpddr4_am62a_ctl_regs_rw_masks.h" |
| 16 | #endif |
| 17 | |
| 18 | #ifdef CONFIG_K3_AM64_DDRSS |
| 19 | #define DSLICE_NUM (2U) |
| 20 | #define ASLICE_NUM (2U) |
| 21 | #define DSLICE0_REG_COUNT (126U) |
| 22 | #define DSLICE1_REG_COUNT (126U) |
| 23 | #define ASLICE0_REG_COUNT (42U) |
| 24 | #define ASLICE1_REG_COUNT (42U) |
| 25 | #define ASLICE2_REG_COUNT (42U) |
| 26 | #define PHY_CORE_REG_COUNT (126U) |
| 27 | |
| 28 | #elif CONFIG_K3_AM62A_DDRSS |
| 29 | #define DSLICE_NUM (4U) |
| 30 | #define ASLICE_NUM (3U) |
| 31 | #define DSLICE0_REG_COUNT (136U) |
| 32 | #define DSLICE1_REG_COUNT (136U) |
| 33 | #define DSLICE2_REG_COUNT (136U) |
| 34 | #define DSLICE3_REG_COUNT (136U) |
| 35 | #define ASLICE0_REG_COUNT (48U) |
| 36 | #define ASLICE1_REG_COUNT (48U) |
| 37 | #define ASLICE2_REG_COUNT (48U) |
| 38 | #define PHY_CORE_REG_COUNT (132U) |
| 39 | |
| 40 | #endif |
| 41 | |
| 42 | #define GRP_SHIFT 1 |
| 43 | #define INT_SHIFT 2 |
| 44 | |
| 45 | #endif /* LPDDR4_AM6X_H */ |