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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 9dd41a7b0c5c94d74c25edfdd6393c656669c09a / . / board / ids8247 / ids8247.c
blob: 081ef658e0d92322ec8d359e031b21cc1cba587e [file] [log] [blame]
wdenk9dd41a72005-05-12 22:48:09 +0000[diff] [blame^]1/*
2 * (C) Copyright 2005
3 * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <ioports.h>
26#include <mpc8260.h>
27
28/*
29 * I/O Port configuration table
30 *
31 * if conf is 1, then that port pin will be configured at boot time
32 * according to the five values podr/pdir/ppar/psor/pdat for that entry
33 */
34
35const iop_conf_t iop_conf_tab[4][32] = {
36
37 /* Port A configuration */
38 { /* conf ppar psor pdir podr pdat */
39 /* PA31 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 COL */
40 /* PA30 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
41 /* PA29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
42 /* PA28 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
43 /* PA27 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
44 /* PA26 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
45 /* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */
46#if defined(CONFIG_SOFT_I2C)
47 /* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */
48 /* PA23 */ { 1, 0, 0, 1, 1, 1 }, /* I2C_SCL2 */
49#else /* normal I/O port pins */
50 /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */
51 /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */
52#endif
53 /* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */
54 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
55 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
56 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
57 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
58 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
59 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */
60 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
61 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
62 /* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */
63 /* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */
64 /* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */
65 /* PA10 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DSR */
66 /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
67 /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
68 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
69 /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
70 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
71 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
72 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
73 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
74 /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
75 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
76 },
77
78 /* Port B configuration */
79 { /* conf ppar psor pdir podr pdat */
80 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
81 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
82 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
83 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
84 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
85 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
86 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
87 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
88 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
89 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
90 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
91 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
92 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
93 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
94 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
95 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
96 /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
97 /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
98 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
99 /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
100 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
101 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
102 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
103 /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
104 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
105 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
106 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
107 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
108 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
109 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
110 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
111 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
112 },
113
114 /* Port C */
115 { /* conf ppar psor pdir podr pdat */
116 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
117 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
118 /* PC29 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CLSN */
119 /* PC28 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_OUT */
120 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
121 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
122 /* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */
123 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
124 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
125 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
126 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
127 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
128 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
129 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
130 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
131 /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
132 /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
133 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
134 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
135 /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
136 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
137 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */
138 /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */
139 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
140 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
141 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
142 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
143 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
144 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
145 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
146 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
147 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
148 },
149
150 /* Port D */
151 { /* conf ppar psor pdir podr pdat */
152 /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
153 /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
154 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
155 /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
156 /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
157 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
158 /* PD25 */ { 0, 1, 0, 0, 0, 0 }, /* SCC3_RX */
159 /* PD24 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_TX */
160 /* PD23 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_RTS */
161 /* PD22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC4_RXD */
162 /* PD21 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_TXD */
163 /* PD20 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_RTS */
164 /* PD19 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_SEL */
165 /* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_CLK */
166 /* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MOSI */
167 /* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MISO */
168#if defined(CONFIG_HARD_I2C)
169 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA1 */
170 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL1 */
171#else /* normal I/O port pins */
172 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* PD15 */
173 /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* PD14 */
174#endif
175 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
176 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
177 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
178 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
179 /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
180 /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
181 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* MII_MDIO */
182 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
183 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
184 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
185 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
186 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
187 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
188 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
189 }
190};
191
192/* ------------------------------------------------------------------------- */
193
194/* Check Board Identity:
195 */
196int checkboard (void)
197{
198 puts ("Board: IDS 8247\n");
199 return 0;
200}
201
202/* ------------------------------------------------------------------------- */
203
204/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
205 *
206 * This routine performs standard 8260 initialization sequence
207 * and calculates the available memory size. It may be called
208 * several times to try different SDRAM configurations on both
209 * 60x and local buses.
210 */
211static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
212 ulong orx, volatile uchar * base)
213{
214 volatile uchar c = 0xff;
215 volatile uint *sdmr_ptr;
216 volatile uint *orx_ptr;
217 ulong maxsize, size;
218 int i;
219
220 /* We must be able to test a location outsize the maximum legal size
221 * to find out THAT we are outside; but this address still has to be
222 * mapped by the controller. That means, that the initial mapping has
223 * to be (at least) twice as large as the maximum expected size.
224 */
225 maxsize = (1 + (~orx | 0x7fff)) / 2;
226
227 sdmr_ptr = &memctl->memc_psdmr;
228 orx_ptr = &memctl->memc_or2;
229
230 *orx_ptr = orx;
231
232 /*
233 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
234 *
235 * "At system reset, initialization software must set up the
236 * programmable parameters in the memory controller banks registers
237 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
238 * system software should execute the following initialization sequence
239 * for each SDRAM device.
240 *
241 * 1. Issue a PRECHARGE-ALL-BANKS command
242 * 2. Issue eight CBR REFRESH commands
243 * 3. Issue a MODE-SET command to initialize the mode register
244 *
245 * The initial commands are executed by setting P/LSDMR[OP] and
246 * accessing the SDRAM with a single-byte transaction."
247 *
248 * The appropriate BRx/ORx registers have already been set when we
249 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
250 */
251
252 *sdmr_ptr = sdmr | PSDMR_OP_PREA;
253 *base = c;
254
255 *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
256 for (i = 0; i < 8; i++)
257 *base = c;
258
259 *sdmr_ptr = sdmr | PSDMR_OP_MRW;
260 *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
261
262 *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
263 *base = c;
264
265 size = get_ram_size((long *)base, maxsize);
266 *orx_ptr = orx | ~(size - 1);
267
268 return (size);
269}
270
271long int initdram (int board_type)
272{
273 volatile immap_t *immap = (immap_t *) CFG_IMMR;
274 volatile memctl8260_t *memctl = &immap->im_memctl;
275
276 long psize, lsize;
277
278 psize = 16 * 1024 * 1024;
279 lsize = 0;
280
281 memctl->memc_psrt = CFG_PSRT;
282 memctl->memc_mptpr = CFG_MPTPR;
283
284#ifndef CFG_RAMBOOT
285 /* 60x SDRAM setup:
286 */
287 psize = try_init (memctl, CFG_PSDMR, CFG_OR2,
288 (uchar *) CFG_SDRAM_BASE);
289#endif /* CFG_RAMBOOT */
290
291 icache_enable ();
292
293 return (psize);
294}
295
296int misc_init_r (void)
297{
298 DECLARE_GLOBAL_DATA_PTR;
299
300 gd->bd->bi_flashstart = 0xff800000;
301}
302
303#if (CONFIG_COMMANDS & CFG_CMD_NAND)
304extern ulong
305nand_probe (ulong physadr);
306
307void
308nand_init (void)
309{
310 ulong totlen = 0;
311
312 debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
313 totlen += nand_probe (CFG_NAND0_BASE);
314
315 printf ("%4lu MB\n", totlen >>20);
316}
317
318#endif /* CFG_CMD_NAND */