| Dave Gerlach | d480bd5 | 2021-04-23 11:27:47 -0500 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_K3=y |
| Nishanth Menon | 9dee749 | 2021-05-04 18:00:56 -0500 | [diff] [blame^] | 3 | CONFIG_SPL_GPIO_SUPPORT=y |
| Dave Gerlach | d480bd5 | 2021-04-23 11:27:47 -0500 | [diff] [blame] | 4 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 5 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 6 | CONFIG_SYS_MALLOC_F_LEN=0x80000 |
| 7 | CONFIG_SOC_K3_AM642=y |
| 8 | CONFIG_TARGET_AM642_R5_EVM=y |
| 9 | CONFIG_ENV_SIZE=0x20000 |
| 10 | CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 |
| 11 | CONFIG_SPL_DM_SPI=y |
| 12 | CONFIG_SPL_TEXT_BASE=0x70020000 |
| 13 | CONFIG_SPL_MMC_SUPPORT=y |
| 14 | CONFIG_SPL_SERIAL_SUPPORT=y |
| 15 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
| 16 | CONFIG_SPL_STACK_R_ADDR=0x82000000 |
| 17 | CONFIG_SPL_FS_FAT=y |
| 18 | CONFIG_SPL_LIBDISK_SUPPORT=y |
| 19 | CONFIG_SPL_SPI_FLASH_SUPPORT=y |
| 20 | CONFIG_SPL_SPI_SUPPORT=y |
| 21 | CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-evm" |
| 22 | CONFIG_SPL_LOAD_FIT=y |
| 23 | # CONFIG_DISPLAY_CPUINFO is not set |
| 24 | CONFIG_SPL_SYS_MALLOC_SIMPLE=y |
| 25 | CONFIG_SPL_STACK_R=y |
| 26 | CONFIG_SPL_SEPARATE_BSS=y |
| 27 | CONFIG_SPL_EARLY_BSS=y |
| 28 | CONFIG_SPL_I2C_SUPPORT=y |
| 29 | CONFIG_SPL_DM_MAILBOX=y |
| 30 | CONFIG_SPL_DM_SPI_FLASH=y |
| 31 | CONFIG_SPL_DM_RESET=y |
| Nishanth Menon | 9dee749 | 2021-05-04 18:00:56 -0500 | [diff] [blame^] | 32 | CONFIG_SPL_POWER_SUPPORT=y |
| Dave Gerlach | d480bd5 | 2021-04-23 11:27:47 -0500 | [diff] [blame] | 33 | CONFIG_SPL_POWER_DOMAIN=y |
| 34 | CONFIG_SPL_REMOTEPROC=y |
| 35 | CONFIG_SPL_SPI_LOAD=y |
| 36 | CONFIG_SPL_YMODEM_SUPPORT=y |
| 37 | CONFIG_HUSH_PARSER=y |
| 38 | CONFIG_CMD_ASKENV=y |
| 39 | CONFIG_CMD_MMC=y |
| 40 | CONFIG_CMD_REMOTEPROC=y |
| 41 | # CONFIG_CMD_SETEXPR is not set |
| 42 | CONFIG_CMD_TIME=y |
| 43 | CONFIG_CMD_FAT=y |
| 44 | CONFIG_OF_CONTROL=y |
| 45 | CONFIG_SPL_OF_CONTROL=y |
| 46 | CONFIG_SPL_MULTI_DTB_FIT=y |
| 47 | CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y |
| 48 | CONFIG_ENV_IS_IN_FAT=y |
| 49 | CONFIG_ENV_FAT_DEVICE_AND_PART="1:1" |
| 50 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 51 | CONFIG_DM=y |
| 52 | CONFIG_SPL_DM=y |
| 53 | CONFIG_SPL_DM_SEQ_ALIAS=y |
| 54 | CONFIG_REGMAP=y |
| 55 | CONFIG_SPL_REGMAP=y |
| 56 | CONFIG_SPL_OF_TRANSLATE=y |
| 57 | CONFIG_CLK=y |
| 58 | CONFIG_SPL_CLK=y |
| 59 | CONFIG_CLK_TI_SCI=y |
| 60 | CONFIG_TI_SCI_PROTOCOL=y |
| Nishanth Menon | 9dee749 | 2021-05-04 18:00:56 -0500 | [diff] [blame^] | 61 | CONFIG_DM_GPIO=y |
| 62 | CONFIG_DA8XX_GPIO=y |
| Dave Gerlach | d480bd5 | 2021-04-23 11:27:47 -0500 | [diff] [blame] | 63 | CONFIG_DM_MAILBOX=y |
| 64 | CONFIG_K3_SEC_PROXY=y |
| 65 | CONFIG_DM_MMC=y |
| 66 | CONFIG_MMC_SDHCI=y |
| 67 | CONFIG_MMC_SDHCI_ADMA=y |
| 68 | CONFIG_SPL_MMC_SDHCI_ADMA=y |
| 69 | CONFIG_MMC_SDHCI_AM654=y |
| 70 | CONFIG_DM_SPI_FLASH=y |
| 71 | CONFIG_SF_DEFAULT_MODE=0 |
| 72 | CONFIG_SPI_FLASH_SPANSION=y |
| 73 | CONFIG_SPI_FLASH_STMICRO=y |
| 74 | CONFIG_PINCTRL=y |
| 75 | # CONFIG_PINCTRL_GENERIC is not set |
| 76 | CONFIG_SPL_PINCTRL=y |
| 77 | # CONFIG_SPL_PINCTRL_GENERIC is not set |
| 78 | CONFIG_PINCTRL_SINGLE=y |
| 79 | CONFIG_POWER_DOMAIN=y |
| 80 | CONFIG_TI_SCI_POWER_DOMAIN=y |
| Nishanth Menon | 9dee749 | 2021-05-04 18:00:56 -0500 | [diff] [blame^] | 81 | CONFIG_DM_REGULATOR=y |
| 82 | CONFIG_SPL_DM_REGULATOR=y |
| 83 | CONFIG_DM_REGULATOR_GPIO=y |
| 84 | CONFIG_SPL_DM_REGULATOR_GPIO=y |
| Dave Gerlach | d480bd5 | 2021-04-23 11:27:47 -0500 | [diff] [blame] | 85 | CONFIG_RAM=y |
| 86 | CONFIG_SPL_RAM=y |
| 87 | CONFIG_K3_SYSTEM_CONTROLLER=y |
| 88 | CONFIG_REMOTEPROC_TI_K3_ARM64=y |
| 89 | CONFIG_DM_RESET=y |
| 90 | CONFIG_RESET_TI_SCI=y |
| 91 | CONFIG_SPECIFY_CONSOLE_INDEX=y |
| 92 | CONFIG_DM_SERIAL=y |
| 93 | CONFIG_SPI=y |
| 94 | CONFIG_DM_SPI=y |
| 95 | CONFIG_CADENCE_QSPI=y |
| 96 | CONFIG_TIMER=y |
| 97 | CONFIG_SPL_TIMER=y |
| 98 | CONFIG_OMAP_TIMER=y |
| 99 | CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 |