blob: d007b562936bb184e25301e4edceccf65924009b [file] [log] [blame]
Sukumar Ghoraide941242010-09-18 20:32:33 -07001/*
2 * (C) Copyright 2008
3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
12 * the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <config.h>
26#include <common.h>
Pantelis Antoniou93bfd612014-03-11 19:34:20 +020027#include <malloc.h>
Sukumar Ghoraide941242010-09-18 20:32:33 -070028#include <mmc.h>
29#include <part.h>
30#include <i2c.h>
31#include <twl4030.h>
Balaji T K14fa2dd2011-09-08 06:34:57 +000032#include <twl6030.h>
Nishanth Menoncb199102013-03-26 05:20:54 +000033#include <palmas.h>
Sukumar Ghoraide941242010-09-18 20:32:33 -070034#include <asm/io.h>
35#include <asm/arch/mmc_host_def.h>
Roger Quadros3b689392015-09-19 16:26:53 +053036#if !defined(CONFIG_SOC_KEYSTONE)
37#include <asm/gpio.h>
Dirk Behme96e0e7b2011-05-15 09:04:47 +000038#include <asm/arch/sys_proto.h>
Roger Quadros3b689392015-09-19 16:26:53 +053039#endif
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +053040#include <dm.h>
41
42DECLARE_GLOBAL_DATA_PTR;
Sukumar Ghoraide941242010-09-18 20:32:33 -070043
Pantelis Antoniouab769f22014-02-26 19:28:45 +020044/* simplify defines to OMAP_HSMMC_USE_GPIO */
45#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
46 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
47#define OMAP_HSMMC_USE_GPIO
48#else
49#undef OMAP_HSMMC_USE_GPIO
50#endif
51
Grazvydas Ignotas25c719e2012-03-19 12:12:06 +000052/* common definitions for all OMAPs */
53#define SYSCTL_SRC (1 << 25)
54#define SYSCTL_SRD (1 << 26)
55
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +000056struct omap_hsmmc_data {
57 struct hsmmc *base_addr;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +020058 struct mmc_config cfg;
Pantelis Antoniouab769f22014-02-26 19:28:45 +020059#ifdef OMAP_HSMMC_USE_GPIO
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +053060#ifdef CONFIG_DM_MMC
61 struct gpio_desc cd_gpio; /* Change Detect GPIO */
62 struct gpio_desc wp_gpio; /* Write Protect GPIO */
63 bool cd_inverted;
64#else
Nikita Kiryanove874d5b2012-12-03 02:19:44 +000065 int cd_gpio;
Nikita Kiryanove3913f52012-12-03 02:19:47 +000066 int wp_gpio;
Pantelis Antoniouab769f22014-02-26 19:28:45 +020067#endif
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +053068#endif
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +000069};
70
Nishanth Menoneb9a28f2010-11-19 11:18:12 -050071/* If we fail after 1 second wait, something is really bad */
72#define MAX_RETRY_MS 1000
73
Sricharan933efe62011-11-15 09:49:53 -050074static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
75static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
76 unsigned int siz);
Balaji T K14fa2dd2011-09-08 06:34:57 +000077
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +053078#if defined(OMAP_HSMMC_USE_GPIO) && !defined(CONFIG_DM_MMC)
Nikita Kiryanove874d5b2012-12-03 02:19:44 +000079static int omap_mmc_setup_gpio_in(int gpio, const char *label)
80{
Simon Glass5915a2a2014-10-22 21:37:09 -060081 int ret;
82
83#ifndef CONFIG_DM_GPIO
Nikita Kiryanove874d5b2012-12-03 02:19:44 +000084 if (!gpio_is_valid(gpio))
85 return -1;
Simon Glass5915a2a2014-10-22 21:37:09 -060086#endif
87 ret = gpio_request(gpio, label);
88 if (ret)
89 return ret;
Nikita Kiryanove874d5b2012-12-03 02:19:44 +000090
Simon Glass5915a2a2014-10-22 21:37:09 -060091 ret = gpio_direction_input(gpio);
92 if (ret)
93 return ret;
Nikita Kiryanove874d5b2012-12-03 02:19:44 +000094
95 return gpio;
96}
Nikita Kiryanove874d5b2012-12-03 02:19:44 +000097#endif
98
Paul Kocialkowskifbf1b082016-02-27 19:18:52 +010099#if defined(CONFIG_OMAP44XX)
Balaji T K14fa2dd2011-09-08 06:34:57 +0000100static void omap4_vmmc_pbias_config(struct mmc *mmc)
101{
102 u32 value = 0;
Balaji T K14fa2dd2011-09-08 06:34:57 +0000103
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000104 value = readl((*ctrl)->control_pbiaslite);
Balaji T K14fa2dd2011-09-08 06:34:57 +0000105 value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000106 writel(value, (*ctrl)->control_pbiaslite);
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000107 value = readl((*ctrl)->control_pbiaslite);
Balaji T K14fa2dd2011-09-08 06:34:57 +0000108 value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000109 writel(value, (*ctrl)->control_pbiaslite);
Balaji T K14fa2dd2011-09-08 06:34:57 +0000110}
111#endif
112
Nishanth Menoncb199102013-03-26 05:20:54 +0000113#if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
Balaji T Kdd23e592012-03-12 02:25:49 +0000114static void omap5_pbias_config(struct mmc *mmc)
115{
116 u32 value = 0;
Balaji T Kdd23e592012-03-12 02:25:49 +0000117
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000118 value = readl((*ctrl)->control_pbias);
Balaji T Ka5d439c2013-06-06 05:04:32 +0000119 value &= ~SDCARD_PWRDNZ;
120 writel(value, (*ctrl)->control_pbias);
121 udelay(10); /* wait 10 us */
122 value &= ~SDCARD_BIAS_PWRDNZ;
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000123 writel(value, (*ctrl)->control_pbias);
Balaji T Kdd23e592012-03-12 02:25:49 +0000124
Nishanth Menon384bcae2013-03-26 05:20:56 +0000125 palmas_mmc1_poweron_ldo();
Balaji T Kdd23e592012-03-12 02:25:49 +0000126
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000127 value = readl((*ctrl)->control_pbias);
Balaji T Ka5d439c2013-06-06 05:04:32 +0000128 value |= SDCARD_BIAS_PWRDNZ;
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000129 writel(value, (*ctrl)->control_pbias);
Balaji T Ka5d439c2013-06-06 05:04:32 +0000130 udelay(150); /* wait 150 us */
131 value |= SDCARD_PWRDNZ;
132 writel(value, (*ctrl)->control_pbias);
133 udelay(150); /* wait 150 us */
Balaji T Kdd23e592012-03-12 02:25:49 +0000134}
135#endif
136
Jeroen Hofstee750121c2014-07-12 21:24:08 +0200137static unsigned char mmc_board_init(struct mmc *mmc)
Sukumar Ghoraide941242010-09-18 20:32:33 -0700138{
Sukumar Ghoraide941242010-09-18 20:32:33 -0700139#if defined(CONFIG_OMAP34XX)
140 t2_t *t2_base = (t2_t *)T2_BASE;
141 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
Grazvydas Ignotasb1e725f2012-03-19 03:50:53 +0000142 u32 pbias_lite;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700143
Grazvydas Ignotasb1e725f2012-03-19 03:50:53 +0000144 pbias_lite = readl(&t2_base->pbias_lite);
145 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
Albert ARIBAUD \(3ADEV\)5bfdd1f2015-01-16 09:09:50 +0100146#ifdef CONFIG_TARGET_OMAP3_CAIRO
147 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
148 pbias_lite &= ~PBIASLITEVMODE0;
149#endif
Grazvydas Ignotasb1e725f2012-03-19 03:50:53 +0000150 writel(pbias_lite, &t2_base->pbias_lite);
Paul Kocialkowskiaac54502014-11-08 20:55:47 +0100151
Grazvydas Ignotasb1e725f2012-03-19 03:50:53 +0000152 writel(pbias_lite | PBIASLITEPWRDNZ1 |
Sukumar Ghoraide941242010-09-18 20:32:33 -0700153 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
154 &t2_base->pbias_lite);
155
156 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
157 &t2_base->devconf0);
158
159 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
160 &t2_base->devconf1);
161
Jonathan Solnitbbbc1ae2012-02-24 11:30:18 +0000162 /* Change from default of 52MHz to 26MHz if necessary */
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200163 if (!(mmc->cfg->host_caps & MMC_MODE_HS_52MHz))
Jonathan Solnitbbbc1ae2012-02-24 11:30:18 +0000164 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
165 &t2_base->ctl_prog_io1);
166
Sukumar Ghoraide941242010-09-18 20:32:33 -0700167 writel(readl(&prcm_base->fclken1_core) |
168 EN_MMC1 | EN_MMC2 | EN_MMC3,
169 &prcm_base->fclken1_core);
170
171 writel(readl(&prcm_base->iclken1_core) |
172 EN_MMC1 | EN_MMC2 | EN_MMC3,
173 &prcm_base->iclken1_core);
174#endif
175
Paul Kocialkowskifbf1b082016-02-27 19:18:52 +0100176#if defined(CONFIG_OMAP44XX)
Balaji T K14fa2dd2011-09-08 06:34:57 +0000177 /* PBIAS config needed for MMC1 only */
Simon Glassbcce53d2016-02-29 15:25:51 -0700178 if (mmc->block_dev.devnum == 0)
Balaji T K14fa2dd2011-09-08 06:34:57 +0000179 omap4_vmmc_pbias_config(mmc);
180#endif
Nishanth Menoncb199102013-03-26 05:20:54 +0000181#if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
Simon Glassbcce53d2016-02-29 15:25:51 -0700182 if (mmc->block_dev.devnum == 0)
Balaji T Kdd23e592012-03-12 02:25:49 +0000183 omap5_pbias_config(mmc);
184#endif
Sukumar Ghoraide941242010-09-18 20:32:33 -0700185
186 return 0;
187}
188
Sricharan933efe62011-11-15 09:49:53 -0500189void mmc_init_stream(struct hsmmc *mmc_base)
Sukumar Ghoraide941242010-09-18 20:32:33 -0700190{
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500191 ulong start;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700192
193 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
194
195 writel(MMC_CMD0, &mmc_base->cmd);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500196 start = get_timer(0);
197 while (!(readl(&mmc_base->stat) & CC_MASK)) {
198 if (get_timer(0) - start > MAX_RETRY_MS) {
199 printf("%s: timedout waiting for cc!\n", __func__);
200 return;
201 }
202 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700203 writel(CC_MASK, &mmc_base->stat)
204 ;
205 writel(MMC_CMD0, &mmc_base->cmd)
206 ;
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500207 start = get_timer(0);
208 while (!(readl(&mmc_base->stat) & CC_MASK)) {
209 if (get_timer(0) - start > MAX_RETRY_MS) {
210 printf("%s: timedout waiting for cc2!\n", __func__);
211 return;
212 }
213 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700214 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
215}
216
217
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200218static int omap_hsmmc_init_setup(struct mmc *mmc)
Sukumar Ghoraide941242010-09-18 20:32:33 -0700219{
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +0000220 struct hsmmc *mmc_base;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700221 unsigned int reg_val;
222 unsigned int dsor;
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500223 ulong start;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700224
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +0000225 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
Balaji T K14fa2dd2011-09-08 06:34:57 +0000226 mmc_board_init(mmc);
Sukumar Ghoraide941242010-09-18 20:32:33 -0700227
228 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
229 &mmc_base->sysconfig);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500230 start = get_timer(0);
231 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
232 if (get_timer(0) - start > MAX_RETRY_MS) {
233 printf("%s: timedout waiting for cc2!\n", __func__);
234 return TIMEOUT;
235 }
236 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700237 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500238 start = get_timer(0);
239 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
240 if (get_timer(0) - start > MAX_RETRY_MS) {
241 printf("%s: timedout waiting for softresetall!\n",
242 __func__);
243 return TIMEOUT;
244 }
245 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700246 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
247 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
248 &mmc_base->capa);
249
250 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
251
252 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
253 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
254 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
255
256 dsor = 240;
257 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
258 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
259 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
260 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500261 start = get_timer(0);
262 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
263 if (get_timer(0) - start > MAX_RETRY_MS) {
264 printf("%s: timedout waiting for ics!\n", __func__);
265 return TIMEOUT;
266 }
267 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700268 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
269
270 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
271
272 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
273 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
274 &mmc_base->ie);
275
276 mmc_init_stream(mmc_base);
277
278 return 0;
279}
280
Grazvydas Ignotas25c719e2012-03-19 12:12:06 +0000281/*
282 * MMC controller internal finite state machine reset
283 *
284 * Used to reset command or data internal state machines, using respectively
285 * SRC or SRD bit of SYSCTL register
286 */
287static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
288{
289 ulong start;
290
291 mmc_reg_out(&mmc_base->sysctl, bit, bit);
292
Oleksandr Tyshchenko61a6cc22013-08-06 13:44:16 +0300293 /*
294 * CMD(DAT) lines reset procedures are slightly different
295 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
296 * According to OMAP3 TRM:
297 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
298 * returns to 0x0.
299 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
300 * procedure steps must be as follows:
301 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
302 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
303 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
304 * 3. Wait until the SRC (SRD) bit returns to 0x0
305 * (reset procedure is completed).
306 */
307#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
Nikita Kiryanovdce55b92015-07-30 23:56:20 +0300308 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
Oleksandr Tyshchenko61a6cc22013-08-06 13:44:16 +0300309 if (!(readl(&mmc_base->sysctl) & bit)) {
310 start = get_timer(0);
311 while (!(readl(&mmc_base->sysctl) & bit)) {
312 if (get_timer(0) - start > MAX_RETRY_MS)
313 return;
314 }
315 }
316#endif
Grazvydas Ignotas25c719e2012-03-19 12:12:06 +0000317 start = get_timer(0);
318 while ((readl(&mmc_base->sysctl) & bit) != 0) {
319 if (get_timer(0) - start > MAX_RETRY_MS) {
320 printf("%s: timedout waiting for sysctl %x to clear\n",
321 __func__, bit);
322 return;
323 }
324 }
325}
Sukumar Ghoraide941242010-09-18 20:32:33 -0700326
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200327static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
Sukumar Ghoraide941242010-09-18 20:32:33 -0700328 struct mmc_data *data)
329{
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +0000330 struct hsmmc *mmc_base;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700331 unsigned int flags, mmc_stat;
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500332 ulong start;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700333
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +0000334 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500335 start = get_timer(0);
Tom Rinia7778f82012-01-30 11:22:25 +0000336 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500337 if (get_timer(0) - start > MAX_RETRY_MS) {
Tom Rinia7778f82012-01-30 11:22:25 +0000338 printf("%s: timedout waiting on cmd inhibit to clear\n",
339 __func__);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500340 return TIMEOUT;
341 }
342 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700343 writel(0xFFFFFFFF, &mmc_base->stat);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500344 start = get_timer(0);
345 while (readl(&mmc_base->stat)) {
346 if (get_timer(0) - start > MAX_RETRY_MS) {
Grazvydas Ignotas15ceb1d2012-03-19 12:11:43 +0000347 printf("%s: timedout waiting for STAT (%x) to clear\n",
348 __func__, readl(&mmc_base->stat));
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500349 return TIMEOUT;
350 }
351 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700352 /*
353 * CMDREG
354 * CMDIDX[13:8] : Command index
355 * DATAPRNT[5] : Data Present Select
356 * ENCMDIDX[4] : Command Index Check Enable
357 * ENCMDCRC[3] : Command CRC Check Enable
358 * RSPTYP[1:0]
359 * 00 = No Response
360 * 01 = Length 136
361 * 10 = Length 48
362 * 11 = Length 48 Check busy after response
363 */
364 /* Delay added before checking the status of frq change
365 * retry not supported by mmc.c(core file)
366 */
367 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
368 udelay(50000); /* wait 50 ms */
369
370 if (!(cmd->resp_type & MMC_RSP_PRESENT))
371 flags = 0;
372 else if (cmd->resp_type & MMC_RSP_136)
373 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
374 else if (cmd->resp_type & MMC_RSP_BUSY)
375 flags = RSP_TYPE_LGHT48B;
376 else
377 flags = RSP_TYPE_LGHT48;
378
379 /* enable default flags */
380 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
381 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
382
383 if (cmd->resp_type & MMC_RSP_CRC)
384 flags |= CCCE_CHECK;
385 if (cmd->resp_type & MMC_RSP_OPCODE)
386 flags |= CICE_CHECK;
387
388 if (data) {
389 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
390 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
391 flags |= (MSBS_MULTIBLK | BCE_ENABLE);
392 data->blocksize = 512;
393 writel(data->blocksize | (data->blocks << 16),
394 &mmc_base->blk);
395 } else
396 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
397
398 if (data->flags & MMC_DATA_READ)
399 flags |= (DP_DATA | DDIR_READ);
400 else
401 flags |= (DP_DATA | DDIR_WRITE);
402 }
403
404 writel(cmd->cmdarg, &mmc_base->arg);
Lubomir Popov152ba362013-08-14 18:59:18 +0300405 udelay(20); /* To fix "No status update" error on eMMC */
Sukumar Ghoraide941242010-09-18 20:32:33 -0700406 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
407
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500408 start = get_timer(0);
Sukumar Ghoraide941242010-09-18 20:32:33 -0700409 do {
410 mmc_stat = readl(&mmc_base->stat);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500411 if (get_timer(0) - start > MAX_RETRY_MS) {
412 printf("%s : timeout: No status update\n", __func__);
413 return TIMEOUT;
414 }
415 } while (!mmc_stat);
Sukumar Ghoraide941242010-09-18 20:32:33 -0700416
Grazvydas Ignotas25c719e2012-03-19 12:12:06 +0000417 if ((mmc_stat & IE_CTO) != 0) {
418 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
Sukumar Ghoraide941242010-09-18 20:32:33 -0700419 return TIMEOUT;
Grazvydas Ignotas25c719e2012-03-19 12:12:06 +0000420 } else if ((mmc_stat & ERRI_MASK) != 0)
Sukumar Ghoraide941242010-09-18 20:32:33 -0700421 return -1;
422
423 if (mmc_stat & CC_MASK) {
424 writel(CC_MASK, &mmc_base->stat);
425 if (cmd->resp_type & MMC_RSP_PRESENT) {
426 if (cmd->resp_type & MMC_RSP_136) {
427 /* response type 2 */
428 cmd->response[3] = readl(&mmc_base->rsp10);
429 cmd->response[2] = readl(&mmc_base->rsp32);
430 cmd->response[1] = readl(&mmc_base->rsp54);
431 cmd->response[0] = readl(&mmc_base->rsp76);
432 } else
433 /* response types 1, 1b, 3, 4, 5, 6 */
434 cmd->response[0] = readl(&mmc_base->rsp10);
435 }
436 }
437
438 if (data && (data->flags & MMC_DATA_READ)) {
439 mmc_read_data(mmc_base, data->dest,
440 data->blocksize * data->blocks);
441 } else if (data && (data->flags & MMC_DATA_WRITE)) {
442 mmc_write_data(mmc_base, data->src,
443 data->blocksize * data->blocks);
444 }
445 return 0;
446}
447
Sricharan933efe62011-11-15 09:49:53 -0500448static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
Sukumar Ghoraide941242010-09-18 20:32:33 -0700449{
450 unsigned int *output_buf = (unsigned int *)buf;
451 unsigned int mmc_stat;
452 unsigned int count;
453
454 /*
455 * Start Polled Read
456 */
457 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
458 count /= 4;
459
460 while (size) {
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500461 ulong start = get_timer(0);
Sukumar Ghoraide941242010-09-18 20:32:33 -0700462 do {
463 mmc_stat = readl(&mmc_base->stat);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500464 if (get_timer(0) - start > MAX_RETRY_MS) {
465 printf("%s: timedout waiting for status!\n",
466 __func__);
467 return TIMEOUT;
468 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700469 } while (mmc_stat == 0);
470
Grazvydas Ignotas25c719e2012-03-19 12:12:06 +0000471 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
472 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
473
Sukumar Ghoraide941242010-09-18 20:32:33 -0700474 if ((mmc_stat & ERRI_MASK) != 0)
475 return 1;
476
477 if (mmc_stat & BRR_MASK) {
478 unsigned int k;
479
480 writel(readl(&mmc_base->stat) | BRR_MASK,
481 &mmc_base->stat);
482 for (k = 0; k < count; k++) {
483 *output_buf = readl(&mmc_base->data);
484 output_buf++;
485 }
486 size -= (count*4);
487 }
488
489 if (mmc_stat & BWR_MASK)
490 writel(readl(&mmc_base->stat) | BWR_MASK,
491 &mmc_base->stat);
492
493 if (mmc_stat & TC_MASK) {
494 writel(readl(&mmc_base->stat) | TC_MASK,
495 &mmc_base->stat);
496 break;
497 }
498 }
499 return 0;
500}
501
Sricharan933efe62011-11-15 09:49:53 -0500502static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
503 unsigned int size)
Sukumar Ghoraide941242010-09-18 20:32:33 -0700504{
505 unsigned int *input_buf = (unsigned int *)buf;
506 unsigned int mmc_stat;
507 unsigned int count;
508
509 /*
Lubomir Popov152ba362013-08-14 18:59:18 +0300510 * Start Polled Write
Sukumar Ghoraide941242010-09-18 20:32:33 -0700511 */
512 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
513 count /= 4;
514
515 while (size) {
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500516 ulong start = get_timer(0);
Sukumar Ghoraide941242010-09-18 20:32:33 -0700517 do {
518 mmc_stat = readl(&mmc_base->stat);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500519 if (get_timer(0) - start > MAX_RETRY_MS) {
520 printf("%s: timedout waiting for status!\n",
521 __func__);
522 return TIMEOUT;
523 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700524 } while (mmc_stat == 0);
525
Grazvydas Ignotas25c719e2012-03-19 12:12:06 +0000526 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
527 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
528
Sukumar Ghoraide941242010-09-18 20:32:33 -0700529 if ((mmc_stat & ERRI_MASK) != 0)
530 return 1;
531
532 if (mmc_stat & BWR_MASK) {
533 unsigned int k;
534
535 writel(readl(&mmc_base->stat) | BWR_MASK,
536 &mmc_base->stat);
537 for (k = 0; k < count; k++) {
538 writel(*input_buf, &mmc_base->data);
539 input_buf++;
540 }
541 size -= (count*4);
542 }
543
544 if (mmc_stat & BRR_MASK)
545 writel(readl(&mmc_base->stat) | BRR_MASK,
546 &mmc_base->stat);
547
548 if (mmc_stat & TC_MASK) {
549 writel(readl(&mmc_base->stat) | TC_MASK,
550 &mmc_base->stat);
551 break;
552 }
553 }
554 return 0;
555}
556
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200557static void omap_hsmmc_set_ios(struct mmc *mmc)
Sukumar Ghoraide941242010-09-18 20:32:33 -0700558{
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +0000559 struct hsmmc *mmc_base;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700560 unsigned int dsor = 0;
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500561 ulong start;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700562
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +0000563 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700564 /* configue bus width */
565 switch (mmc->bus_width) {
566 case 8:
567 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
568 &mmc_base->con);
569 break;
570
571 case 4:
572 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
573 &mmc_base->con);
574 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
575 &mmc_base->hctl);
576 break;
577
578 case 1:
579 default:
580 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
581 &mmc_base->con);
582 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
583 &mmc_base->hctl);
584 break;
585 }
586
587 /* configure clock with 96Mhz system clock.
588 */
589 if (mmc->clock != 0) {
590 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
591 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
592 dsor++;
593 }
594
595 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
596 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
597
598 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
599 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
600
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500601 start = get_timer(0);
602 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
603 if (get_timer(0) - start > MAX_RETRY_MS) {
604 printf("%s: timedout waiting for ics!\n", __func__);
605 return;
606 }
607 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700608 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
609}
610
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200611#ifdef OMAP_HSMMC_USE_GPIO
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +0530612#ifdef CONFIG_DM_MMC
613static int omap_hsmmc_getcd(struct mmc *mmc)
614{
615 struct omap_hsmmc_data *priv = mmc->priv;
616 int value;
617
618 value = dm_gpio_get_value(&priv->cd_gpio);
619 /* if no CD return as 1 */
620 if (value < 0)
621 return 1;
622
623 if (priv->cd_inverted)
624 return !value;
625 return value;
626}
627
628static int omap_hsmmc_getwp(struct mmc *mmc)
629{
630 struct omap_hsmmc_data *priv = mmc->priv;
631 int value;
632
633 value = dm_gpio_get_value(&priv->wp_gpio);
634 /* if no WP return as 0 */
635 if (value < 0)
636 return 0;
637 return value;
638}
639#else
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200640static int omap_hsmmc_getcd(struct mmc *mmc)
641{
642 struct omap_hsmmc_data *priv_data = mmc->priv;
643 int cd_gpio;
644
645 /* if no CD return as 1 */
646 cd_gpio = priv_data->cd_gpio;
647 if (cd_gpio < 0)
648 return 1;
649
Igor Grinberg0b03a932014-11-03 11:32:23 +0200650 /* NOTE: assumes card detect signal is active-low */
651 return !gpio_get_value(cd_gpio);
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200652}
653
654static int omap_hsmmc_getwp(struct mmc *mmc)
655{
656 struct omap_hsmmc_data *priv_data = mmc->priv;
657 int wp_gpio;
658
659 /* if no WP return as 0 */
660 wp_gpio = priv_data->wp_gpio;
661 if (wp_gpio < 0)
662 return 0;
663
Igor Grinberg0b03a932014-11-03 11:32:23 +0200664 /* NOTE: assumes write protect signal is active-high */
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200665 return gpio_get_value(wp_gpio);
666}
667#endif
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +0530668#endif
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200669
670static const struct mmc_ops omap_hsmmc_ops = {
671 .send_cmd = omap_hsmmc_send_cmd,
672 .set_ios = omap_hsmmc_set_ios,
673 .init = omap_hsmmc_init_setup,
674#ifdef OMAP_HSMMC_USE_GPIO
675 .getcd = omap_hsmmc_getcd,
676 .getwp = omap_hsmmc_getwp,
677#endif
678};
679
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +0530680#ifndef CONFIG_DM_MMC
Nikita Kiryanove3913f52012-12-03 02:19:47 +0000681int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
682 int wp_gpio)
Sukumar Ghoraide941242010-09-18 20:32:33 -0700683{
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200684 struct mmc *mmc;
685 struct omap_hsmmc_data *priv_data;
686 struct mmc_config *cfg;
687 uint host_caps_val;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700688
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200689 priv_data = malloc(sizeof(*priv_data));
690 if (priv_data == NULL)
691 return -1;
692
Rob Herring5a203972015-03-23 17:56:59 -0500693 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700694
695 switch (dev_index) {
696 case 0:
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +0000697 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700698 break;
Tom Rini1037d582011-10-12 06:20:50 +0000699#ifdef OMAP_HSMMC2_BASE
Sukumar Ghoraide941242010-09-18 20:32:33 -0700700 case 1:
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +0000701 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
Lubomir Popov152ba362013-08-14 18:59:18 +0300702#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
Nikita Kiryanov9fbdca62015-07-30 23:56:21 +0300703 defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) || \
Heiko Schocher3d4f6282016-06-07 08:31:22 +0200704 defined(CONFIG_AM33XX) || \
Roger Quadros3b689392015-09-19 16:26:53 +0530705 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
706 defined(CONFIG_HSMMC2_8BIT)
Lubomir Popov152ba362013-08-14 18:59:18 +0300707 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
708 host_caps_val |= MMC_MODE_8BIT;
709#endif
Sukumar Ghoraide941242010-09-18 20:32:33 -0700710 break;
Tom Rini1037d582011-10-12 06:20:50 +0000711#endif
712#ifdef OMAP_HSMMC3_BASE
Sukumar Ghoraide941242010-09-18 20:32:33 -0700713 case 2:
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +0000714 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
Felipe Balbid11ac4b2014-11-06 08:28:51 -0600715#if (defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && defined(CONFIG_HSMMC3_8BIT)
Lubomir Popov152ba362013-08-14 18:59:18 +0300716 /* Enable 8-bit interface for eMMC on DRA7XX */
717 host_caps_val |= MMC_MODE_8BIT;
718#endif
Sukumar Ghoraide941242010-09-18 20:32:33 -0700719 break;
Tom Rini1037d582011-10-12 06:20:50 +0000720#endif
Sukumar Ghoraide941242010-09-18 20:32:33 -0700721 default:
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +0000722 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700723 return 1;
724 }
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200725#ifdef OMAP_HSMMC_USE_GPIO
726 /* on error gpio values are set to -1, which is what we want */
Nikita Kiryanove874d5b2012-12-03 02:19:44 +0000727 priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
Nikita Kiryanove3913f52012-12-03 02:19:47 +0000728 priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200729#endif
Peter Korsgaard173ddc52013-03-21 04:00:04 +0000730
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200731 cfg = &priv_data->cfg;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700732
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200733 cfg->name = "OMAP SD/MMC";
734 cfg->ops = &omap_hsmmc_ops;
735
736 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
737 cfg->host_caps = host_caps_val & ~host_caps_mask;
738
739 cfg->f_min = 400000;
Jonathan Solnitbbbc1ae2012-02-24 11:30:18 +0000740
741 if (f_max != 0)
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200742 cfg->f_max = f_max;
Jonathan Solnitbbbc1ae2012-02-24 11:30:18 +0000743 else {
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200744 if (cfg->host_caps & MMC_MODE_HS) {
745 if (cfg->host_caps & MMC_MODE_HS_52MHz)
746 cfg->f_max = 52000000;
Jonathan Solnitbbbc1ae2012-02-24 11:30:18 +0000747 else
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200748 cfg->f_max = 26000000;
Jonathan Solnitbbbc1ae2012-02-24 11:30:18 +0000749 } else
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200750 cfg->f_max = 20000000;
Jonathan Solnitbbbc1ae2012-02-24 11:30:18 +0000751 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700752
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200753 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
John Rigby8feafcc2011-04-18 05:50:08 +0000754
John Rigby4ca92442011-04-19 05:48:14 +0000755#if defined(CONFIG_OMAP34XX)
756 /*
757 * Silicon revs 2.1 and older do not support multiblock transfers.
758 */
759 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200760 cfg->b_max = 1;
John Rigby4ca92442011-04-19 05:48:14 +0000761#endif
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200762 mmc = mmc_create(cfg, priv_data);
763 if (mmc == NULL)
764 return -1;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700765
766 return 0;
767}
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +0530768#else
769static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
770{
771 struct omap_hsmmc_data *priv = dev_get_priv(dev);
772 const void *fdt = gd->fdt_blob;
773 int node = dev->of_offset;
774 struct mmc_config *cfg;
775 int val;
776
Mugunthan V N4bc5e192016-04-04 15:22:49 +0530777 priv->base_addr = map_physmem(dev_get_addr(dev), sizeof(struct hsmmc *),
778 MAP_NOCACHE);
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +0530779 cfg = &priv->cfg;
780
781 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
782 val = fdtdec_get_int(fdt, node, "bus-width", -1);
783 if (val < 0) {
784 printf("error: bus-width property missing\n");
785 return -ENOENT;
786 }
787
788 switch (val) {
789 case 0x8:
790 cfg->host_caps |= MMC_MODE_8BIT;
791 case 0x4:
792 cfg->host_caps |= MMC_MODE_4BIT;
793 break;
794 default:
795 printf("error: invalid bus-width property\n");
796 return -ENOENT;
797 }
798
799 cfg->f_min = 400000;
800 cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
801 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
802 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
803
804 priv->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
805
806 return 0;
807}
808
809static int omap_hsmmc_probe(struct udevice *dev)
810{
811 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
812 struct omap_hsmmc_data *priv = dev_get_priv(dev);
813 struct mmc_config *cfg;
814 struct mmc *mmc;
815
816 cfg = &priv->cfg;
817 cfg->name = "OMAP SD/MMC";
818 cfg->ops = &omap_hsmmc_ops;
819
820 mmc = mmc_create(cfg, priv);
821 if (mmc == NULL)
822 return -1;
823
Mugunthan V N5cc6a242016-04-04 17:28:01 +0530824#ifdef OMAP_HSMMC_USE_GPIO
825 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
826 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
827#endif
828
Simon Glasscffe5d82016-05-01 13:52:34 -0600829 mmc->dev = dev;
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +0530830 upriv->mmc = mmc;
831
832 return 0;
833}
834
835static const struct udevice_id omap_hsmmc_ids[] = {
836 { .compatible = "ti,omap3-hsmmc" },
837 { .compatible = "ti,omap4-hsmmc" },
838 { .compatible = "ti,am33xx-hsmmc" },
839 { }
840};
841
842U_BOOT_DRIVER(omap_hsmmc) = {
843 .name = "omap_hsmmc",
844 .id = UCLASS_MMC,
845 .of_match = omap_hsmmc_ids,
846 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
847 .probe = omap_hsmmc_probe,
848 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
849};
850#endif