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Reinhard Arltc2e49f72009-07-25 06:19:12 +02001/*
2 * esd vme8349 U-Boot configuration file
3 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
4 *
Wolfgang Denk2ae18242010-10-06 09:05:45 +02005 * (C) Copyright 2006-2010
Reinhard Arltc2e49f72009-07-25 06:19:12 +02006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
8 * reinhard.arlt@esd-electronics.de
9 * Based on the MPC8349EMDS config.
10 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020011 * SPDX-License-Identifier: GPL-2.0+
Reinhard Arltc2e49f72009-07-25 06:19:12 +020012 */
13
14/*
15 * vme8349 board configuration file.
16 */
17
18#ifndef __CONFIG_H
19#define __CONFIG_H
20
21/*
Reinhard Arlt1dee9be2009-12-08 09:13:08 +010022 * Top level Makefile configuration choices
23 */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020024#ifdef CONFIG_CADDY2
Reinhard Arlt1dee9be2009-12-08 09:13:08 +010025#define VME_CADDY2
26#endif
27
28/*
Reinhard Arltc2e49f72009-07-25 06:19:12 +020029 * High Level Configuration Options
30 */
31#define CONFIG_E300 1 /* E300 Family */
32#define CONFIG_MPC83xx 1 /* MPC83xx family */
33#define CONFIG_MPC834x 1 /* MPC834x family */
34#define CONFIG_MPC8349 1 /* MPC8349 specific */
35#define CONFIG_VME8349 1 /* ESD VME8349 board specific */
36
Wolfgang Denk2ae18242010-10-06 09:05:45 +020037#define CONFIG_SYS_TEXT_BASE 0xFFF00000
38
Reinhard Arlt1dee9be2009-12-08 09:13:08 +010039#define CONFIG_MISC_INIT_R
40
Reinhard Arltc2e49f72009-07-25 06:19:12 +020041#define CONFIG_PCI
42/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
43#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
44
Wolfgang Denk2ae18242010-10-06 09:05:45 +020045#define CONFIG_PCI_66M
46#ifdef CONFIG_PCI_66M
Reinhard Arltc2e49f72009-07-25 06:19:12 +020047#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
48#else
49#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
50#endif
51
52#ifndef CONFIG_SYS_CLK_FREQ
Wolfgang Denk2ae18242010-10-06 09:05:45 +020053#ifdef CONFIG_PCI_66M
Reinhard Arltc2e49f72009-07-25 06:19:12 +020054#define CONFIG_SYS_CLK_FREQ 66000000
55#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
56#else
57#define CONFIG_SYS_CLK_FREQ 33000000
58#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
59#endif
60#endif
61
62#define CONFIG_SYS_IMMR 0xE0000000
63
64#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
65#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
66#define CONFIG_SYS_MEMTEST_END 0x00100000
67
68/*
69 * DDR Setup
70 */
71#define CONFIG_DDR_ECC /* only for ECC DDR module */
72#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
Reinhard Arlt1dee9be2009-12-08 09:13:08 +010073#define CONFIG_SPD_EEPROM
74#define SPD_EEPROM_ADDRESS 0x54
75#define CONFIG_SYS_READ_SPD vme8349_read_spd
Reinhard Arltc2e49f72009-07-25 06:19:12 +020076#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
77
78/*
79 * 32-bit data path mode.
80 *
81 * Please note that using this mode for devices with the real density of 64-bit
82 * effectively reduces the amount of available memory due to the effect of
83 * wrapping around while translating address to row/columns, for example in the
84 * 256MB module the upper 128MB get aliased with contents of the lower
85 * 128MB); normally this define should be used for devices with real 32-bit
86 * data path.
87 */
88#undef CONFIG_DDR_32BIT
89
90#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
91#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
92#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
Joe Hershberger2fef4022011-10-11 23:57:29 -050093#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
94 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
Reinhard Arltc2e49f72009-07-25 06:19:12 +020095#define CONFIG_DDR_2T_TIMING
Joe Hershberger2fef4022011-10-11 23:57:29 -050096#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
97 | DDRCDR_ODT \
98 | DDRCDR_Q_DRN)
99 /* 0x80080001 */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200100
101/*
102 * FLASH on the Local Bus
103 */
104#define CONFIG_SYS_FLASH_CFI
105#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100106#ifdef VME_CADDY2
107#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
108#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200109#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500110 BR_PS_16 | /* 16bit */ \
111 BR_MS_GPCM | /* MSEL = GPCM */ \
112 BR_V) /* valid */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200113
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500114#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
115 | OR_GPCM_XAM \
116 | OR_GPCM_CSNT \
117 | OR_GPCM_ACS_DIV2 \
118 | OR_GPCM_XACS \
119 | OR_GPCM_SCY_15 \
120 | OR_GPCM_TRLX_SET \
121 | OR_GPCM_EHTR_SET \
122 | OR_GPCM_EAD)
123 /* 0xffc06ff7 */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200124#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500125#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB)
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100126#else
127#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
128#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
129#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500130 BR_PS_16 | /* 16bit */ \
131 BR_MS_GPCM | /* MSEL = GPCM */ \
132 BR_V) /* valid */
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100133
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500134#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
135 | OR_GPCM_XAM \
136 | OR_GPCM_CSNT \
137 | OR_GPCM_ACS_DIV2 \
138 | OR_GPCM_XACS \
139 | OR_GPCM_SCY_15 \
140 | OR_GPCM_TRLX_SET \
141 | OR_GPCM_EHTR_SET \
142 | OR_GPCM_EAD)
143 /* 0xf8006ff7 */
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100144#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500145#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100146#endif
147/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200148
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500149#define CONFIG_SYS_WINDOW1_BASE 0xf0000000
150#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \
151 | BR_PS_32 \
152 | BR_MS_GPCM \
153 | BR_V)
154 /* 0xF0001801 */
155#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \
156 | OR_GPCM_SETA)
157 /* 0xfffc0208 */
158#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE
159#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200160
161#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
162#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
163
164#undef CONFIG_SYS_FLASH_CHECKSUM
165#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
166#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
167
Joe Hershbergerc7357a22011-10-11 23:57:27 -0500168#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200169
170#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
171#define CONFIG_SYS_RAMBOOT
172#else
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100173#undef CONFIG_SYS_RAMBOOT
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200174#endif
175
176#define CONFIG_SYS_INIT_RAM_LOCK 1
177#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200178#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200179
Wolfgang Denk553f0982010-10-26 13:32:32 +0200180#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200181 GENERATED_GBL_DATA_SIZE)
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200182#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
183
184#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
Kim Phillipsc8a90642012-06-30 18:29:20 -0500185#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200186
187/*
188 * Local Bus LCRR and LBCR regs
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100189 * LCRR: no DLL bypass, Clock divider is 4
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200190 * External Local Bus rate is
191 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
192 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500193#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200194#define CONFIG_SYS_LBC_LBCR 0x00000000
195
196#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
197
198/*
199 * Serial Port
200 */
201#define CONFIG_CONS_INDEX 1
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200202#define CONFIG_SYS_NS16550
203#define CONFIG_SYS_NS16550_SERIAL
204#define CONFIG_SYS_NS16550_REG_SIZE 1
205#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
206
207#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershbergerc7357a22011-10-11 23:57:27 -0500208 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200209
210#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
211#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
212
213#define CONFIG_CMDLINE_EDITING /* add command line history */
Kim Phillipsa059e902010-04-15 17:36:05 -0500214#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200215/* Use the HUSH parser */
216#define CONFIG_SYS_HUSH_PARSER
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200217
218/* pass open firmware flat tree */
219#define CONFIG_OF_LIBFDT
220#define CONFIG_OF_BOARD_SETUP
221#define CONFIG_OF_STDOUT_VIA_ALIAS
222
223/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200224#define CONFIG_SYS_I2C
225#define CONFIG_SYS_I2C_FSL
226#define CONFIG_SYS_FSL_I2C_SPEED 400000
227#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
228#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
229#define CONFIG_SYS_FSL_I2C2_SPEED 400000
230#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
231#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
232#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Paul Gortmakerefaf6f12009-10-02 18:54:20 -0400233/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200234
235#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
236
237/* TSEC */
238#define CONFIG_SYS_TSEC1_OFFSET 0x24000
239#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
240#define CONFIG_SYS_TSEC2_OFFSET 0x25000
241#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
242
243/*
244 * General PCI
245 * Addresses are mapped 1-1.
246 */
247#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
248#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
249#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
250#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
251#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
252#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
253#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
254#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
255#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
256
257#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
258#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
259#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
260#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
261#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
262#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
263#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
264#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
265#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
266
267#if defined(CONFIG_PCI)
268
269#define PCI_64BIT
270#define PCI_ONE_PCI1
271#if defined(PCI_64BIT)
272#undef PCI_ALL_PCI1
273#undef PCI_TWO_PCI1
274#undef PCI_ONE_PCI1
275#endif
276
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100277#ifndef VME_CADDY2
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100278#endif
279#define CONFIG_PCI_PNP /* do pci plug-and-play */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200280
281#undef CONFIG_EEPRO100
282#undef CONFIG_TULIP
283
284#if !defined(CONFIG_PCI_PNP)
285 #define PCI_ENET0_IOADDR 0xFIXME
286 #define PCI_ENET0_MEMADDR 0xFIXME
287 #define PCI_IDSEL_NUMBER 0xFIXME
288#endif
289
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100290#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
291#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
292
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200293#endif /* CONFIG_PCI */
294
295/*
296 * TSEC configuration
297 */
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100298#ifdef VME_CADDY2
299#define CONFIG_E1000
300#else
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200301#define CONFIG_TSEC_ENET /* TSEC ethernet support */
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100302#endif
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200303
304#if defined(CONFIG_TSEC_ENET)
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200305
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100306#define CONFIG_GMII /* MII PHY management */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200307#define CONFIG_TSEC1
308#define CONFIG_TSEC1_NAME "TSEC0"
309#define CONFIG_TSEC2
310#define CONFIG_TSEC2_NAME "TSEC1"
311#define CONFIG_PHY_M88E1111
312#define TSEC1_PHY_ADDR 0x08
313#define TSEC2_PHY_ADDR 0x10
314#define TSEC1_PHYIDX 0
315#define TSEC2_PHYIDX 0
316#define TSEC1_FLAGS TSEC_GIGABIT
317#define TSEC2_FLAGS TSEC_GIGABIT
318
319/* Options are: TSEC[0-1] */
320#define CONFIG_ETHPRIME "TSEC0"
321
322#endif /* CONFIG_TSEC_ENET */
323
324/*
325 * Environment
326 */
327#ifndef CONFIG_SYS_RAMBOOT
328 #define CONFIG_ENV_IS_IN_FLASH
329 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
330 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
331 #define CONFIG_ENV_SIZE 0x2000
332
333/* Address and size of Redundant Environment Sector */
334#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
335#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
336
337#else
338 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
339 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
340 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
341 #define CONFIG_ENV_SIZE 0x2000
342#endif
343
344#define CONFIG_LOADS_ECHO /* echo on for serial download */
345#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
346
347/*
348 * BOOTP options
349 */
350#define CONFIG_BOOTP_BOOTFILESIZE
351#define CONFIG_BOOTP_BOOTPATH
352#define CONFIG_BOOTP_GATEWAY
353#define CONFIG_BOOTP_HOSTNAME
354
355/*
356 * Command line configuration.
357 */
358#include <config_cmd_default.h>
359
360#define CONFIG_CMD_I2C
361#define CONFIG_CMD_MII
362#define CONFIG_CMD_PING
363#define CONFIG_CMD_DATE
364#define CONFIG_SYS_RTC_BUS_NUM 0x01
365#define CONFIG_SYS_I2C_RTC_ADDR 0x32
366#define CONFIG_RTC_RX8025
367#define CONFIG_CMD_TSI148
368
369#if defined(CONFIG_PCI)
370 #define CONFIG_CMD_PCI
371#endif
372
373#if defined(CONFIG_SYS_RAMBOOT)
374 #undef CONFIG_CMD_ENV
375 #undef CONFIG_CMD_LOADS
376#endif
377
378#define CONFIG_CMD_ELF
379/* Pass Ethernet MAC to VxWorks */
380#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
381
382#undef CONFIG_WATCHDOG /* watchdog disabled */
383
384/*
385 * Miscellaneous configurable options
386 */
387#define CONFIG_SYS_LONGHELP /* undef to save memory */
388#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200389
390#if defined(CONFIG_CMD_KGDB)
391 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
392#else
393 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
394#endif
395
396#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
397#define CONFIG_SYS_MAXARGS 16 /* max num of command args */
398#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200399
400/*
401 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700402 * have to be in the first 256 MB of memory, since this is
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200403 * the maximum mapped by the Linux kernel during initialization.
404 */
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700405#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200406
407#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
408
409#define CONFIG_SYS_HRCW_LOW (\
410 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
411 HRCWL_DDR_TO_SCB_CLK_1X1 |\
412 HRCWL_CSB_TO_CLKIN |\
413 HRCWL_VCO_1X2 |\
414 HRCWL_CORE_TO_CSB_2X1)
415
416#if defined(PCI_64BIT)
417#define CONFIG_SYS_HRCW_HIGH (\
418 HRCWH_PCI_HOST |\
419 HRCWH_64_BIT_PCI |\
420 HRCWH_PCI1_ARBITER_ENABLE |\
421 HRCWH_PCI2_ARBITER_DISABLE |\
422 HRCWH_CORE_ENABLE |\
423 HRCWH_FROM_0X00000100 |\
424 HRCWH_BOOTSEQ_DISABLE |\
425 HRCWH_SW_WATCHDOG_DISABLE |\
426 HRCWH_ROM_LOC_LOCAL_16BIT |\
427 HRCWH_TSEC1M_IN_GMII |\
428 HRCWH_TSEC2M_IN_GMII)
429#else
430#define CONFIG_SYS_HRCW_HIGH (\
431 HRCWH_PCI_HOST |\
432 HRCWH_32_BIT_PCI |\
433 HRCWH_PCI1_ARBITER_ENABLE |\
434 HRCWH_PCI2_ARBITER_ENABLE |\
435 HRCWH_CORE_ENABLE |\
436 HRCWH_FROM_0X00000100 |\
437 HRCWH_BOOTSEQ_DISABLE |\
438 HRCWH_SW_WATCHDOG_DISABLE |\
439 HRCWH_ROM_LOC_LOCAL_16BIT |\
440 HRCWH_TSEC1M_IN_GMII |\
441 HRCWH_TSEC2M_IN_GMII)
442#endif
443
444/* System IO Config */
445#define CONFIG_SYS_SICRH 0
446#define CONFIG_SYS_SICRL SICRL_LDP_A
447
448#define CONFIG_SYS_HID0_INIT 0x000000000
Kim Phillips1a2e2032010-04-20 19:37:54 -0500449#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
450 HID0_ENABLE_INSTRUCTION_CACHE)
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200451
452#define CONFIG_SYS_HID2 HID2_HBE
453
454#define CONFIG_SYS_GPIO1_PRELIM
455#define CONFIG_SYS_GPIO1_DIR 0x00100000
456#define CONFIG_SYS_GPIO1_DAT 0x00100000
457
458#define CONFIG_SYS_GPIO2_PRELIM
459#define CONFIG_SYS_GPIO2_DIR 0x78900000
460#define CONFIG_SYS_GPIO2_DAT 0x70100000
461
462#define CONFIG_HIGH_BATS /* High BATs supported */
463
464/* DDR @ 0x00000000 */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500465#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200466 BATL_MEMCOHERENCE)
467#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
468 BATU_VS | BATU_VP)
469
470/* PCI @ 0x80000000 */
471#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000472#define CONFIG_PCI_INDIRECT_BRIDGE
Joe Hershberger72cd4082011-10-11 23:57:28 -0500473#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200474 BATL_MEMCOHERENCE)
475#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
476 BATU_VS | BATU_VP)
Joe Hershberger72cd4082011-10-11 23:57:28 -0500477#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200478 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
479#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
480 BATU_VS | BATU_VP)
481#else
482#define CONFIG_SYS_IBAT1L (0)
483#define CONFIG_SYS_IBAT1U (0)
484#define CONFIG_SYS_IBAT2L (0)
485#define CONFIG_SYS_IBAT2U (0)
486#endif
487
488#ifdef CONFIG_MPC83XX_PCI2
Joe Hershberger72cd4082011-10-11 23:57:28 -0500489#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200490 BATL_MEMCOHERENCE)
491#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
492 BATU_VS | BATU_VP)
Joe Hershberger72cd4082011-10-11 23:57:28 -0500493#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200494 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
495#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
496 BATU_VS | BATU_VP)
497#else
498#define CONFIG_SYS_IBAT3L (0)
499#define CONFIG_SYS_IBAT3U (0)
500#define CONFIG_SYS_IBAT4L (0)
501#define CONFIG_SYS_IBAT4U (0)
502#endif
503
504/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500505#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200506 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
507#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
508 BATU_VS | BATU_VP)
509
Joe Hershberger72cd4082011-10-11 23:57:28 -0500510#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200511#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
512
513#if (CONFIG_SYS_DDR_SIZE == 512)
514#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500515 BATL_PP_RW | BATL_MEMCOHERENCE)
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200516#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
517 BATU_BL_256M | BATU_VS | BATU_VP)
518#else
519#define CONFIG_SYS_IBAT7L (0)
520#define CONFIG_SYS_IBAT7U (0)
521#endif
522
523#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
524#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
525#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
526#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
527#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
528#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
529#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
530#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
531#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
532#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
533#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
534#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
535#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
536#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
537#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
538#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
539
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200540#if defined(CONFIG_CMD_KGDB)
541#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
542#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
543#endif
544
545/*
546 * Environment Configuration
547 */
548#define CONFIG_ENV_OVERWRITE
549
550#if defined(CONFIG_TSEC_ENET)
551#define CONFIG_HAS_ETH0
552#define CONFIG_HAS_ETH1
553#endif
554
555#define CONFIG_HOSTNAME VME8349
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000556#define CONFIG_ROOTPATH "/tftpboot/rootfs"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000557#define CONFIG_BOOTFILE "uImage"
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200558
Kim Phillips79f516b2009-08-21 16:34:38 -0500559#define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200560
561#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
562#undef CONFIG_BOOTARGS /* boot command will set bootargs */
563
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100564#define CONFIG_BAUDRATE 9600
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200565
566#define CONFIG_EXTRA_ENV_SETTINGS \
567 "netdev=eth0\0" \
568 "hostname=vme8349\0" \
569 "nfsargs=setenv bootargs root=/dev/nfs rw " \
570 "nfsroot=${serverip}:${rootpath}\0" \
571 "ramargs=setenv bootargs root=/dev/ram rw\0" \
572 "addip=setenv bootargs ${bootargs} " \
573 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
574 ":${hostname}:${netdev}:off panic=1\0" \
575 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
576 "flash_nfs=run nfsargs addip addtty;" \
577 "bootm ${kernel_addr}\0" \
578 "flash_self=run ramargs addip addtty;" \
579 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
580 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
581 "bootm\0" \
582 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
583 "update=protect off fff00000 fff3ffff; " \
584 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
585 "upd=run load update\0" \
Kim Phillips79f516b2009-08-21 16:34:38 -0500586 "fdtaddr=780000\0" \
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200587 "fdtfile=vme8349.dtb\0" \
588 ""
589
Joe Hershbergerc7357a22011-10-11 23:57:27 -0500590#define CONFIG_NFSBOOTCOMMAND \
591 "setenv bootargs root=/dev/nfs rw " \
592 "nfsroot=$serverip:$rootpath " \
593 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
594 "$netdev:off " \
595 "console=$consoledev,$baudrate $othbootargs;" \
596 "tftp $loadaddr $bootfile;" \
597 "tftp $fdtaddr $fdtfile;" \
598 "bootm $loadaddr - $fdtaddr"
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200599
600#define CONFIG_RAMBOOTCOMMAND \
Joe Hershbergerc7357a22011-10-11 23:57:27 -0500601 "setenv bootargs root=/dev/ram rw " \
602 "console=$consoledev,$baudrate $othbootargs;" \
603 "tftp $ramdiskaddr $ramdiskfile;" \
604 "tftp $loadaddr $bootfile;" \
605 "tftp $fdtaddr $fdtfile;" \
606 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200607
608#define CONFIG_BOOTCOMMAND "run flash_self"
609
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100610#ifndef __ASSEMBLY__
611int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
612 unsigned char *buffer, int len);
613#endif
614
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200615#endif /* __CONFIG_H */