blob: 2028f4ae286e077003c188d0c10e42c909d8f448 [file] [log] [blame]
Jim Liu52503d82022-05-17 16:28:11 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2021 Nuvoton Technology Corp.
4 */
5
6#include <common.h>
7#include <cpu_func.h>
8#include <dm.h>
9#include <errno.h>
10#include <miiphy.h>
11#include <malloc.h>
12#include <net.h>
13#include <regmap.h>
14#include <serial.h>
15#include <syscon.h>
16#include <asm/io.h>
17#include <linux/err.h>
18#include <linux/iopoll.h>
19
20#define MAC_ADDR_SIZE 6
Tom Rini6e7df1d2023-01-10 11:19:45 -050021#define CFG_TX_DESCR_NUM 32
22#define CFG_RX_DESCR_NUM 32
Jim Liu52503d82022-05-17 16:28:11 +080023
24#define TX_TOTAL_BUFSIZE \
Tom Rini6e7df1d2023-01-10 11:19:45 -050025 ((CFG_TX_DESCR_NUM + 1) * PKTSIZE_ALIGN + PKTALIGN)
Jim Liu52503d82022-05-17 16:28:11 +080026#define RX_TOTAL_BUFSIZE \
Tom Rini6e7df1d2023-01-10 11:19:45 -050027 ((CFG_RX_DESCR_NUM + 1) * PKTSIZE_ALIGN + PKTALIGN)
Jim Liu52503d82022-05-17 16:28:11 +080028
Tom Rini6e7df1d2023-01-10 11:19:45 -050029#define CFG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
Jim Liu52503d82022-05-17 16:28:11 +080030
31struct npcm750_rxbd {
32 unsigned int sl;
33 unsigned int buffer;
34 unsigned int reserved;
35 unsigned int next;
36} __aligned(ARCH_DMA_MINALIGN);
37
38struct npcm750_txbd {
39 unsigned int mode;
40 unsigned int buffer;
41 unsigned int sl;
42 unsigned int next;
43} __aligned(ARCH_DMA_MINALIGN);
44
45struct emc_regs {
46 u32 camcmr; /* 0x00 */
47 u32 camen; /* 0x04 */
48 u32 cam0m; /* 0x08 */
49 u32 cam0l; /* 0x0c */
50 u32 cam1m; /* 0x10 */
51 u32 cam1l; /* 0x14 */
52 u32 cam2m; /* 0x18 */
53 u32 cam2l; /* 0x1c */
54 u32 cam3m; /* 0x20 */
55 u32 cam3l; /* 0x24 */
56 u32 cam4m; /* 0x28 */
57 u32 cam4l; /* 0x2c */
58 u32 cam5m; /* 0x30 */
59 u32 cam5l; /* 0x34 */
60 u32 cam6m; /* 0x38 */
61 u32 cam6l; /* 0x3c */
62 u32 cam7m; /* 0x40 */
63 u32 cam7l; /* 0x44 */
64 u32 cam8m; /* 0x48 */
65 u32 cam8l; /* 0x4c */
66 u32 cam9m; /* 0x50 */
67 u32 cam9l; /* 0x54 */
68 u32 cam10m; /* 0x58 */
69 u32 cam10l; /* 0x5c */
70 u32 cam11m; /* 0x60 */
71 u32 cam11l; /* 0x64 */
72 u32 cam12m; /* 0x68 */
73 u32 cam12l; /* 0x6c */
74 u32 cam13m; /* 0x70 */
75 u32 cam13l; /* 0x74 */
76 u32 cam14m; /* 0x78 */
77 u32 cam14l; /* 0x7c */
78 u32 cam15m; /* 0x80 */
79 u32 cam15l; /* 0x84 */
80 u32 txdlsa; /* 0x88 */
81 u32 rxdlsa; /* 0x8c */
82 u32 mcmdr; /* 0x90 */
83 u32 miid; /* 0x94 */
84 u32 miida; /* 0x98 */
85 u32 fftcr; /* 0x9c */
86 u32 tsdr; /* 0xa0 */
87 u32 rsdr; /* 0xa4 */
88 u32 dmarfc; /* 0xa8 */
89 u32 mien; /* 0xac */
90 u32 mista; /* 0xb0 */
91 u32 mgsta; /* 0xb4 */
92 u32 mpcnt; /* 0xb8 */
93 u32 mrpc; /* 0xbc */
94 u32 mrpcc; /* 0xc0 */
95 u32 mrepc; /* 0xc4 */
96 u32 dmarfs; /* 0xc8 */
97 u32 ctxdsa; /* 0xcc */
98 u32 ctxbsa; /* 0xd0 */
99 u32 crxdsa; /* 0xd4 */
100 u32 crxbsa; /* 0xd8 */
101};
102
103struct npcm750_eth_dev {
Tom Rini6e7df1d2023-01-10 11:19:45 -0500104 struct npcm750_txbd tdesc[CFG_TX_DESCR_NUM] __aligned(ARCH_DMA_MINALIGN);
105 struct npcm750_rxbd rdesc[CFG_RX_DESCR_NUM] __aligned(ARCH_DMA_MINALIGN);
Jim Liu52503d82022-05-17 16:28:11 +0800106 u8 txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
107 u8 rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
108 struct emc_regs *emc_regs_p;
109 struct phy_device *phydev;
110 struct mii_dev *bus;
111 struct npcm750_txbd *curr_txd;
112 struct npcm750_rxbd *curr_rxd;
113 u32 interface;
114 u32 max_speed;
115 u32 idx;
116 struct regmap *gcr_regmap;
117};
118
119struct npcm750_eth_pdata {
120 struct eth_pdata eth_pdata;
121};
122
123/* mac controller bit */
124#define MCMDR_RXON BIT(0)
125#define MCMDR_ACP BIT(3)
126#define MCMDR_SPCRC BIT(5)
127#define MCMDR_TXON BIT(8)
128#define MCMDR_NDEF BIT(9)
129#define MCMDR_FDUP BIT(18)
130#define MCMDR_ENMDC BIT(19)
131#define MCMDR_OPMOD BIT(20)
132#define MCMDR_SWR BIT(24)
133
134/* cam command regiser */
135#define CAMCMR_AUP 0x01
136#define CAMCMR_AMP BIT(1)
137#define CAMCMR_ABP BIT(2)
138#define CAMCMR_CCAM BIT(3)
139#define CAMCMR_ECMP BIT(4)
140#define CAM0EN 0x01
141
142/* mac mii controller bit */
143#define MDCON BIT(19)
144#define PHYAD BIT(8)
145#define PHYWR BIT(16)
146#define PHYBUSY BIT(17)
147#define PHYPRESP BIT(18)
148#define CAM_ENTRY_SIZE 0x08
149
150/* rx and tx status */
151#define TXDS_TXCP BIT(19)
152#define RXDS_CRCE BIT(17)
153#define RXDS_PTLE BIT(19)
154#define RXDS_RXGD BIT(20)
155#define RXDS_ALIE BIT(21)
156#define RXDS_RP BIT(22)
157
158/* mac interrupt status*/
159#define MISTA_RXINTR BIT(0)
160#define MISTA_CRCE BIT(1)
161#define MISTA_RXOV BIT(2)
162#define MISTA_PTLE BIT(3)
163#define MISTA_RXGD BIT(4)
164#define MISTA_ALIE BIT(5)
165#define MISTA_RP BIT(6)
166#define MISTA_MMP BIT(7)
167#define MISTA_DFOI BIT(8)
168#define MISTA_DENI BIT(9)
169#define MISTA_RDU BIT(10)
170#define MISTA_RXBERR BIT(11)
171#define MISTA_CFR BIT(14)
172#define MISTA_TXINTR BIT(16)
173#define MISTA_TXEMP BIT(17)
174#define MISTA_TXCP BIT(18)
175#define MISTA_EXDEF BIT(19)
176#define MISTA_NCS BIT(20)
177#define MISTA_TXABT BIT(21)
178#define MISTA_LC BIT(22)
179#define MISTA_TDU BIT(23)
180#define MISTA_TXBERR BIT(24)
181
182#define ENSTART 0x01
183#define ENRXINTR BIT(0)
184#define ENCRCE BIT(1)
185#define EMRXOV BIT(2)
186#define ENPTLE BIT(3)
187#define ENRXGD BIT(4)
188#define ENALIE BIT(5)
189#define ENRP BIT(6)
190#define ENMMP BIT(7)
191#define ENDFO BIT(8)
192#define ENDENI BIT(9)
193#define ENRDU BIT(10)
194#define ENRXBERR BIT(11)
195#define ENCFR BIT(14)
196#define ENTXINTR BIT(16)
197#define ENTXEMP BIT(17)
198#define ENTXCP BIT(18)
199#define ENTXDEF BIT(19)
200#define ENNCS BIT(20)
201#define ENTXABT BIT(21)
202#define ENLC BIT(22)
203#define ENTDU BIT(23)
204#define ENTXBERR BIT(24)
205
206#define RX_STAT_RBC 0xffff
207#define RX_STAT_RXINTR BIT(16)
208#define RX_STAT_CRCE BIT(17)
209#define RX_STAT_PTLE BIT(19)
210#define RX_STAT_RXGD BIT(20)
211#define RX_STAT_ALIE BIT(21)
212#define RX_STAT_RP BIT(22)
213#define RX_STAT_OWNER (BIT(30) | BIT(31))
214
215#define TX_STAT_TBC 0xffff
216#define TX_STAT_TXINTR BIT(16)
217#define TX_STAT_DEF BIT(17)
218#define TX_STAT_TXCP BIT(19)
219#define TX_STAT_EXDEF BIT(20)
220#define TX_STAT_NCS BIT(21)
221#define TX_STAT_TXBT BIT(22)
222#define TX_STAT_LC BIT(23)
223#define TX_STAT_TXHA BIT(24)
224#define TX_STAT_PAU BIT(25)
225#define TX_STAT_SQE BIT(26)
226
227/* rx and tx owner bit */
228#define RX_OWEN_DMA BIT(31)
229#define RX_OWEN_CPU 0x00 //bit 30 & bit 31
230#define TX_OWEN_DMA BIT(31)
231#define TX_OWEN_CPU (~(BIT(31)))
232
233/* tx frame desc controller bit */
234#define MACTXINTEN 0x04
235#define CRCMODE 0x02
236#define PADDINGMODE 0x01
237
238/* fftcr controller bit */
239#define RXTHD 0x03
240#define TXTHD (BIT(8) | BIT(9))
241#define BLENGTH BIT(21)
242
243/* global setting for driver */
244#define RX_DESC_SIZE 128
245#define TX_DESC_SIZE 64
246#define MAX_RBUFF_SZ 0x600
247#define MAX_TBUFF_SZ 0x600
248#define TX_TIMEOUT 50
249#define DELAY 1000
250#define CAM0 0x0
251#define RX_POLL_SIZE (RX_DESC_SIZE / 2)
252#define MII_TIMEOUT 100
253#define GCR_INTCR 0x3c
254#define INTCR_R1EN BIT(5)
255
256enum MIIDA_MDCCR_T {
257 MIIDA_MDCCR_4 = 0x00,
258 MIIDA_MDCCR_6 = 0x01,
259 MIIDA_MDCCR_8 = 0x02,
260 MIIDA_MDCCR_12 = 0x03,
261 MIIDA_MDCCR_16 = 0x04,
262 MIIDA_MDCCR_20 = 0x05,
263 MIIDA_MDCCR_24 = 0x06,
264 MIIDA_MDCCR_28 = 0x07,
265 MIIDA_MDCCR_30 = 0x08,
266 MIIDA_MDCCR_32 = 0x09,
267 MIIDA_MDCCR_36 = 0x0A,
268 MIIDA_MDCCR_40 = 0x0B,
269 MIIDA_MDCCR_44 = 0x0C,
270 MIIDA_MDCCR_48 = 0x0D,
271 MIIDA_MDCCR_54 = 0x0E,
272 MIIDA_MDCCR_60 = 0x0F,
273};
274
275DECLARE_GLOBAL_DATA_PTR;
276
277static int npcm750_mdio_read(struct mii_dev *bus, int addr, int devad, int regs)
278{
279 struct npcm750_eth_dev *priv = (struct npcm750_eth_dev *)bus->priv;
280 struct emc_regs *reg = priv->emc_regs_p;
281 u32 start, val;
Tom Rini6e7df1d2023-01-10 11:19:45 -0500282 int timeout = CFG_MDIO_TIMEOUT;
Jim Liu52503d82022-05-17 16:28:11 +0800283
284 val = (addr << 0x08) | regs | PHYBUSY | (MIIDA_MDCCR_60 << 20);
285 writel(val, &reg->miida);
286
287 start = get_timer(0);
288 while (get_timer(start) < timeout) {
289 if (!(readl(&reg->miida) & PHYBUSY)) {
290 val = readl(&reg->miid);
291 return val;
292 }
293 udelay(10);
294 };
295 return -ETIMEDOUT;
296}
297
298static int npcm750_mdio_write(struct mii_dev *bus, int addr, int devad, int regs,
299 u16 val)
300{
301 struct npcm750_eth_dev *priv = (struct npcm750_eth_dev *)bus->priv;
302 struct emc_regs *reg = priv->emc_regs_p;
303 ulong start;
Tom Rini6e7df1d2023-01-10 11:19:45 -0500304 int ret = -ETIMEDOUT, timeout = CFG_MDIO_TIMEOUT;
Jim Liu52503d82022-05-17 16:28:11 +0800305
306 writel(val, &reg->miid);
307 writel((addr << 0x08) | regs | PHYBUSY | PHYWR | (MIIDA_MDCCR_60 << 20), &reg->miida);
308
309 start = get_timer(0);
310 while (get_timer(start) < timeout) {
311 if (!(readl(&reg->miida) & PHYBUSY)) {
312 ret = 0;
313 break;
314 }
315 udelay(10);
316 };
317 return ret;
318}
319
320static int npcm750_mdio_reset(struct mii_dev *bus)
321{
322 return 0;
323}
324
325static int npcm750_mdio_init(const char *name, struct npcm750_eth_dev *priv)
326{
327 struct emc_regs *reg = priv->emc_regs_p;
328 struct mii_dev *bus = mdio_alloc();
329
330 if (!bus) {
331 printf("Failed to allocate MDIO bus\n");
332 return -ENOMEM;
333 }
334
335 bus->read = npcm750_mdio_read;
336 bus->write = npcm750_mdio_write;
337 snprintf(bus->name, sizeof(bus->name), "%s", name);
338 bus->reset = npcm750_mdio_reset;
339
340 bus->priv = (void *)priv;
341
342 writel(readl(&reg->mcmdr) | MCMDR_ENMDC, &reg->mcmdr);
343 return mdio_register(bus);
344}
345
346static void npcm750_tx_descs_init(struct npcm750_eth_dev *priv)
347{
348 struct emc_regs *reg = priv->emc_regs_p;
349 struct npcm750_txbd *desc_table_p = &priv->tdesc[0];
350 struct npcm750_txbd *desc_p;
351 u8 *txbuffs = &priv->txbuffs[0];
352 u32 idx;
353
354 writel((u32)desc_table_p, &reg->txdlsa);
355 priv->curr_txd = desc_table_p;
356
Tom Rini6e7df1d2023-01-10 11:19:45 -0500357 for (idx = 0; idx < CFG_TX_DESCR_NUM; idx++) {
Jim Liu52503d82022-05-17 16:28:11 +0800358 desc_p = &desc_table_p[idx];
359 desc_p->buffer = (u32)&txbuffs[idx * PKTSIZE_ALIGN];
360 desc_p->sl = 0;
361 desc_p->mode = 0;
362 desc_p->mode = TX_OWEN_CPU | PADDINGMODE | CRCMODE | MACTXINTEN;
Tom Rini6e7df1d2023-01-10 11:19:45 -0500363 if (idx < (CFG_TX_DESCR_NUM - 1))
Jim Liu52503d82022-05-17 16:28:11 +0800364 desc_p->next = (u32)&desc_table_p[idx + 1];
365 else
366 desc_p->next = (u32)&priv->tdesc[0];
367 }
368 flush_dcache_range((ulong)&desc_table_p[0],
Tom Rini6e7df1d2023-01-10 11:19:45 -0500369 (ulong)&desc_table_p[CFG_TX_DESCR_NUM]);
Jim Liu52503d82022-05-17 16:28:11 +0800370}
371
372static void npcm750_rx_descs_init(struct npcm750_eth_dev *priv)
373{
374 struct emc_regs *reg = priv->emc_regs_p;
375 struct npcm750_rxbd *desc_table_p = &priv->rdesc[0];
376 struct npcm750_rxbd *desc_p;
377 u8 *rxbuffs = &priv->rxbuffs[0];
378 u32 idx;
379
380 flush_dcache_range((ulong)priv->rxbuffs[0],
Tom Rini6e7df1d2023-01-10 11:19:45 -0500381 (ulong)priv->rxbuffs[CFG_RX_DESCR_NUM]);
Jim Liu52503d82022-05-17 16:28:11 +0800382
383 writel((u32)desc_table_p, &reg->rxdlsa);
384 priv->curr_rxd = desc_table_p;
385
Tom Rini6e7df1d2023-01-10 11:19:45 -0500386 for (idx = 0; idx < CFG_RX_DESCR_NUM; idx++) {
Jim Liu52503d82022-05-17 16:28:11 +0800387 desc_p = &desc_table_p[idx];
388 desc_p->sl = RX_OWEN_DMA;
389 desc_p->buffer = (u32)&rxbuffs[idx * PKTSIZE_ALIGN];
Tom Rini6e7df1d2023-01-10 11:19:45 -0500390 if (idx < (CFG_RX_DESCR_NUM - 1))
Jim Liu52503d82022-05-17 16:28:11 +0800391 desc_p->next = (u32)&desc_table_p[idx + 1];
392 else
393 desc_p->next = (u32)&priv->rdesc[0];
394 }
395 flush_dcache_range((ulong)&desc_table_p[0],
Tom Rini6e7df1d2023-01-10 11:19:45 -0500396 (ulong)&desc_table_p[CFG_RX_DESCR_NUM]);
Jim Liu52503d82022-05-17 16:28:11 +0800397}
398
399static void npcm750_set_fifo_threshold(struct npcm750_eth_dev *priv)
400{
401 struct emc_regs *reg = priv->emc_regs_p;
402 unsigned int val;
403
404 val = RXTHD | TXTHD | BLENGTH;
405 writel(val, &reg->fftcr);
406}
407
408static void npcm750_set_global_maccmd(struct npcm750_eth_dev *priv)
409{
410 struct emc_regs *reg = priv->emc_regs_p;
411 unsigned int val;
412
413 val = readl(&reg->mcmdr);
414 val |= MCMDR_SPCRC | MCMDR_ENMDC | MCMDR_ACP | MCMDR_NDEF;
415 writel(val, &reg->mcmdr);
416}
417
418static void npcm750_set_cam(struct npcm750_eth_dev *priv,
419 unsigned int x, unsigned char *pval)
420{
421 struct emc_regs *reg = priv->emc_regs_p;
422 unsigned int msw, lsw;
423
424 msw = (pval[0] << 24) | (pval[1] << 16) | (pval[2] << 8) | pval[3];
425 lsw = (pval[4] << 24) | (pval[5] << 16);
426
427 writel(lsw, &reg->cam0l + x * CAM_ENTRY_SIZE);
428 writel(msw, &reg->cam0m + x * CAM_ENTRY_SIZE);
429 writel(readl(&reg->camen) | CAM0EN, &reg->camen);
430 writel(CAMCMR_ECMP | CAMCMR_ABP | CAMCMR_AUP, &reg->camcmr);
431}
432
433static void npcm750_adjust_link(struct emc_regs *reg,
434 struct phy_device *phydev)
435{
436 u32 val = readl(&reg->mcmdr);
437
438 if (!phydev->link) {
439 printf("%s: No link.\n", phydev->dev->name);
440 return;
441 }
442
443 if (phydev->speed == 100)
444 val |= MCMDR_OPMOD;
445 else
446 val &= ~MCMDR_OPMOD;
447
448 if (phydev->duplex)
449 val |= MCMDR_FDUP;
450 else
451 val &= ~MCMDR_FDUP;
452
453 writel(val, &reg->mcmdr);
454
455 debug("Speed: %d, %s duplex%s\n", phydev->speed,
456 (phydev->duplex) ? "full" : "half",
457 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
458}
459
460static int npcm750_phy_init(struct npcm750_eth_dev *priv, void *dev)
461{
462 struct phy_device *phydev;
463 int ret;
464 u32 address = 0x0;
465
466 phydev = phy_connect(priv->bus, address, dev, priv->interface);
467 if (!phydev)
468 return -ENODEV;
469
470 if (priv->max_speed) {
471 ret = phy_set_supported(phydev, priv->max_speed);
472 if (ret)
473 return ret;
474 }
475 phydev->advertising = phydev->supported;
476
477 priv->phydev = phydev;
478 phy_config(phydev);
479 return 0;
480}
481
482static int npcm750_eth_start(struct udevice *dev)
483{
484 struct eth_pdata *pdata = dev_get_plat(dev);
485 struct npcm750_eth_dev *priv = dev_get_priv(dev);
486 struct emc_regs *reg = priv->emc_regs_p;
487 u8 *enetaddr = pdata->enetaddr;
488 int ret;
489
490 writel(readl(&reg->mcmdr) & ~MCMDR_TXON & ~MCMDR_RXON, &reg->mcmdr);
491
492 writel(readl(&reg->mcmdr) | MCMDR_SWR, &reg->mcmdr);
493 do {
494 ret = readl(&reg->mcmdr);
495 } while (ret & MCMDR_SWR);
496
497 npcm750_rx_descs_init(priv);
498 npcm750_tx_descs_init(priv);
499
500 npcm750_set_cam(priv, priv->idx, enetaddr);
501 npcm750_set_global_maccmd(priv);
502 npcm750_set_fifo_threshold(priv);
503
504 /* Start up the PHY */
505 ret = phy_startup(priv->phydev);
506 if (ret) {
507 printf("Could not initialize PHY\n");
508 return ret;
509 }
510
511 npcm750_adjust_link(reg, priv->phydev);
512 writel(readl(&reg->mcmdr) | MCMDR_TXON | MCMDR_RXON, &reg->mcmdr);
513
514 return 0;
515}
516
517static int npcm750_eth_send(struct udevice *dev, void *packet, int length)
518{
519 struct npcm750_eth_dev *priv = dev_get_priv(dev);
520 struct emc_regs *reg = priv->emc_regs_p;
521 struct npcm750_txbd *desc_p;
522 struct npcm750_txbd *next_desc_p;
523
524 desc_p = priv->curr_txd;
525
526 invalidate_dcache_range((ulong)desc_p, (ulong)(desc_p + 1));
527 /* Check if the descriptor is owned by CPU */
528 if (desc_p->mode & TX_OWEN_DMA) {
529 next_desc_p = (struct npcm750_txbd *)desc_p->next;
530
531 while ((next_desc_p != desc_p) && (next_desc_p->mode & TX_OWEN_DMA))
532 next_desc_p = (struct npcm750_txbd *)next_desc_p->next;
533
534 if (next_desc_p == desc_p) {
535 struct emc_regs *reg = priv->emc_regs_p;
536
537 writel(0, &reg->tsdr);
538 serial_printf("TX: overflow and exit\n");
539 return -EPERM;
540 }
541
542 desc_p = next_desc_p;
543 }
544
545 memcpy((void *)desc_p->buffer, packet, length);
546 flush_dcache_range((ulong)desc_p->buffer,
547 (ulong)desc_p->buffer + roundup(length, ARCH_DMA_MINALIGN));
548 desc_p->sl = 0;
549 desc_p->sl = length & TX_STAT_TBC;
550 desc_p->mode = TX_OWEN_DMA | PADDINGMODE | CRCMODE;
551 flush_dcache_range((ulong)desc_p, (ulong)(desc_p + 1));
552
553 if (!(readl(&reg->mcmdr) & MCMDR_TXON))
554 writel(readl(&reg->mcmdr) | MCMDR_TXON, &reg->mcmdr);
555 priv->curr_txd = (struct npcm750_txbd *)priv->curr_txd->next;
556
557 writel(0, &reg->tsdr);
558 return 0;
559}
560
561static int npcm750_eth_recv(struct udevice *dev, int flags, uchar **packetp)
562{
563 struct npcm750_eth_dev *priv = dev_get_priv(dev);
564 struct npcm750_rxbd *desc_p;
565 struct npcm750_rxbd *next_desc_p;
566 int length = -1;
567
568 desc_p = priv->curr_rxd;
569 invalidate_dcache_range((ulong)desc_p, (ulong)(desc_p + 1));
570
571 if ((desc_p->sl & RX_STAT_OWNER) == RX_OWEN_DMA) {
572 next_desc_p = (struct npcm750_rxbd *)desc_p->next;
573 while ((next_desc_p != desc_p) &&
574 ((next_desc_p->sl & RX_STAT_OWNER) == RX_OWEN_CPU)) {
575 next_desc_p = (struct npcm750_rxbd *)next_desc_p->next;
576 }
577
578 if (next_desc_p == desc_p) {
579 struct emc_regs *reg = priv->emc_regs_p;
580
581 writel(0, &reg->rsdr);
582 serial_printf("RX: overflow and exit\n");
583 return -EPERM;
584 }
585 desc_p = next_desc_p;
586 }
587
588 /* Check if the descriptor is owned by CPU */
589 if ((desc_p->sl & RX_STAT_OWNER) == RX_OWEN_CPU) {
590 if (desc_p->sl & RX_STAT_RXGD) {
591 length = desc_p->sl & RX_STAT_RBC;
592 invalidate_dcache_range((ulong)desc_p->buffer,
593 (ulong)(desc_p->buffer + roundup(length,
594 ARCH_DMA_MINALIGN)));
595 *packetp = (u8 *)(u32)desc_p->buffer;
596 priv->curr_rxd = desc_p;
597 }
598 }
599 return length;
600}
601
602static int npcm750_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
603{
604 struct npcm750_eth_dev *priv = dev_get_priv(dev);
605 struct emc_regs *reg = priv->emc_regs_p;
606 struct npcm750_rxbd *desc_p = priv->curr_rxd;
607
608 /*
609 * Make the current descriptor valid again and go to
610 * the next one
611 */
612 desc_p->sl |= RX_OWEN_DMA;
613 flush_dcache_range((ulong)desc_p, (ulong)(desc_p + 1));
614 priv->curr_rxd = (struct npcm750_rxbd *)priv->curr_rxd->next;
615 writel(0, &reg->rsdr);
616
617 return 0;
618}
619
620static void npcm750_eth_stop(struct udevice *dev)
621{
622 struct npcm750_eth_dev *priv = dev_get_priv(dev);
623 struct emc_regs *reg = priv->emc_regs_p;
624
625 writel(readl(&reg->mcmdr) & ~MCMDR_TXON, &reg->mcmdr);
626 writel(readl(&reg->mcmdr) & ~MCMDR_RXON, &reg->mcmdr);
627 priv->curr_txd = (struct npcm750_txbd *)readl(&reg->txdlsa);
628 priv->curr_rxd = (struct npcm750_rxbd *)readl(&reg->rxdlsa);
629 phy_shutdown(priv->phydev);
630}
631
632static int npcm750_eth_write_hwaddr(struct udevice *dev)
633{
634 struct eth_pdata *pdata = dev_get_plat(dev);
635 struct npcm750_eth_dev *priv = dev_get_priv(dev);
636
637 npcm750_set_cam(priv, CAM0, pdata->enetaddr);
638 return 0;
639}
640
641static int npcm750_eth_bind(struct udevice *dev)
642{
643 return 0;
644}
645
646static int npcm750_eth_probe(struct udevice *dev)
647{
648 struct eth_pdata *pdata = dev_get_plat(dev);
649 struct npcm750_eth_dev *priv = dev_get_priv(dev);
650 u32 iobase = pdata->iobase;
651 int ret;
652
653 memset(priv, 0, sizeof(struct npcm750_eth_dev));
654 ret = dev_read_u32(dev, "id", &priv->idx);
655 if (ret) {
656 printf("failed to get id\n");
657 return -EINVAL;
658 }
659
660 priv->gcr_regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-gcr");
661 if (IS_ERR(priv->gcr_regmap))
662 return -EINVAL;
663
664 priv->emc_regs_p = (struct emc_regs *)iobase;
665 priv->interface = pdata->phy_interface;
666 priv->max_speed = pdata->max_speed;
667
668 if (priv->idx == 0) {
669 /* Enable RMII for EMC1 module */
670 regmap_update_bits(priv->gcr_regmap, GCR_INTCR, INTCR_R1EN, INTCR_R1EN);
671 }
672
673 npcm750_mdio_init(dev->name, priv);
674 priv->bus = miiphy_get_dev_by_name(dev->name);
675
676 ret = npcm750_phy_init(priv, dev);
677
678 return ret;
679}
680
681static int npcm750_eth_remove(struct udevice *dev)
682{
683 struct npcm750_eth_dev *priv = dev_get_priv(dev);
684
685 free(priv->phydev);
686 mdio_unregister(priv->bus);
687 mdio_free(priv->bus);
688
689 return 0;
690}
691
692static const struct eth_ops npcm750_eth_ops = {
693 .start = npcm750_eth_start,
694 .send = npcm750_eth_send,
695 .recv = npcm750_eth_recv,
696 .free_pkt = npcm750_eth_free_pkt,
697 .stop = npcm750_eth_stop,
698 .write_hwaddr = npcm750_eth_write_hwaddr,
699};
700
701static int npcm750_eth_ofdata_to_platdata(struct udevice *dev)
702{
703 struct npcm750_eth_pdata *npcm750_pdata = dev_get_plat(dev);
704 struct eth_pdata *pdata = &npcm750_pdata->eth_pdata;
705 const char *phy_mode;
706 const fdt32_t *cell;
707 int ret = 0;
708
709 pdata->iobase = (phys_addr_t)dev_read_addr_ptr(dev);
710
711 pdata->phy_interface = -1;
712 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", NULL);
Jim Liudd5f07e2022-09-13 14:25:21 +0800713
Jim Liu52503d82022-05-17 16:28:11 +0800714 if (phy_mode)
Jim Liudd5f07e2022-09-13 14:25:21 +0800715 pdata->phy_interface = dev_read_phy_mode(dev);
716
717 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
Jim Liu52503d82022-05-17 16:28:11 +0800718 return -EINVAL;
Jim Liu52503d82022-05-17 16:28:11 +0800719
720 pdata->max_speed = 0;
721 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
722 if (cell)
723 pdata->max_speed = fdt32_to_cpu(*cell);
724
725 return ret;
726}
727
728static const struct udevice_id npcm750_eth_ids[] = {
729 { .compatible = "nuvoton,npcm750-emc" },
730 { }
731};
732
733U_BOOT_DRIVER(eth_npcm750) = {
734 .name = "eth_npcm750",
735 .id = UCLASS_ETH,
736 .of_match = npcm750_eth_ids,
737 .of_to_plat = npcm750_eth_ofdata_to_platdata,
738 .bind = npcm750_eth_bind,
739 .probe = npcm750_eth_probe,
740 .remove = npcm750_eth_remove,
741 .ops = &npcm750_eth_ops,
742 .priv_auto = sizeof(struct npcm750_eth_dev),
743 .plat_auto = sizeof(struct npcm750_eth_pdata),
744 .flags = DM_FLAG_ALLOC_PRIV_DMA,
745};