Tor Krill | 9536dfc | 2008-03-15 15:40:26 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2008 |
| 3 | * Tor Krill, Excito Elektronik i Skåne , tor@excito.com |
| 4 | * |
| 5 | * Modelled after the ds1337 driver |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * Date & Time support (no alarms) for Intersil |
| 25 | * ISL1208 Real Time Clock (RTC). |
| 26 | */ |
| 27 | |
| 28 | #include <common.h> |
| 29 | #include <command.h> |
| 30 | #include <rtc.h> |
| 31 | #include <i2c.h> |
| 32 | |
| 33 | /*---------------------------------------------------------------------*/ |
| 34 | #ifdef DEBUG_RTC |
| 35 | #define DEBUGR(fmt,args...) printf(fmt ,##args) |
| 36 | #else |
| 37 | #define DEBUGR(fmt,args...) |
| 38 | #endif |
| 39 | /*---------------------------------------------------------------------*/ |
| 40 | |
| 41 | /* |
| 42 | * RTC register addresses |
| 43 | */ |
| 44 | |
| 45 | #define RTC_SEC_REG_ADDR 0x0 |
| 46 | #define RTC_MIN_REG_ADDR 0x1 |
| 47 | #define RTC_HR_REG_ADDR 0x2 |
| 48 | #define RTC_DATE_REG_ADDR 0x3 |
| 49 | #define RTC_MON_REG_ADDR 0x4 |
| 50 | #define RTC_YR_REG_ADDR 0x5 |
| 51 | #define RTC_DAY_REG_ADDR 0x6 |
| 52 | #define RTC_STAT_REG_ADDR 0x7 |
| 53 | /* |
| 54 | * RTC control register bits |
| 55 | */ |
| 56 | |
| 57 | /* |
| 58 | * RTC status register bits |
| 59 | */ |
| 60 | #define RTC_STAT_BIT_ARST 0x80 /* AUTO RESET ENABLE BIT */ |
| 61 | #define RTC_STAT_BIT_XTOSCB 0x40 /* CRYSTAL OSCILLATOR ENABLE BIT */ |
| 62 | #define RTC_STAT_BIT_WRTC 0x10 /* WRITE RTC ENABLE BIT */ |
| 63 | #define RTC_STAT_BIT_ALM 0x04 /* ALARM BIT */ |
| 64 | #define RTC_STAT_BIT_BAT 0x02 /* BATTERY BIT */ |
| 65 | #define RTC_STAT_BIT_RTCF 0x01 /* REAL TIME CLOCK FAIL BIT */ |
| 66 | |
| 67 | static uchar rtc_read (uchar reg); |
| 68 | static void rtc_write (uchar reg, uchar val); |
| 69 | static uchar bin2bcd (unsigned int n); |
| 70 | static unsigned bcd2bin (uchar c); |
| 71 | |
| 72 | /* |
| 73 | * Get the current time from the RTC |
| 74 | */ |
| 75 | |
Yuri Tikhonov | b73a19e | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 76 | int rtc_get (struct rtc_time *tmp) |
Tor Krill | 9536dfc | 2008-03-15 15:40:26 +0100 | [diff] [blame] | 77 | { |
Yuri Tikhonov | b73a19e | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 78 | int rel = 0; |
Tor Krill | 9536dfc | 2008-03-15 15:40:26 +0100 | [diff] [blame] | 79 | uchar sec, min, hour, mday, wday, mon, year, status; |
| 80 | |
| 81 | status = rtc_read (RTC_STAT_REG_ADDR); |
| 82 | sec = rtc_read (RTC_SEC_REG_ADDR); |
| 83 | min = rtc_read (RTC_MIN_REG_ADDR); |
| 84 | hour = rtc_read (RTC_HR_REG_ADDR); |
| 85 | wday = rtc_read (RTC_DAY_REG_ADDR); |
| 86 | mday = rtc_read (RTC_DATE_REG_ADDR); |
| 87 | mon = rtc_read (RTC_MON_REG_ADDR); |
| 88 | year = rtc_read (RTC_YR_REG_ADDR); |
| 89 | |
| 90 | DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x " |
| 91 | "hr: %02x min: %02x sec: %02x status: %02x\n", |
| 92 | year, mon, mday, wday, hour, min, sec, status); |
| 93 | |
| 94 | if (status & RTC_STAT_BIT_RTCF) { |
| 95 | printf ("### Warning: RTC oscillator has stopped\n"); |
| 96 | rtc_write(RTC_STAT_REG_ADDR, |
| 97 | rtc_read(RTC_STAT_REG_ADDR) &~ (RTC_STAT_BIT_BAT|RTC_STAT_BIT_RTCF)); |
Yuri Tikhonov | b73a19e | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 98 | rel = -1; |
Tor Krill | 9536dfc | 2008-03-15 15:40:26 +0100 | [diff] [blame] | 99 | } |
| 100 | |
| 101 | tmp->tm_sec = bcd2bin (sec & 0x7F); |
| 102 | tmp->tm_min = bcd2bin (min & 0x7F); |
| 103 | tmp->tm_hour = bcd2bin (hour & 0x3F); |
| 104 | tmp->tm_mday = bcd2bin (mday & 0x3F); |
| 105 | tmp->tm_mon = bcd2bin (mon & 0x1F); |
| 106 | tmp->tm_year = bcd2bin (year)+2000; |
| 107 | tmp->tm_wday = bcd2bin (wday & 0x07); |
| 108 | tmp->tm_yday = 0; |
| 109 | tmp->tm_isdst= 0; |
| 110 | |
| 111 | DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
| 112 | tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, |
| 113 | tmp->tm_hour, tmp->tm_min, tmp->tm_sec); |
Yuri Tikhonov | b73a19e | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 114 | |
| 115 | return rel; |
Tor Krill | 9536dfc | 2008-03-15 15:40:26 +0100 | [diff] [blame] | 116 | } |
| 117 | |
| 118 | /* |
| 119 | * Set the RTC |
| 120 | */ |
Jean-Christophe PLAGNIOL-VILLARD | d1e2319 | 2008-09-01 23:06:23 +0200 | [diff] [blame] | 121 | int rtc_set (struct rtc_time *tmp) |
Tor Krill | 9536dfc | 2008-03-15 15:40:26 +0100 | [diff] [blame] | 122 | { |
| 123 | DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
| 124 | tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, |
| 125 | tmp->tm_hour, tmp->tm_min, tmp->tm_sec); |
| 126 | |
| 127 | /* enable write */ |
| 128 | rtc_write(RTC_STAT_REG_ADDR, |
| 129 | rtc_read(RTC_STAT_REG_ADDR) | RTC_STAT_BIT_WRTC); |
| 130 | |
| 131 | rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); |
| 132 | rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon)); |
| 133 | rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday)); |
| 134 | rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); |
| 135 | rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour) | 0x80 ); /* 24h clock */ |
| 136 | rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); |
| 137 | rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); |
| 138 | |
| 139 | /* disable write */ |
| 140 | rtc_write(RTC_STAT_REG_ADDR, |
| 141 | rtc_read(RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_WRTC); |
Jean-Christophe PLAGNIOL-VILLARD | d1e2319 | 2008-09-01 23:06:23 +0200 | [diff] [blame] | 142 | |
| 143 | return 0; |
Tor Krill | 9536dfc | 2008-03-15 15:40:26 +0100 | [diff] [blame] | 144 | } |
| 145 | |
| 146 | void rtc_reset (void) |
| 147 | { |
| 148 | } |
| 149 | |
| 150 | /* |
| 151 | * Helper functions |
| 152 | */ |
| 153 | |
| 154 | static uchar rtc_read (uchar reg) |
| 155 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 156 | return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); |
Tor Krill | 9536dfc | 2008-03-15 15:40:26 +0100 | [diff] [blame] | 157 | } |
| 158 | |
| 159 | static void rtc_write (uchar reg, uchar val) |
| 160 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 161 | i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); |
Tor Krill | 9536dfc | 2008-03-15 15:40:26 +0100 | [diff] [blame] | 162 | } |
| 163 | |
| 164 | static unsigned bcd2bin (uchar n) |
| 165 | { |
| 166 | return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); |
| 167 | } |
| 168 | |
| 169 | static unsigned char bin2bcd (unsigned int n) |
| 170 | { |
| 171 | return (((n / 10) << 4) | (n % 10)); |
| 172 | } |