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Jason Liu23608e22011-11-25 00:18:02 +00001/*
2 * Based on the iomux-v3.c from Linux kernel:
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
5 * <armlinux@phytec.de>
6 *
7 * Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Jason Liu23608e22011-11-25 00:18:02 +000010 */
11#include <common.h>
12#include <asm/io.h>
13#include <asm/arch/imx-regs.h>
Troy Kiskyaf2a35f2012-07-19 08:18:22 +000014#include <asm/imx-common/iomux-v3.h>
Peng Fancf226d92015-09-23 11:13:28 +080015#include <asm/imx-common/sys_proto.h>
Jason Liu23608e22011-11-25 00:18:02 +000016
17static void *base = (void *)IOMUXC_BASE_ADDR;
18
19/*
20 * configures a single pad in the iomuxer
21 */
Stefan Roese59efa052013-04-10 23:06:46 +000022void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
Jason Liu23608e22011-11-25 00:18:02 +000023{
24 u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
25 u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
26 u32 sel_input_ofs =
27 (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
28 u32 sel_input =
29 (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
30 u32 pad_ctrl_ofs =
31 (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
32 u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
33
Fabio Estevam98d2cff2014-04-29 10:15:46 -030034#if defined CONFIG_MX6SL
35 /* Check whether LVE bit needs to be set */
36 if (pad_ctrl & PAD_CTL_LVE) {
37 pad_ctrl &= ~PAD_CTL_LVE;
38 pad_ctrl |= PAD_CTL_LVE_BIT;
39 }
40#endif
41
Adrian Alonso03f0e4c2015-08-11 11:19:50 -050042#ifdef CONFIG_IOMUX_LPSR
43 u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT;
44
45 if (lpsr == IOMUX_CONFIG_LPSR) {
46 base = (void *)IOMUXC_LPSR_BASE_ADDR;
47 mux_mode &= ~IOMUX_CONFIG_LPSR;
48 /* set daisy chain sel_input */
49 if (sel_input_ofs)
50 sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
51 }
52#endif
53
Peng Fancf226d92015-09-23 11:13:28 +080054 if (is_soc_type(MXC_SOC_MX7) || mux_ctrl_ofs)
55 __raw_writel(mux_mode, base + mux_ctrl_ofs);
Jason Liu23608e22011-11-25 00:18:02 +000056
57 if (sel_input_ofs)
58 __raw_writel(sel_input, base + sel_input_ofs);
59
Alison Wangcfd701b2013-05-27 22:55:41 +000060#ifdef CONFIG_IOMUX_SHARE_CONF_REG
61 if (!(pad_ctrl & NO_PAD_CTRL))
62 __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl,
63 base + pad_ctrl_ofs);
64#else
Jason Liu23608e22011-11-25 00:18:02 +000065 if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
66 __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
Alison Wangcfd701b2013-05-27 22:55:41 +000067#endif
Adrian Alonso03f0e4c2015-08-11 11:19:50 -050068
69#ifdef CONFIG_IOMUX_LPSR
70 if (lpsr == IOMUX_CONFIG_LPSR)
71 base = (void *)IOMUXC_BASE_ADDR;
72#endif
73
Jason Liu23608e22011-11-25 00:18:02 +000074}
75
Tim Harvey5bf497e2014-06-02 16:13:24 -070076/* configures a list of pads within declared with IOMUX_PADS macro */
Stefan Roese59efa052013-04-10 23:06:46 +000077void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
78 unsigned count)
Jason Liu23608e22011-11-25 00:18:02 +000079{
Eric Nelson5ae28d22012-10-03 07:26:37 +000080 iomux_v3_cfg_t const *p = pad_list;
Tim Harvey5bf497e2014-06-02 16:13:24 -070081 int stride;
Jason Liu23608e22011-11-25 00:18:02 +000082 int i;
Jason Liu23608e22011-11-25 00:18:02 +000083
Tim Harvey5bf497e2014-06-02 16:13:24 -070084#if defined(CONFIG_MX6QDL)
85 stride = 2;
86 if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
87 p += 1;
88#else
89 stride = 1;
90#endif
91 for (i = 0; i < count; i++) {
92 imx_iomux_v3_setup_pad(*p);
93 p += stride;
94 }
Jason Liu23608e22011-11-25 00:18:02 +000095}
Ye.Li8fe280f2014-10-30 18:53:49 +080096
97void imx_iomux_set_gpr_register(int group, int start_bit,
98 int num_bits, int value)
99{
100 int i = 0;
101 u32 reg;
102 reg = readl(base + group * 4);
103 while (num_bits) {
104 reg &= ~(1<<(start_bit + i));
105 i++;
106 num_bits--;
107 }
108 reg |= (value << start_bit);
109 writel(reg, base + group * 4);
110}
Bhuvanchandra DVd348a942015-06-01 18:37:16 +0530111
112#ifdef CONFIG_IOMUX_SHARE_CONF_REG
113void imx_iomux_gpio_set_direction(unsigned int gpio,
114 unsigned int direction)
115{
116 u32 reg;
117 /*
118 * Only on Vybrid the input/output buffer enable flags
119 * are part of the shared mux/conf register.
120 */
121 reg = readl(base + (gpio << 2));
122
123 if (direction)
124 reg |= 0x2;
125 else
126 reg &= ~0x2;
127
128 writel(reg, base + (gpio << 2));
129}
130
131void imx_iomux_gpio_get_function(unsigned int gpio, u32 *gpio_state)
132{
133 *gpio_state = readl(base + (gpio << 2)) &
134 ((0X07 << PAD_MUX_MODE_SHIFT) | PAD_CTL_OBE_IBE_ENABLE);
135}
136#endif