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wdenk2262cfe2002-11-18 00:14:45 +00001/*
2 * (C) Copyright 2002
3 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* i8259.h i8259 PIC Registers */
25
26#ifndef _ASMI386_I8259_H_
27#define _ASMI386_I8959_H_ 1
28
29
30/* PIC I/O mapped registers */
31
32#define IRR 0x0 /* Interrupt Request Register */
33#define ISR 0x0 /* In-Service Register */
34#define ICW1 0x0 /* Initialization Control Word 1 */
35#define OCW2 0x0 /* Operation Control Word 2 */
36#define OCW3 0x0 /* Operation Control Word 3 */
37#define ICW2 0x1 /* Initialization Control Word 2 */
38#define ICW3 0x1 /* Initialization Control Word 3 */
39#define ICW4 0x1 /* Initialization Control Word 4 */
40#define IMR 0x1 /* Interrupt Mask Register */
41
42/* bits for IRR, IMR, ISR and ICW3 */
43#define IR7 0x80 /* IR7 */
44#define IR6 0x40 /* IR6 */
45#define IR5 0x20 /* IR5 */
46#define IR4 0x10 /* IR4 */
47#define IR3 0x08 /* IR3 */
48#define IR2 0x04 /* IR2 */
49#define IR1 0x02 /* IR1 */
50#define IR0 0x01 /* IR0 */
51
52/* bits for SEOI */
53#define SEOI_IR7 0x07 /* IR7 */
54#define SEOI_IR6 0x06 /* IR6 */
55#define SEOI_IR5 0x05 /* IR5 */
56#define SEOI_IR4 0x04 /* IR4 */
57#define SEOI_IR3 0x03 /* IR3 */
58#define SEOI_IR2 0x02 /* IR2 */
59#define SEOI_IR1 0x01 /* IR1 */
60#define SEOI_IR0 0x00 /* IR0 */
61
62/* OCW2 bits */
63#define OCW2_RCLR 0x00 /* Rotate/clear */
64#define OCW2_NEOI 0x20 /* Non specific EOI */
65#define OCW2_NOP 0x40 /* NOP */
66#define OCW2_SEOI 0x60 /* Specific EOI */
67#define OCW2_RSET 0x80 /* Rotate/set */
68#define OCW2_REOI 0xA0 /* Rotate on non specific EOI */
69#define OCW2_PSET 0xC0 /* Priority Set Command */
70#define OCW2_RSEOI 0xE0 /* Rotate on specific EOI */
71
72/* ICW1 bits */
73#define ICW1_SEL 0x10 /* Select ICW1 */
74#define ICW1_LTIM 0x08 /* Level-Triggered Interrupt Mode */
75#define ICW1_ADI 0x04 /* Address Interval */
76#define ICW1_SNGL 0x02 /* Single PIC */
77#define ICW1_EICW4 0x01 /* Expect initilization ICW4 */
78
79/* ICW2 is the starting vector number */
80
wdenk8bde7f72003-06-27 21:31:46 +000081/* ICW2 is bit-mask of present slaves for a master device,
wdenk2262cfe2002-11-18 00:14:45 +000082 * or the slave ID for a slave device */
83
84/* ICW4 bits */
85#define ICW4_AEOI 0x02 /* Automatic EOI Mode */
86#define ICW4_PM 0x01 /* Microprocessor Mode */
87
88#endif