blob: e139c6d1295fff6057c9727cebd7df1e8975cd43 [file] [log] [blame]
Stefan Roese537223a2007-08-06 21:10:17 +02001The 2 important dipswitches are configured as shown below:
2
3SW1 (for 33MHz SysClk)
4----------------------
5S1 S2 S3 S4 S5 S6 S7 S8
6OFF OFF OFF OFF OFF OFF OFF ON
7
8SW7 (for Op-Code Flash and Boot Option H)
9-----------------------------------------
10S1 S2 S3 S4 S5 S6 S7 S8
11OFF OFF OFF ON OFF OFF OFF OFF
12
13The EEPROM at location 0x52 is loaded with these 16 bytes:
14C47042A6 05D7A190 40082350 0d050000
15
16SDR0_SDSTP0[ENG]: 1 : PLL's VCO is the source for PLL forward divisors
17SDR0_SDSTP0[SRC]: 1 : Feedback originates from PLLOUTB
18SDR0_SDSTP0[SEL]: 0 : Feedback selection is PLL output
19SDR0_SDSTP0[TUNE]: 1000111000 : 10 <= M <= 22, 600MHz < VCO <= 900MHz
20SDR0_SDSTP0[FBDV]: 4 : PLL feedback divisor
21SDR0_SDSTP0[FBDVA]: 2 : PLL forward divisor A
22SDR0_SDSTP0[FBDVB]: 5 : PLL forward divisor B
23SDR0_SDSTP0[PRBDV0]: 1 : PLL primary divisor B
24SDR0_SDSTP0[OPBDV0]: 2 : OPB clock divisor
25SDR0_SDSTP0[LFBDV]: 1 : PLL local feedback divisor
26SDR0_SDSTP0[PERDV0]: 3 : Peripheral clock divisor 0
27SDR0_SDSTP0[MALDV0]: 2 : MAL clock divisor 0
28SDR0_SDSTP0[PCIDV0]: 2 : Sync PCI clock divisor 0
29SDR0_SDSTP0[PLLTIMER]: 7 : PLL locking timer
30SDR0_SDSTP0[RW]: 1 : EBC ROM width: 16-bit
31SDR0_SDSTP0[RL]: 0 : EBC ROM location: EBC
32SDR0_SDSTP0[PAE]: 0 : PCI internal arbiter: disabled
33SDR0_SDSTP0[PHCE]: 0 : PCI host configuration: disabled
34SDR0_SDSTP0[ZM]: 3 : ZMII mode: RMII mode 100
35SDR0_SDSTP0[CTE]: 0 : CPU trace: disabled
36SDR0_SDSTP0[Nto1]: 0 : CPU/PLB ratio N/P: not N to 1
37SDR0_SDSTP0[PAME]: 1 : PCI asynchronous mode: enabled
38SDR0_SDSTP0[MEM]: 1 : Multiplex: EMAC
39SDR0_SDSTP0[NE]: 0 : NDFC: disabled
40SDR0_SDSTP0[NBW]: 0 : NDFC boot width: 8-bit
41SDR0_SDSTP0[NBW]: 0 : NDFC boot page selection
42SDR0_SDSTP0[NBAC]: 0 : NDFC boot address selection cycle: 3 Addr. Cycles, 1 Col. + 2 Row (512 page size)
43SDR0_SDSTP0[NARE]: 0 : NDFC auto read : disabled
44SDR0_SDSTP0[NRB]: 0 : NDFC Ready/Busy : Ready
45SDR0_SDSTP0[NDRSC]: 33333 : NDFC device reset counter
46SDR0_SDSTP0[NCG0]: 0 : NDFC/EBC chip select gating CS0 : EBC
47SDR0_SDSTP0[NCG1]: 0 : NDFC/EBC chip select gating CS1 : EBC
48SDR0_SDSTP0[NCG2]: 0 : NDFC/EBC chip select gating CS2 : EBC
49SDR0_SDSTP0[NCG3]: 0 : NDFC/EBC chip select gating CS3 : EBC
50SDR0_SDSTP0[NCRDC]: 3333 : NDFC device read count
51
52PPC440EP Clocking Configuration
53
54SysClk is 33.0MHz, M is 20, VCO is 660.0MHz, CPU is 330.0MHz, PLB is 132.0MHz
55OPB is 66.0MHz, EBC is 44.0MHz, MAL is 66.0MHz, Sync PCI is 66.0MHz
56
57The above information is reported by Eugene O'Brien
58<Eugene.O'Brien@advantechamt.com>. Thanks a lot.
59
602007-08-06, Stefan Roese <sr@denx.de>
61---------------------------------------------------------------------
62
Stefan Roese193dd952006-07-27 16:14:05 +020063The configuration for the AMCC 440EP eval board "Bamboo" was changed
64to only use 384 kbytes of FLASH for the U-Boot image. This way the
65redundant environment can be saved in the remaining 2 sectors of the
66same flash chip.
67
68Caution: With an upgrade from an earlier U-Boot version the current
69environment will be erased since the environment is now saved in
70different sectors. By using the following command the environment can
71be saved after upgrading the U-Boot image and *before* resetting the
72board:
73
74setenv recover_env 'prot off FFF80000 FFF9FFFF;era FFF80000 FFF9FFFF;' \
75 'cp.b FFF60000 FFF80000 20000'
76
772006-07-27, Stefan Roese <sr@denx.de>