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Stefan Roese17ceb062008-06-02 14:59:21 +02001/*
2 * (C) Copyright 2008
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese17ceb062008-06-02 14:59:21 +02006 */
7
8#ifndef _PPC4xx_SDRAM_H_
9#define _PPC4xx_SDRAM_H_
10
11#if defined(CONFIG_SDRAM_PPC4xx_IBM_SDRAM)
12
13/*
14 * SDRAM Controller
15 */
Adam Grahamf6b6c452008-09-03 12:26:59 -070016
Stefan Roese17ceb062008-06-02 14:59:21 +020017#ifndef CONFIG_405EP
Stefan Roese95b602b2009-09-24 13:59:57 +020018#define SDRAM0_BESR0 0x00 /* bus error syndrome reg a */
19#define SDRAM0_BESRS0 0x04 /* bus error syndrome reg set a */
20#define SDRAM0_BESR1 0x08 /* bus error syndrome reg b */
21#define SDRAM0_BESRS1 0x0c /* bus error syndrome reg set b */
22#define SDRAM0_BEAR 0x10 /* bus error address reg */
Stefan Roese17ceb062008-06-02 14:59:21 +020023#endif
Stefan Roese95b602b2009-09-24 13:59:57 +020024#define SDRAM0_CFG 0x20 /* memory controller options 1 */
25#define SDRAM0_STATUS 0x24 /* memory status */
26#define SDRAM0_RTR 0x30 /* refresh timer reg */
27#define SDRAM0_PMIT 0x34 /* power management idle timer */
28#define SDRAM0_B0CR 0x40 /* memory bank 0 configuration */
29#define SDRAM0_B1CR 0x44 /* memory bank 1 configuration */
Stefan Roese17ceb062008-06-02 14:59:21 +020030#ifndef CONFIG_405EP
Stefan Roese95b602b2009-09-24 13:59:57 +020031#define SDRAM0_B2CR 0x48 /* memory bank 2 configuration */
32#define SDRAM0_B3CR 0x4c /* memory bank 3 configuration */
Stefan Roese17ceb062008-06-02 14:59:21 +020033#endif
Stefan Roese95b602b2009-09-24 13:59:57 +020034#define SDRAM0_TR 0x80 /* timing reg 1 */
Stefan Roese17ceb062008-06-02 14:59:21 +020035#ifndef CONFIG_405EP
Stefan Roese95b602b2009-09-24 13:59:57 +020036#define SDRAM0_ECCCFG 0x94 /* ECC configuration */
37#define SDRAM0_ECCESR 0x98 /* ECC error status */
Stefan Roese17ceb062008-06-02 14:59:21 +020038#endif
39
40#endif /* CONFIG_SDRAM_PPC4xx_IBM_SDRAM */
41
42#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
43
44/*
45 * Memory controller registers
46 */
47#define SDRAM_CFG0 0x20 /* memory controller options 0 */
48#define SDRAM_CFG1 0x21 /* memory controller options 1 */
49
Stefan Roeseb995d7c2010-07-21 11:08:27 +020050#define SDRAM0_BESR0 0x0000 /* bus error status reg 0 */
51#define SDRAM0_BESR1 0x0008 /* bus error status reg 1 */
Stefan Roese95b602b2009-09-24 13:59:57 +020052#define SDRAM0_BEAR 0x0010 /* bus error address reg */
53#define SDRAM0_SLIO 0x0018 /* ddr sdram slave interface options */
54#define SDRAM0_CFG0 0x0020 /* ddr sdram options 0 */
55#define SDRAM0_CFG1 0x0021 /* ddr sdram options 1 */
56#define SDRAM0_DEVOPT 0x0022 /* ddr sdram device options */
57#define SDRAM0_MCSTS 0x0024 /* memory controller status */
58#define SDRAM0_RTR 0x0030 /* refresh timer register */
59#define SDRAM0_PMIT 0x0034 /* power management idle timer */
60#define SDRAM0_UABBA 0x0038 /* plb UABus base address */
61#define SDRAM0_B0CR 0x0040 /* ddr sdram bank 0 configuration */
62#define SDRAM0_B1CR 0x0044 /* ddr sdram bank 1 configuration */
63#define SDRAM0_B2CR 0x0048 /* ddr sdram bank 2 configuration */
64#define SDRAM0_B3CR 0x004c /* ddr sdram bank 3 configuration */
65#define SDRAM0_TR0 0x0080 /* sdram timing register 0 */
66#define SDRAM0_TR1 0x0081 /* sdram timing register 1 */
67#define SDRAM0_CLKTR 0x0082 /* ddr clock timing register */
68#define SDRAM0_WDDCTR 0x0083 /* write data/dm/dqs clock timing reg */
69#define SDRAM0_DLYCAL 0x0084 /* delay line calibration register */
70#define SDRAM0_ECCESR 0x0098 /* ECC error status */
Stefan Roese17ceb062008-06-02 14:59:21 +020071
72/*
73 * Memory Controller Options 0
74 */
75#define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */
76#define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */
77#define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */
78#define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */
79#define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */
80#define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */
81#define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */
82#define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */
83#define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */
84#define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */
85#define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */
86#define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */
87
88/*
89 * Memory Controller Options 1
90 */
91#define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */
92#define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */
93
94/*
95 * SDRAM DEVPOT Options
96 */
97#define SDRAM_DEVOPT_DLL 0x80000000
98#define SDRAM_DEVOPT_DS 0x40000000
99
100/*
101 * SDRAM MCSTS Options
102 */
103#define SDRAM_MCSTS_MRSC 0x80000000
104#define SDRAM_MCSTS_SRMS 0x40000000
105#define SDRAM_MCSTS_CIS 0x20000000
Stefan Roesefb951692009-09-28 17:33:45 +0200106#define SDRAM_MCSTS_IDLE_NOT 0x00000000 /* Mem contr not idle */
Stefan Roese17ceb062008-06-02 14:59:21 +0200107
108/*
109 * SDRAM Refresh Timer Register
110 */
111#define SDRAM_RTR_RINT_MASK 0xFFFF0000
112#define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK)
113
114/*
115 * SDRAM UABus Base Address Reg
116 */
117#define SDRAM_UABBA_UBBA_MASK 0x0000000F
118
119/*
120 * Memory Bank 0-7 configuration
121 */
122#define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */
123#define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */
124#define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */
125#define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */
126#define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */
127#define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */
128#define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */
129#define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */
130#define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */
131#define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */
132#define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */
133#define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */
134#define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */
135#define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */
136#define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */
137
138/*
139 * SDRAM TR0 Options
140 */
141#define SDRAM_TR0_SDWR_MASK 0x80000000
142#define SDRAM_TR0_SDWR_2_CLK 0x00000000
143#define SDRAM_TR0_SDWR_3_CLK 0x80000000
144#define SDRAM_TR0_SDWD_MASK 0x40000000
145#define SDRAM_TR0_SDWD_0_CLK 0x00000000
146#define SDRAM_TR0_SDWD_1_CLK 0x40000000
147#define SDRAM_TR0_SDCL_MASK 0x01800000
148#define SDRAM_TR0_SDCL_2_0_CLK 0x00800000
149#define SDRAM_TR0_SDCL_2_5_CLK 0x01000000
150#define SDRAM_TR0_SDCL_3_0_CLK 0x01800000
151#define SDRAM_TR0_SDPA_MASK 0x000C0000
152#define SDRAM_TR0_SDPA_2_CLK 0x00040000
153#define SDRAM_TR0_SDPA_3_CLK 0x00080000
154#define SDRAM_TR0_SDPA_4_CLK 0x000C0000
155#define SDRAM_TR0_SDCP_MASK 0x00030000
156#define SDRAM_TR0_SDCP_2_CLK 0x00000000
157#define SDRAM_TR0_SDCP_3_CLK 0x00010000
158#define SDRAM_TR0_SDCP_4_CLK 0x00020000
159#define SDRAM_TR0_SDCP_5_CLK 0x00030000
160#define SDRAM_TR0_SDLD_MASK 0x0000C000
161#define SDRAM_TR0_SDLD_1_CLK 0x00000000
162#define SDRAM_TR0_SDLD_2_CLK 0x00004000
163#define SDRAM_TR0_SDRA_MASK 0x0000001C
164#define SDRAM_TR0_SDRA_6_CLK 0x00000000
165#define SDRAM_TR0_SDRA_7_CLK 0x00000004
166#define SDRAM_TR0_SDRA_8_CLK 0x00000008
167#define SDRAM_TR0_SDRA_9_CLK 0x0000000C
168#define SDRAM_TR0_SDRA_10_CLK 0x00000010
169#define SDRAM_TR0_SDRA_11_CLK 0x00000014
170#define SDRAM_TR0_SDRA_12_CLK 0x00000018
171#define SDRAM_TR0_SDRA_13_CLK 0x0000001C
172#define SDRAM_TR0_SDRD_MASK 0x00000003
173#define SDRAM_TR0_SDRD_2_CLK 0x00000001
174#define SDRAM_TR0_SDRD_3_CLK 0x00000002
175#define SDRAM_TR0_SDRD_4_CLK 0x00000003
176
177/*
178 * SDRAM TR1 Options
179 */
180#define SDRAM_TR1_RDSS_MASK 0xC0000000
181#define SDRAM_TR1_RDSS_TR0 0x00000000
182#define SDRAM_TR1_RDSS_TR1 0x40000000
183#define SDRAM_TR1_RDSS_TR2 0x80000000
184#define SDRAM_TR1_RDSS_TR3 0xC0000000
185#define SDRAM_TR1_RDSL_MASK 0x00C00000
186#define SDRAM_TR1_RDSL_STAGE1 0x00000000
187#define SDRAM_TR1_RDSL_STAGE2 0x00400000
188#define SDRAM_TR1_RDSL_STAGE3 0x00800000
189#define SDRAM_TR1_RDCD_MASK 0x00000800
190#define SDRAM_TR1_RDCD_RCD_0_0 0x00000000
191#define SDRAM_TR1_RDCD_RCD_1_2 0x00000800
192#define SDRAM_TR1_RDCT_MASK 0x000001FF
193#define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK)
194#define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
195#define SDRAM_TR1_RDCT_MIN 0x00000000
196#define SDRAM_TR1_RDCT_MAX 0x000001FF
197
198/*
199 * SDRAM WDDCTR Options
200 */
201#define SDRAM_WDDCTR_WRCP_MASK 0xC0000000
202#define SDRAM_WDDCTR_WRCP_0DEG 0x00000000
203#define SDRAM_WDDCTR_WRCP_90DEG 0x40000000
204#define SDRAM_WDDCTR_WRCP_180DEG 0x80000000
205#define SDRAM_WDDCTR_DCD_MASK 0x000001FF
206
207/*
208 * SDRAM CLKTR Options
209 */
210#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
211#define SDRAM_CLKTR_CLKP_0DEG 0x00000000
212#define SDRAM_CLKTR_CLKP_90DEG 0x40000000
213#define SDRAM_CLKTR_CLKP_180DEG 0x80000000
214#define SDRAM_CLKTR_DCDT_MASK 0x000001FF
215
216/*
217 * SDRAM DLYCAL Options
218 */
219#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
220#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
221#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
222
223#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR */
224
225#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
226
227#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
228#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
229#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
230
Adam Grahamf6b6c452008-09-03 12:26:59 -0700231#if !defined(CONFIG_405EX)
Stefan Roese17ceb062008-06-02 14:59:21 +0200232/*
233 * Memory queue defines
234 */
Prodyut Hazarika079589b2008-08-20 09:38:51 -0700235#define SDRAMQ_DCR_BASE 0x040
Stefan Roese17ceb062008-06-02 14:59:21 +0200236
Prodyut Hazarika079589b2008-08-20 09:38:51 -0700237#define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */
238#define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */
239#define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */
240#define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */
241#define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */
242#define SDRAM_CONF1HB_AAFR 0x80000000 /* Address Ack on First Request - Bit 0 */
243#define SDRAM_CONF1HB_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */
244#define SDRAM_CONF1HB_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */
245#define SDRAM_CONF1HB_PRW 0x00020000 /* PLB Read Wait - Bit 14 */
Yuri Tikhonovbf29e0e2008-10-17 12:54:18 +0200246#define SDRAM_CONF1HB_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */
Prodyut Hazarika079589b2008-08-20 09:38:51 -0700247#define SDRAM_CONF1HB_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */
248#define SDRAM_CONF1HB_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */
Yuri Tikhonovbf29e0e2008-10-17 12:54:18 +0200249#define SDRAM_CONF1HB_WRCL 0x00000080 /* MCIF Cycle Limit 1 - Bits 22..24 */
250#define SDRAM_CONF1HB_MASK 0x0000F380 /* RPLM & WRCL mask */
Prodyut Hazarika079589b2008-08-20 09:38:51 -0700251
252#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */
253#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */
254#define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */
255#define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */
256#define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */
257#define SDRAM_CONF1LL_AAFR 0x80000000 /* Address Ack on First Request - Bit 0 */
258#define SDRAM_CONF1LL_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */
259#define SDRAM_CONF1LL_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */
260#define SDRAM_CONF1LL_PRW 0x00020000 /* PLB Read Wait - Bit 14 */
Yuri Tikhonovbf29e0e2008-10-17 12:54:18 +0200261#define SDRAM_CONF1LL_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */
Prodyut Hazarika079589b2008-08-20 09:38:51 -0700262#define SDRAM_CONF1LL_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */
263#define SDRAM_CONF1LL_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */
Yuri Tikhonovbf29e0e2008-10-17 12:54:18 +0200264#define SDRAM_CONF1LL_MASK 0x0000F000 /* RPLM mask */
Prodyut Hazarika079589b2008-08-20 09:38:51 -0700265
266#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */
267#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */
268#define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */
269#define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */
270#define SDRAM_CONFPATHB_TPEN 0x08000000 /* Transaction Passing Enable - Bit 4 */
271
272#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */
Stefan Roese17ceb062008-06-02 14:59:21 +0200273
Stefan Roese17ceb062008-06-02 14:59:21 +0200274/*
275 * Memory Bank 0-7 configuration
276 */
277#if defined(CONFIG_440SPE) || \
Feng Kan96e5fc02008-07-08 22:48:07 -0700278 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Masahiro Yamada9ed32462014-09-29 01:37:59 +0900279 defined(CONFIG_460SX)
Stefan Roese17ceb062008-06-02 14:59:21 +0200280#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */
Stefan Roese5d812b82008-07-09 17:33:57 +0200281#define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000))
282#define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2)
Stefan Roese17ceb062008-06-02 14:59:21 +0200283#endif /* CONFIG_440SPE */
284#if defined(CONFIG_440SP)
285#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */
286#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((u32)(n))&0xFF800000))
287#define SDRAM_RXBAS_SDBA_DECODE(n) ((((u32)(n))&0xFF800000))
288#endif /* CONFIG_440SP */
289#define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */
290#define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((u32)(n))&0x3FF)<<6)
291#define SDRAM_RXBAS_SDSZ_DECODE(n) ((((u32)(n))>>6)&0x3FF)
292#define SDRAM_RXBAS_SDSZ_0 0x00000000 /* 0M */
293#define SDRAM_RXBAS_SDSZ_8 0x0000FFC0 /* 8M */
294#define SDRAM_RXBAS_SDSZ_16 0x0000FF80 /* 16M */
295#define SDRAM_RXBAS_SDSZ_32 0x0000FF00 /* 32M */
296#define SDRAM_RXBAS_SDSZ_64 0x0000FE00 /* 64M */
297#define SDRAM_RXBAS_SDSZ_128 0x0000FC00 /* 128M */
298#define SDRAM_RXBAS_SDSZ_256 0x0000F800 /* 256M */
299#define SDRAM_RXBAS_SDSZ_512 0x0000F000 /* 512M */
300#define SDRAM_RXBAS_SDSZ_1024 0x0000E000 /* 1024M */
301#define SDRAM_RXBAS_SDSZ_2048 0x0000C000 /* 2048M */
302#define SDRAM_RXBAS_SDSZ_4096 0x00008000 /* 4096M */
303#else /* CONFIG_405EX */
304/*
305 * XXX - ToDo:
306 * Revisit this file to check if all these 405EX defines are correct and
307 * can be used in the common 44x_spd_ddr2 code as well. sr, 2008-06-02
308 */
309#define SDRAM_RXBAS_SDSZ_MASK PPC_REG_VAL(19, 0xF)
310#define SDRAM_RXBAS_SDSZ_4MB PPC_REG_VAL(19, 0x0)
311#define SDRAM_RXBAS_SDSZ_8MB PPC_REG_VAL(19, 0x1)
312#define SDRAM_RXBAS_SDSZ_16MB PPC_REG_VAL(19, 0x2)
313#define SDRAM_RXBAS_SDSZ_32MB PPC_REG_VAL(19, 0x3)
314#define SDRAM_RXBAS_SDSZ_64MB PPC_REG_VAL(19, 0x4)
315#define SDRAM_RXBAS_SDSZ_128MB PPC_REG_VAL(19, 0x5)
316#define SDRAM_RXBAS_SDSZ_256MB PPC_REG_VAL(19, 0x6)
317#define SDRAM_RXBAS_SDSZ_512MB PPC_REG_VAL(19, 0x7)
318#define SDRAM_RXBAS_SDSZ_1024MB PPC_REG_VAL(19, 0x8)
319#define SDRAM_RXBAS_SDSZ_2048MB PPC_REG_VAL(19, 0x9)
320#define SDRAM_RXBAS_SDSZ_4096MB PPC_REG_VAL(19, 0xA)
321#define SDRAM_RXBAS_SDSZ_8192MB PPC_REG_VAL(19, 0xB)
322#define SDRAM_RXBAS_SDSZ_8 SDRAM_RXBAS_SDSZ_8MB
323#define SDRAM_RXBAS_SDSZ_16 SDRAM_RXBAS_SDSZ_16MB
324#define SDRAM_RXBAS_SDSZ_32 SDRAM_RXBAS_SDSZ_32MB
325#define SDRAM_RXBAS_SDSZ_64 SDRAM_RXBAS_SDSZ_64MB
326#define SDRAM_RXBAS_SDSZ_128 SDRAM_RXBAS_SDSZ_128MB
327#define SDRAM_RXBAS_SDSZ_256 SDRAM_RXBAS_SDSZ_256MB
328#define SDRAM_RXBAS_SDSZ_512 SDRAM_RXBAS_SDSZ_512MB
329#define SDRAM_RXBAS_SDSZ_1024 SDRAM_RXBAS_SDSZ_1024MB
330#define SDRAM_RXBAS_SDSZ_2048 SDRAM_RXBAS_SDSZ_2048MB
331#define SDRAM_RXBAS_SDSZ_4096 SDRAM_RXBAS_SDSZ_4096MB
332#define SDRAM_RXBAS_SDSZ_8192 SDRAM_RXBAS_SDSZ_8192MB
Stefan Roese2909ac02010-05-25 16:13:41 +0200333#endif /* CONFIG_405EX */
334
335/* The mode definitions are the same for all PPC4xx variants */
Stefan Roese17ceb062008-06-02 14:59:21 +0200336#define SDRAM_RXBAS_SDAM_MODE0 PPC_REG_VAL(23, 0x0)
337#define SDRAM_RXBAS_SDAM_MODE1 PPC_REG_VAL(23, 0x1)
338#define SDRAM_RXBAS_SDAM_MODE2 PPC_REG_VAL(23, 0x2)
339#define SDRAM_RXBAS_SDAM_MODE3 PPC_REG_VAL(23, 0x3)
340#define SDRAM_RXBAS_SDAM_MODE4 PPC_REG_VAL(23, 0x4)
341#define SDRAM_RXBAS_SDAM_MODE5 PPC_REG_VAL(23, 0x5)
342#define SDRAM_RXBAS_SDAM_MODE6 PPC_REG_VAL(23, 0x6)
343#define SDRAM_RXBAS_SDAM_MODE7 PPC_REG_VAL(23, 0x7)
344#define SDRAM_RXBAS_SDAM_MODE8 PPC_REG_VAL(23, 0x8)
345#define SDRAM_RXBAS_SDAM_MODE9 PPC_REG_VAL(23, 0x9)
346#define SDRAM_RXBAS_SDBE_DISABLE PPC_REG_VAL(31, 0x0)
347#define SDRAM_RXBAS_SDBE_ENABLE PPC_REG_VAL(31, 0x1)
Stefan Roese17ceb062008-06-02 14:59:21 +0200348
349/*
350 * Memory controller registers
351 */
Masahiro Yamada9ed32462014-09-29 01:37:59 +0900352#if defined(CONFIG_405EX)
Grant Ericksonad7382d2008-07-09 16:31:59 -0700353#define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */
354#define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */
355#define SDRAM_BEARL 0x02 /* PLB bus error address low */
356#define SDRAM_BEARH 0x03 /* PLB bus error address high */
357#define SDRAM_WMIRQ 0x06 /* PLB write master interrupt (read/clear) */
358#define SDRAM_WMIRQT 0x07 /* PLB write master interrupt (test/set) */
359#define SDRAM_PLBOPT 0x08 /* PLB slave options */
360#define SDRAM_PUABA 0x09 /* PLB upper address base */
Grant Erickson5b457d02008-07-09 11:55:46 -0700361#define SDRAM_MCSTAT 0x1F /* memory controller status */
Masahiro Yamada9ed32462014-09-29 01:37:59 +0900362#else /* CONFIG_405EX */
Stefan Roese897d6ab2010-07-21 11:08:16 +0200363#define SDRAM_MCSTAT 0x14 /* memory controller status */
Masahiro Yamada9ed32462014-09-29 01:37:59 +0900364#endif /* CONFIG_405EX */
Stefan Roese17ceb062008-06-02 14:59:21 +0200365#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
366#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
367#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
368#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */
369#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */
370#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */
371#define SDRAM_CODT 0x26 /* on die termination for controller */
372#define SDRAM_VVPR 0x27 /* variable VRef programmming */
373#define SDRAM_OPARS 0x28 /* on chip driver control setup */
374#define SDRAM_OPART 0x29 /* on chip driver control trigger */
375#define SDRAM_RTR 0x30 /* refresh timer */
376#define SDRAM_PMIT 0x34 /* power management idle timer */
377#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */
378#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */
379#define SDRAM_MB2CF 0x48
380#define SDRAM_MB3CF 0x4C
381#define SDRAM_INITPLR0 0x50 /* manual initialization control */
382#define SDRAM_INITPLR1 0x51 /* manual initialization control */
383#define SDRAM_INITPLR2 0x52 /* manual initialization control */
384#define SDRAM_INITPLR3 0x53 /* manual initialization control */
385#define SDRAM_INITPLR4 0x54 /* manual initialization control */
386#define SDRAM_INITPLR5 0x55 /* manual initialization control */
387#define SDRAM_INITPLR6 0x56 /* manual initialization control */
388#define SDRAM_INITPLR7 0x57 /* manual initialization control */
389#define SDRAM_INITPLR8 0x58 /* manual initialization control */
390#define SDRAM_INITPLR9 0x59 /* manual initialization control */
391#define SDRAM_INITPLR10 0x5a /* manual initialization control */
392#define SDRAM_INITPLR11 0x5b /* manual initialization control */
393#define SDRAM_INITPLR12 0x5c /* manual initialization control */
394#define SDRAM_INITPLR13 0x5d /* manual initialization control */
395#define SDRAM_INITPLR14 0x5e /* manual initialization control */
396#define SDRAM_INITPLR15 0x5f /* manual initialization control */
397#define SDRAM_RQDC 0x70 /* read DQS delay control */
398#define SDRAM_RFDC 0x74 /* read feedback delay control */
399#define SDRAM_RDCC 0x78 /* read data capture control */
400#define SDRAM_DLCR 0x7A /* delay line calibration */
401#define SDRAM_CLKTR 0x80 /* DDR clock timing */
402#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */
403#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */
404#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */
405#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */
406#define SDRAM_MMODE 0x88 /* memory mode */
407#define SDRAM_MEMODE 0x89 /* memory extended mode */
Stefan Roesefb951692009-09-28 17:33:45 +0200408#define SDRAM_ECCES 0x98 /* ECC error status */
Stefan Roese17ceb062008-06-02 14:59:21 +0200409#define SDRAM_CID 0xA4 /* core ID */
Masahiro Yamada9ed32462014-09-29 01:37:59 +0900410#if !defined(CONFIG_405EX)
Stefan Roese17ceb062008-06-02 14:59:21 +0200411#define SDRAM_RID 0xA8 /* revision ID */
Grant Ericksonad7382d2008-07-09 16:31:59 -0700412#endif
413#define SDRAM_FCSR 0xB0 /* feedback calibration status */
Stefan Roese17ceb062008-06-02 14:59:21 +0200414#define SDRAM_RTSR 0xB1 /* run time status tracking */
Masahiro Yamada9ed32462014-09-29 01:37:59 +0900415#if defined(CONFIG_405EX)
Grant Ericksonad7382d2008-07-09 16:31:59 -0700416#define SDRAM_RID 0xF8 /* revision ID */
417#endif
418
419/*
420 * Memory Controller Bus Error Status
421 */
422#define SDRAM_BESR_MASK PPC_REG_VAL(7, 0xFF)
423#define SDRAM_BESR_M0ID_MASK PPC_REG_VAL(3, 0xF)
424#define SDRAM_BESR_M0ID_ICU PPC_REG_VAL(3, 0x0)
425#define SDRAM_BESR_M0ID_PCIE0 PPC_REG_VAL(3, 0x1)
426#define SDRAM_BESR_M0ID_PCIE1 PPC_REG_VAL(3, 0x2)
427#define SDRAM_BESR_M0ID_DMA PPC_REG_VAL(3, 0x3)
428#define SDRAM_BESR_M0ID_DCU PPC_REG_VAL(3, 0x4)
429#define SDRAM_BESR_M0ID_OPB PPC_REG_VAL(3, 0x5)
430#define SDRAM_BESR_M0ID_MAL PPC_REG_VAL(3, 0x6)
431#define SDRAM_BESR_M0ID_SEC PPC_REG_VAL(3, 0x7)
432#define SDRAM_BESR_M0ET_MASK PPC_REG_VAL(6, 0x7)
433#define SDRAM_BESR_M0ET_NONE PPC_REG_VAL(6, 0x0)
434#define SDRAM_BESR_M0ET_ECC PPC_REG_VAL(6, 0x1)
435#define SDRAM_BESR_M0RW_WRITE PPC_REG_VAL(7, 0)
436#define SDRAM_BESR_M0RW_READ PPC_REG_VAL(8, 1)
Stefan Roese17ceb062008-06-02 14:59:21 +0200437
438/*
439 * Memory Controller Status
440 */
441#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */
442#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */
443#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */
444#define SDRAM_MCSTAT_SRMS_MASK 0x40000000 /* Mem self refresh stat mask */
445#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */
446#define SDRAM_MCSTAT_SRMS_SF 0x40000000 /* Mem in self refresh */
447#define SDRAM_MCSTAT_IDLE_MASK 0x20000000 /* Mem self refresh stat mask */
448#define SDRAM_MCSTAT_IDLE_NOT 0x00000000 /* Mem contr not idle */
449#define SDRAM_MCSTAT_IDLE 0x20000000 /* Mem contr idle */
450
451/*
452 * Memory Controller Options 1
453 */
454#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask*/
455#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */
456#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */
457#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */
458#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/
459#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((u32)(n))>>28)&0x3)
460#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */
461#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */
462#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */
463#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */
464#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */
465#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */
466#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */
467#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */
468#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */
469#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */
470#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */
471#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */
472#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */
473#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */
474#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */
475#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */
476#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */
477#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */
478#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */
479#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */
480#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */
481#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */
482#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */
483#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */
484#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */
485#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */
486#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */
487#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */
488#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */
489
490/*
491 * Memory Controller Options 2
492 */
493#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */
494#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */
495#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */
496#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */
497#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */
498#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */
499#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */
500#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */
501#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */
502#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */
503#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */
504#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */
505#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */
506#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */
507#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */
508#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/
509#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */
510#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */
511
512/*
513 * SDRAM Refresh Timer Register
514 */
515#define SDRAM_RTR_RINT_MASK 0xFFF80000
516#define SDRAM_RTR_RINT_ENCODE(n) ((((u32)(n))&0xFFF8)<<16)
517#define SDRAM_RTR_RINT_DECODE(n) ((((u32)(n))>>16)&0xFFF8)
518
519/*
520 * SDRAM Read DQS Delay Control Register
521 */
522#define SDRAM_RQDC_RQDE_MASK 0x80000000
523#define SDRAM_RQDC_RQDE_DISABLE 0x00000000
524#define SDRAM_RQDC_RQDE_ENABLE 0x80000000
525#define SDRAM_RQDC_RQFD_MASK 0x000001FF
526#define SDRAM_RQDC_RQFD_ENCODE(n) ((((u32)(n))&0x1FF)<<0)
527
528#define SDRAM_RQDC_RQFD_MAX 0x1FF
529
530/*
531 * SDRAM Read Data Capture Control Register
532 */
533#define SDRAM_RDCC_RDSS_MASK 0xC0000000
534#define SDRAM_RDCC_RDSS_T1 0x00000000
535#define SDRAM_RDCC_RDSS_T2 0x40000000
536#define SDRAM_RDCC_RDSS_T3 0x80000000
537#define SDRAM_RDCC_RDSS_T4 0xC0000000
538#define SDRAM_RDCC_RSAE_MASK 0x00000001
539#define SDRAM_RDCC_RSAE_DISABLE 0x00000001
540#define SDRAM_RDCC_RSAE_ENABLE 0x00000000
Adam Grahamc6450122009-02-09 13:18:12 -0800541#define SDRAM_RDCC_RDSS_ENCODE(n) ((((u32)(n))&0x03)<<30)
542#define SDRAM_RDCC_RDSS_DECODE(n) ((((u32)(n))>>30)&0x03)
Stefan Roese17ceb062008-06-02 14:59:21 +0200543
544/*
545 * SDRAM Read Feedback Delay Control Register
546 */
547#define SDRAM_RFDC_ARSE_MASK 0x80000000
548#define SDRAM_RFDC_ARSE_DISABLE 0x80000000
549#define SDRAM_RFDC_ARSE_ENABLE 0x00000000
550#define SDRAM_RFDC_RFOS_MASK 0x007F0000
551#define SDRAM_RFDC_RFOS_ENCODE(n) ((((u32)(n))&0x7F)<<16)
552#define SDRAM_RFDC_RFFD_MASK 0x000007FF
553#define SDRAM_RFDC_RFFD_ENCODE(n) ((((u32)(n))&0x7FF)<<0)
554
555#define SDRAM_RFDC_RFFD_MAX 0x7FF
556
557/*
558 * SDRAM Delay Line Calibration Register
559 */
560#define SDRAM_DLCR_DCLM_MASK 0x80000000
Grant Erickson2e205082008-07-09 16:46:35 -0700561#define SDRAM_DLCR_DCLM_MANUAL 0x80000000
Stefan Roese17ceb062008-06-02 14:59:21 +0200562#define SDRAM_DLCR_DCLM_AUTO 0x00000000
563#define SDRAM_DLCR_DLCR_MASK 0x08000000
564#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000
565#define SDRAM_DLCR_DLCR_IDLE 0x00000000
566#define SDRAM_DLCR_DLCS_MASK 0x07000000
567#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000
568#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000
569#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000
570#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000
571#define SDRAM_DLCR_DLCS_ERROR 0x04000000
572#define SDRAM_DLCR_DLCV_MASK 0x000001FF
573#define SDRAM_DLCR_DLCV_ENCODE(n) ((((u32)(n))&0x1FF)<<0)
574#define SDRAM_DLCR_DLCV_DECODE(n) ((((u32)(n))>>0)&0x1FF)
575
576/*
Grant Erickson2e205082008-07-09 16:46:35 -0700577 * SDRAM Memory On Die Terimination Control Register
578 */
579#define SDRAM_MODT_ODTON_DISABLE PPC_REG_VAL(0, 0)
580#define SDRAM_MODT_ODTON_ENABLE PPC_REG_VAL(0, 1)
581#define SDRAM_MODT_EB1W_DISABLE PPC_REG_VAL(1, 0)
582#define SDRAM_MODT_EB1W_ENABLE PPC_REG_VAL(1, 1)
583#define SDRAM_MODT_EB1R_DISABLE PPC_REG_VAL(2, 0)
584#define SDRAM_MODT_EB1R_ENABLE PPC_REG_VAL(2, 1)
585#define SDRAM_MODT_EB0W_DISABLE PPC_REG_VAL(7, 0)
586#define SDRAM_MODT_EB0W_ENABLE PPC_REG_VAL(7, 1)
587#define SDRAM_MODT_EB0R_DISABLE PPC_REG_VAL(8, 0)
588#define SDRAM_MODT_EB0R_ENABLE PPC_REG_VAL(8, 1)
589
590/*
Stefan Roese17ceb062008-06-02 14:59:21 +0200591 * SDRAM Controller On Die Termination Register
592 */
Grant Erickson2e205082008-07-09 16:46:35 -0700593#define SDRAM_CODT_ODT_ON PPC_REG_VAL(0, 1)
594#define SDRAM_CODT_ODT_OFF PPC_REG_VAL(0, 0)
595#define SDRAM_CODT_RK1W_ON PPC_REG_VAL(1, 1)
596#define SDRAM_CODT_RK1W_OFF PPC_REG_VAL(1, 0)
597#define SDRAM_CODT_RK1R_ON PPC_REG_VAL(2, 1)
598#define SDRAM_CODT_RK1R_OFF PPC_REG_VAL(2, 0)
599#define SDRAM_CODT_RK0W_ON PPC_REG_VAL(7, 1)
600#define SDRAM_CODT_RK0W_OFF PPC_REG_VAL(7, 0)
601#define SDRAM_CODT_RK0R_ON PPC_REG_VAL(8, 1)
602#define SDRAM_CODT_RK0R_OFF PPC_REG_VAL(8, 0)
603#define SDRAM_CODT_ODTSH_NORMAL PPC_REG_VAL(10, 0)
604#define SDRAM_CODT_ODTSH_REMOVE_ONE_AT_END PPC_REG_VAL(10, 1)
605#define SDRAM_CODT_ODTSH_ADD_ONE_AT_START PPC_REG_VAL(10, 2)
606#define SDRAM_CODT_ODTSH_SHIFT_ONE_EARLIER PPC_REG_VAL(10, 3)
607#define SDRAM_CODT_CODTZ_75OHM PPC_REG_VAL(11, 0)
608#define SDRAM_CODT_CKEG_ON PPC_REG_VAL(12, 1)
609#define SDRAM_CODT_CKEG_OFF PPC_REG_VAL(12, 0)
610#define SDRAM_CODT_CTLG_ON PPC_REG_VAL(13, 1)
611#define SDRAM_CODT_CTLG_OFF PPC_REG_VAL(13, 0)
612#define SDRAM_CODT_FBDG_ON PPC_REG_VAL(14, 1)
613#define SDRAM_CODT_FBDG_OFF PPC_REG_VAL(14, 0)
614#define SDRAM_CODT_FBRG_ON PPC_REG_VAL(15, 1)
615#define SDRAM_CODT_FBRG_OFF PPC_REG_VAL(15, 0)
616#define SDRAM_CODT_CKLZ_36OHM PPC_REG_VAL(18, 1)
617#define SDRAM_CODT_CKLZ_18OHM PPC_REG_VAL(18, 0)
618#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK PPC_REG_VAL(26, 1)
619#define SDRAM_CODT_DQS_2_5_V_DDR1 PPC_REG_VAL(26, 0)
620#define SDRAM_CODT_DQS_1_8_V_DDR2 PPC_REG_VAL(26, 1)
621#define SDRAM_CODT_DQS_MASK PPC_REG_VAL(27, 1)
622#define SDRAM_CODT_DQS_DIFFERENTIAL PPC_REG_VAL(27, 0)
623#define SDRAM_CODT_DQS_SINGLE_END PPC_REG_VAL(27, 1)
624#define SDRAM_CODT_CKSE_DIFFERENTIAL PPC_REG_VAL(28, 0)
625#define SDRAM_CODT_CKSE_SINGLE_END PPC_REG_VAL(28, 1)
626#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END PPC_REG_VAL(29, 1)
627#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END PPC_REG_VAL(30, 1)
628#define SDRAM_CODT_IO_HIZ PPC_REG_VAL(31, 0)
629#define SDRAM_CODT_IO_NMODE PPC_REG_VAL(31, 1)
Stefan Roese17ceb062008-06-02 14:59:21 +0200630
631/*
Grant Erickson2e205082008-07-09 16:46:35 -0700632 * SDRAM Initialization Preload Register
Stefan Roese17ceb062008-06-02 14:59:21 +0200633 */
Grant Erickson2e205082008-07-09 16:46:35 -0700634#define SDRAM_INITPLR_ENABLE PPC_REG_VAL(0, 1)
635#define SDRAM_INITPLR_DISABLE PPC_REG_VAL(0, 0)
636#define SDRAM_INITPLR_IMWT_MASK PPC_REG_VAL(8, 0xFF)
637#define SDRAM_INITPLR_IMWT_ENCODE(n) PPC_REG_VAL(8, \
638 (static_cast(u32, \
639 n)) \
640 & 0xFF)
641#define SDRAM_INITPLR_ICMD_MASK PPC_REG_VAL(12, 0x7)
642#define SDRAM_INITPLR_ICMD_ENCODE(n) PPC_REG_VAL(12, \
643 (static_cast(u32, \
644 n)) \
645 & 0x7)
646#define SDRAM_INITPLR_IBA_MASK PPC_REG_VAL(15, 0x7)
647#define SDRAM_INITPLR_IBA_ENCODE(n) PPC_REG_VAL(15, \
648 (static_cast(u32, \
649 n)) \
650 & 0x7)
651#define SDRAM_INITPLR_IMA_MASK PPC_REG_VAL(31, 0x7FFF)
652#define SDRAM_INITPLR_IMA_ENCODE(n) PPC_REG_VAL(31, \
653 (static_cast(u32, \
654 n)) \
655 & 0x7FFF)
Stefan Roese17ceb062008-06-02 14:59:21 +0200656
657/*
Grant Erickson2e205082008-07-09 16:46:35 -0700658 * JEDEC DDR Initialization Commands
Stefan Roese17ceb062008-06-02 14:59:21 +0200659 */
Grant Erickson2e205082008-07-09 16:46:35 -0700660#define JEDEC_CMD_NOP 7
661#define JEDEC_CMD_PRECHARGE 2
662#define JEDEC_CMD_REFRESH 1
663#define JEDEC_CMD_EMR 0
664#define JEDEC_CMD_READ 5
665#define JEDEC_CMD_WRITE 4
666
667/*
668 * JEDEC Precharge Command Memory Address Arguments
669 */
670#define JEDEC_MA_PRECHARGE_ONE (0 << 10)
671#define JEDEC_MA_PRECHARGE_ALL (1 << 10)
672
673/*
674 * JEDEC DDR EMR Command Bank Address Arguments
675 */
676#define JEDEC_BA_MR 0
677#define JEDEC_BA_EMR 1
678#define JEDEC_BA_EMR2 2
679#define JEDEC_BA_EMR3 3
680
681/*
682 * JEDEC DDR Mode Register
683 */
684#define JEDEC_MA_MR_PDMODE_FAST_EXIT (0 << 12)
685#define JEDEC_MA_MR_PDMODE_SLOW_EXIT (1 << 12)
686#define JEDEC_MA_MR_WR_MASK (0x7 << 9)
687#define JEDEC_MA_MR_WR_DDR1 (0x0 << 9)
688#define JEDEC_MA_MR_WR_DDR2_2_CYC (0x1 << 9)
689#define JEDEC_MA_MR_WR_DDR2_3_CYC (0x2 << 9)
690#define JEDEC_MA_MR_WR_DDR2_4_CYC (0x3 << 9)
691#define JEDEC_MA_MR_WR_DDR2_5_CYC (0x4 << 9)
692#define JEDEC_MA_MR_WR_DDR2_6_CYC (0x5 << 9)
693#define JEDEC_MA_MR_DLL_RESET (1 << 8)
694#define JEDEC_MA_MR_MODE_NORMAL (0 << 8)
695#define JEDEC_MA_MR_MODE_TEST (1 << 8)
696#define JEDEC_MA_MR_CL_MASK (0x7 << 4)
697#define JEDEC_MA_MR_CL_DDR1_2_0_CLK (0x2 << 4)
698#define JEDEC_MA_MR_CL_DDR1_2_5_CLK (0x6 << 4)
699#define JEDEC_MA_MR_CL_DDR1_3_0_CLK (0x3 << 4)
700#define JEDEC_MA_MR_CL_DDR2_2_0_CLK (0x2 << 4)
701#define JEDEC_MA_MR_CL_DDR2_3_0_CLK (0x3 << 4)
702#define JEDEC_MA_MR_CL_DDR2_4_0_CLK (0x4 << 4)
703#define JEDEC_MA_MR_CL_DDR2_5_0_CLK (0x5 << 4)
704#define JEDEC_MA_MR_CL_DDR2_6_0_CLK (0x6 << 4)
705#define JEDEC_MA_MR_CL_DDR2_7_0_CLK (0x7 << 4)
706#define JEDEC_MA_MR_BTYP_SEQUENTIAL (0 << 3)
707#define JEDEC_MA_MR_BTYP_INTERLEAVED (1 << 3)
708#define JEDEC_MA_MR_BLEN_MASK (0x7 << 0)
709#define JEDEC_MA_MR_BLEN_4 (2 << 0)
710#define JEDEC_MA_MR_BLEN_8 (3 << 0)
711
712/*
713 * JEDEC DDR Extended Mode Register
714 */
715#define JEDEC_MA_EMR_OUTPUT_MASK (1 << 12)
716#define JEDEC_MA_EMR_OUTPUT_ENABLE (0 << 12)
717#define JEDEC_MA_EMR_OUTPUT_DISABLE (1 << 12)
718#define JEDEC_MA_EMR_RQDS_MASK (1 << 11)
719#define JEDEC_MA_EMR_RDQS_DISABLE (0 << 11)
720#define JEDEC_MA_EMR_RDQS_ENABLE (1 << 11)
721#define JEDEC_MA_EMR_DQS_MASK (1 << 10)
722#define JEDEC_MA_EMR_DQS_DISABLE (1 << 10)
723#define JEDEC_MA_EMR_DQS_ENABLE (0 << 10)
724#define JEDEC_MA_EMR_OCD_MASK (0x7 << 7)
725#define JEDEC_MA_EMR_OCD_EXIT (0 << 7)
726#define JEDEC_MA_EMR_OCD_ENTER (7 << 7)
727#define JEDEC_MA_EMR_AL_DDR1_0_CYC (0 << 3)
728#define JEDEC_MA_EMR_AL_DDR2_1_CYC (1 << 3)
729#define JEDEC_MA_EMR_AL_DDR2_2_CYC (2 << 3)
730#define JEDEC_MA_EMR_AL_DDR2_3_CYC (3 << 3)
731#define JEDEC_MA_EMR_AL_DDR2_4_CYC (4 << 3)
732#define JEDEC_MA_EMR_RTT_MASK (0x11 << 2)
733#define JEDEC_MA_EMR_RTT_DISABLED (0x00 << 2)
734#define JEDEC_MA_EMR_RTT_75OHM (0x01 << 2)
735#define JEDEC_MA_EMR_RTT_150OHM (0x10 << 2)
736#define JEDEC_MA_EMR_RTT_50OHM (0x11 << 2)
737#define JEDEC_MA_EMR_ODS_MASK (1 << 1)
738#define JEDEC_MA_EMR_ODS_NORMAL (0 << 1)
739#define JEDEC_MA_EMR_ODS_WEAK (1 << 1)
740#define JEDEC_MA_EMR_DLL_MASK (1 << 0)
741#define JEDEC_MA_EMR_DLL_ENABLE (0 << 0)
742#define JEDEC_MA_EMR_DLL_DISABLE (1 << 0)
743
744/*
745 * JEDEC DDR Extended Mode Register 2
746 */
747#define JEDEC_MA_EMR2_TEMP_COMMERCIAL (0 << 7)
748#define JEDEC_MA_EMR2_TEMP_INDUSTRIAL (1 << 7)
749
750/*
751 * SDRAM Mode Register (Corresponds 1:1 w/ JEDEC Mode Register)
752 */
753#define SDRAM_MMODE_WR_MASK JEDEC_MA_MR_WR_MASK
754#define SDRAM_MMODE_WR_DDR1 JEDEC_MA_MR_WR_DDR1
755#define SDRAM_MMODE_WR_DDR2_2_CYC JEDEC_MA_MR_WR_DDR2_2_CYC
756#define SDRAM_MMODE_WR_DDR2_3_CYC JEDEC_MA_MR_WR_DDR2_3_CYC
757#define SDRAM_MMODE_WR_DDR2_4_CYC JEDEC_MA_MR_WR_DDR2_4_CYC
758#define SDRAM_MMODE_WR_DDR2_5_CYC JEDEC_MA_MR_WR_DDR2_5_CYC
759#define SDRAM_MMODE_WR_DDR2_6_CYC JEDEC_MA_MR_WR_DDR2_6_CYC
760#define SDRAM_MMODE_DCL_MASK JEDEC_MA_MR_CL_MASK
761#define SDRAM_MMODE_DCL_DDR1_2_0_CLK JEDEC_MA_MR_CL_DDR1_2_0_CLK
762#define SDRAM_MMODE_DCL_DDR1_2_5_CLK JEDEC_MA_MR_CL_DDR1_2_5_CLK
763#define SDRAM_MMODE_DCL_DDR1_3_0_CLK JEDEC_MA_MR_CL_DDR1_3_0_CLK
764#define SDRAM_MMODE_DCL_DDR2_2_0_CLK JEDEC_MA_MR_CL_DDR2_2_0_CLK
765#define SDRAM_MMODE_DCL_DDR2_3_0_CLK JEDEC_MA_MR_CL_DDR2_3_0_CLK
766#define SDRAM_MMODE_DCL_DDR2_4_0_CLK JEDEC_MA_MR_CL_DDR2_4_0_CLK
767#define SDRAM_MMODE_DCL_DDR2_5_0_CLK JEDEC_MA_MR_CL_DDR2_5_0_CLK
768#define SDRAM_MMODE_DCL_DDR2_6_0_CLK JEDEC_MA_MR_CL_DDR2_6_0_CLK
769#define SDRAM_MMODE_DCL_DDR2_7_0_CLK JEDEC_MA_MR_CL_DDR2_7_0_CLK
770#define SDRAM_MMODE_BTYP_SEQUENTIAL JEDEC_MA_MR_BTYP_SEQUENTIAL
771#define SDRAM_MMODE_BTYP_INTERLEAVED JEDEC_MA_MR_BTYP_INTERLEAVED
772#define SDRAM_MMODE_BLEN_MASK JEDEC_MA_MR_BLEN_MASK
773#define SDRAM_MMODE_BLEN_4 JEDEC_MA_MR_BLEN_4
774#define SDRAM_MMODE_BLEN_8 JEDEC_MA_MR_BLEN_8
775
776/*
777 * SDRAM Extended Mode Register (Corresponds 1:1 w/ JEDEC Extended
778 * Mode Register)
779 */
780#define SDRAM_MEMODE_QOFF_MASK JEDEC_MA_EMR_OUTPUT_MASK
781#define SDRAM_MEMODE_QOFF_DISABLE JEDEC_MA_EMR_OUTPUT_DISABLE
782#define SDRAM_MEMODE_QOFF_ENABLE JEDEC_MA_EMR_OUTPUT_ENABLE
783#define SDRAM_MEMODE_RDQS_MASK JEDEC_MA_EMR_RQDS_MASK
784#define SDRAM_MEMODE_RDQS_DISABLE JEDEC_MA_EMR_RDQS_DISABLE
785#define SDRAM_MEMODE_RDQS_ENABLE JEDEC_MA_EMR_RDQS_ENABLE
786#define SDRAM_MEMODE_DQS_MASK JEDEC_MA_EMR_DQS_MASK
787#define SDRAM_MEMODE_DQS_DISABLE JEDEC_MA_EMR_DQS_DISABLE
788#define SDRAM_MEMODE_DQS_ENABLE JEDEC_MA_EMR_DQS_ENABLE
789#define SDRAM_MEMODE_AL_DDR1_0_CYC JEDEC_MA_EMR_AL_DDR1_0_CYC
790#define SDRAM_MEMODE_AL_DDR2_1_CYC JEDEC_MA_EMR_AL_DDR2_1_CYC
791#define SDRAM_MEMODE_AL_DDR2_2_CYC JEDEC_MA_EMR_AL_DDR2_2_CYC
792#define SDRAM_MEMODE_AL_DDR2_3_CYC JEDEC_MA_EMR_AL_DDR2_3_CYC
793#define SDRAM_MEMODE_AL_DDR2_4_CYC JEDEC_MA_EMR_AL_DDR2_4_CYC
794#define SDRAM_MEMODE_RTT_MASK JEDEC_MA_EMR_RTT_MASK
795#define SDRAM_MEMODE_RTT_DISABLED JEDEC_MA_EMR_RTT_DISABLED
796#define SDRAM_MEMODE_RTT_75OHM JEDEC_MA_EMR_RTT_75OHM
797#define SDRAM_MEMODE_RTT_150OHM JEDEC_MA_EMR_RTT_150OHM
798#define SDRAM_MEMODE_RTT_50OHM JEDEC_MA_EMR_RTT_50OHM
799#define SDRAM_MEMODE_DIC_MASK JEDEC_MA_EMR_ODS_MASK
800#define SDRAM_MEMODE_DIC_NORMAL JEDEC_MA_EMR_ODS_NORMAL
801#define SDRAM_MEMODE_DIC_WEAK JEDEC_MA_EMR_ODS_WEAK
802#define SDRAM_MEMODE_DLL_MASK JEDEC_MA_EMR_DLL_MASK
803#define SDRAM_MEMODE_DLL_DISABLE JEDEC_MA_EMR_DLL_DISABLE
804#define SDRAM_MEMODE_DLL_ENABLE JEDEC_MA_EMR_DLL_ENABLE
Stefan Roese17ceb062008-06-02 14:59:21 +0200805
806/*
807 * SDRAM Clock Timing Register
808 */
809#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
810#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000
811#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000
812#define SDRAM_CLKTR_CLKP_90_DEG_ADV 0x40000000
813#define SDRAM_CLKTR_CLKP_270_DEG_ADV 0xC0000000
814
815/*
816 * SDRAM Write Timing Register
817 */
818#define SDRAM_WRDTR_LLWP_MASK 0x10000000
819#define SDRAM_WRDTR_LLWP_DIS 0x10000000
820#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000
821#define SDRAM_WRDTR_WTR_MASK 0x0E000000
822#define SDRAM_WRDTR_WTR_0_DEG 0x06000000
823#define SDRAM_WRDTR_WTR_90_DEG_ADV 0x04000000
824#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000
825#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000
826
827/*
828 * SDRAM SDTR1 Options
829 */
830#define SDRAM_SDTR1_LDOF_MASK 0x80000000
831#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000
832#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000
833#define SDRAM_SDTR1_RTW_MASK 0x00F00000
834#define SDRAM_SDTR1_RTW_2_CLK 0x00200000
835#define SDRAM_SDTR1_RTW_3_CLK 0x00300000
836#define SDRAM_SDTR1_WTWO_MASK 0x000F0000
837#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000
838#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000
839#define SDRAM_SDTR1_RTRO_MASK 0x0000F000
840#define SDRAM_SDTR1_RTRO_1_CLK 0x00001000
841#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000
842
843/*
844 * SDRAM SDTR2 Options
845 */
846#define SDRAM_SDTR2_RCD_MASK 0xF0000000
847#define SDRAM_SDTR2_RCD_1_CLK 0x10000000
848#define SDRAM_SDTR2_RCD_2_CLK 0x20000000
849#define SDRAM_SDTR2_RCD_3_CLK 0x30000000
850#define SDRAM_SDTR2_RCD_4_CLK 0x40000000
851#define SDRAM_SDTR2_RCD_5_CLK 0x50000000
852#define SDRAM_SDTR2_WTR_MASK 0x0F000000
853#define SDRAM_SDTR2_WTR_1_CLK 0x01000000
854#define SDRAM_SDTR2_WTR_2_CLK 0x02000000
855#define SDRAM_SDTR2_WTR_3_CLK 0x03000000
856#define SDRAM_SDTR2_WTR_4_CLK 0x04000000
857#define SDRAM_SDTR3_WTR_ENCODE(n) ((((u32)(n))&0xF)<<24)
858#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000
859#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000
860#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000
861#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000
862#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000
863#define SDRAM_SDTR2_WPC_MASK 0x0000F000
864#define SDRAM_SDTR2_WPC_2_CLK 0x00002000
865#define SDRAM_SDTR2_WPC_3_CLK 0x00003000
866#define SDRAM_SDTR2_WPC_4_CLK 0x00004000
867#define SDRAM_SDTR2_WPC_5_CLK 0x00005000
868#define SDRAM_SDTR2_WPC_6_CLK 0x00006000
869#define SDRAM_SDTR3_WPC_ENCODE(n) ((((u32)(n))&0xF)<<12)
870#define SDRAM_SDTR2_RPC_MASK 0x00000F00
871#define SDRAM_SDTR2_RPC_2_CLK 0x00000200
872#define SDRAM_SDTR2_RPC_3_CLK 0x00000300
873#define SDRAM_SDTR2_RPC_4_CLK 0x00000400
874#define SDRAM_SDTR2_RP_MASK 0x000000F0
875#define SDRAM_SDTR2_RP_3_CLK 0x00000030
876#define SDRAM_SDTR2_RP_4_CLK 0x00000040
877#define SDRAM_SDTR2_RP_5_CLK 0x00000050
878#define SDRAM_SDTR2_RP_6_CLK 0x00000060
879#define SDRAM_SDTR2_RP_7_CLK 0x00000070
880#define SDRAM_SDTR2_RRD_MASK 0x0000000F
881#define SDRAM_SDTR2_RRD_2_CLK 0x00000002
882#define SDRAM_SDTR2_RRD_3_CLK 0x00000003
883
884/*
885 * SDRAM SDTR3 Options
886 */
887#define SDRAM_SDTR3_RAS_MASK 0x1F000000
888#define SDRAM_SDTR3_RAS_ENCODE(n) ((((u32)(n))&0x1F)<<24)
889#define SDRAM_SDTR3_RC_MASK 0x001F0000
890#define SDRAM_SDTR3_RC_ENCODE(n) ((((u32)(n))&0x1F)<<16)
891#define SDRAM_SDTR3_XCS_MASK 0x00001F00
892#define SDRAM_SDTR3_XCS 0x00000D00
893#define SDRAM_SDTR3_RFC_MASK 0x0000003F
894#define SDRAM_SDTR3_RFC_ENCODE(n) ((((u32)(n))&0x3F)<<0)
895
896/*
Grant Ericksonad7382d2008-07-09 16:31:59 -0700897 * ECC Error Status
898 */
899#define SDRAM_ECCES_MASK PPC_REG_VAL(21, 0x3FFFFF)
900#define SDRAM_ECCES_BNCE_MASK PPC_REG_VAL(15, 0xFFFF)
901#define SDRAM_ECCES_BNCE_ENCODE(lane) PPC_REG_VAL(((lane) & 0xF), 1)
902#define SDRAM_ECCES_CKBER_MASK PPC_REG_VAL(17, 0x3)
903#define SDRAM_ECCES_CKBER_NONE PPC_REG_VAL(17, 0)
904#define SDRAM_ECCES_CKBER_16_ECC_0_3 PPC_REG_VAL(17, 2)
905#define SDRAM_ECCES_CKBER_32_ECC_0_3 PPC_REG_VAL(17, 1)
906#define SDRAM_ECCES_CKBER_32_ECC_4_8 PPC_REG_VAL(17, 2)
907#define SDRAM_ECCES_CKBER_32_ECC_0_8 PPC_REG_VAL(17, 3)
908#define SDRAM_ECCES_CE PPC_REG_VAL(18, 1)
909#define SDRAM_ECCES_UE PPC_REG_VAL(19, 1)
910#define SDRAM_ECCES_BKNER_MASK PPC_REG_VAL(21, 0x3)
911#define SDRAM_ECCES_BK0ER PPC_REG_VAL(20, 1)
912#define SDRAM_ECCES_BK1ER PPC_REG_VAL(21, 1)
913
914/*
Stefan Roese17ceb062008-06-02 14:59:21 +0200915 * Memory Bank 0-1 configuration
916 */
917#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */
918#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */
919#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */
920#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */
921#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */
922#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */
923#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */
924#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */
925#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */
926#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */
927#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */
928#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */
929#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */
930#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
931
932#define SDRAM_RTSR_TRK1SM_MASK 0xC0000000 /* Tracking State Mach 1*/
933#define SDRAM_RTSR_TRK1SM_ATBASE 0x00000000 /* atbase state */
934#define SDRAM_RTSR_TRK1SM_MISSED 0x40000000 /* missed state */
935#define SDRAM_RTSR_TRK1SM_ATPLS1 0x80000000 /* atpls1 state */
936#define SDRAM_RTSR_TRK1SM_RESET 0xC0000000 /* reset state */
937
Stefan Roese17ceb062008-06-02 14:59:21 +0200938#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */
939
940#if defined(CONFIG_SDRAM_PPC4xx_DENALI_DDR2)
941/*
942 * SDRAM Controller
943 */
944#define DDR0_00 0x00
945#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */
946#define DDR0_00_INT_ACK_ALL 0x7F000000
947#define DDR0_00_INT_ACK_ENCODE(n) ((((u32)(n))&0x7F)<<24)
948#define DDR0_00_INT_ACK_DECODE(n) ((((u32)(n))>>24)&0x7F)
949/* Status */
950#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */
951/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
952#define DDR0_00_INT_STATUS_BIT0 0x00010000
953/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
954#define DDR0_00_INT_STATUS_BIT1 0x00020000
955/* Bit2. Single correctable ECC event detected */
956#define DDR0_00_INT_STATUS_BIT2 0x00040000
957/* Bit3. Multiple correctable ECC events detected. */
958#define DDR0_00_INT_STATUS_BIT3 0x00080000
959/* Bit4. Single uncorrectable ECC event detected. */
960#define DDR0_00_INT_STATUS_BIT4 0x00100000
961/* Bit5. Multiple uncorrectable ECC events detected. */
962#define DDR0_00_INT_STATUS_BIT5 0x00200000
963/* Bit6. DRAM initialization complete. */
964#define DDR0_00_INT_STATUS_BIT6 0x00400000
965/* Bit7. Logical OR of all lower bits. */
966#define DDR0_00_INT_STATUS_BIT7 0x00800000
967
968#define DDR0_00_INT_STATUS_ENCODE(n) ((((u32)(n))&0xFF)<<16)
969#define DDR0_00_INT_STATUS_DECODE(n) ((((u32)(n))>>16)&0xFF)
970#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00
971#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((u32)(n))&0x7F)<<8)
972#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((u32)(n))>>8)&0x7F)
973#define DDR0_00_DLL_START_POINT_MASK 0x0000007F
974#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((u32)(n))&0x7F)<<0)
975#define DDR0_00_DLL_START_POINT_DECODE(n) ((((u32)(n))>>0)&0x7F)
976
977#define DDR0_01 0x01
978#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
979#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((u32)(n))&0x1F)<<24)
980#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((u32)(n))>>24)&0x1F)
981#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000
982#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((u32)(n))&0x1F)<<16)
983#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((u32)(n))>>16)&0x1F)
984#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */
985#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((u32)(n))&0x7)<<8)
986#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((u32)(n))>>8)&0x7)
987#define DDR0_01_INT_MASK_MASK 0x000000FF
988#define DDR0_01_INT_MASK_ENCODE(n) ((((u32)(n))&0xFF)<<0)
989#define DDR0_01_INT_MASK_DECODE(n) ((((u32)(n))>>0)&0xFF)
990#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
991#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
992
993#define DDR0_02 0x02
994#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */
995#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((u32)(n))&0x2)<<24)
996#define DDR0_02_MAX_CS_REG_DECODE(n) ((((u32)(n))>>24)&0x2)
997#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */
998#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((u32)(n))&0xF)<<16)
999#define DDR0_02_MAX_COL_REG_DECODE(n) ((((u32)(n))>>16)&0xF)
1000#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */
1001#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((u32)(n))&0xF)<<8)
1002#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((u32)(n))>>8)&0xF)
1003#define DDR0_02_START_MASK 0x00000001
1004#define DDR0_02_START_ENCODE(n) ((((u32)(n))&0x1)<<0)
1005#define DDR0_02_START_DECODE(n) ((((u32)(n))>>0)&0x1)
1006#define DDR0_02_START_OFF 0x00000000
1007#define DDR0_02_START_ON 0x00000001
1008
1009#define DDR0_03 0x03
1010#define DDR0_03_BSTLEN_MASK 0x07000000
1011#define DDR0_03_BSTLEN_ENCODE(n) ((((u32)(n))&0x7)<<24)
1012#define DDR0_03_BSTLEN_DECODE(n) ((((u32)(n))>>24)&0x7)
1013#define DDR0_03_CASLAT_MASK 0x00070000
1014#define DDR0_03_CASLAT_ENCODE(n) ((((u32)(n))&0x7)<<16)
1015#define DDR0_03_CASLAT_DECODE(n) ((((u32)(n))>>16)&0x7)
1016#define DDR0_03_CASLAT_LIN_MASK 0x00000F00
1017#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((u32)(n))&0xF)<<8)
1018#define DDR0_03_CASLAT_LIN_DECODE(n) ((((u32)(n))>>8)&0xF)
1019#define DDR0_03_INITAREF_MASK 0x0000000F
1020#define DDR0_03_INITAREF_ENCODE(n) ((((u32)(n))&0xF)<<0)
1021#define DDR0_03_INITAREF_DECODE(n) ((((u32)(n))>>0)&0xF)
1022
1023#define DDR0_04 0x04
1024#define DDR0_04_TRC_MASK 0x1F000000
1025#define DDR0_04_TRC_ENCODE(n) ((((u32)(n))&0x1F)<<24)
1026#define DDR0_04_TRC_DECODE(n) ((((u32)(n))>>24)&0x1F)
1027#define DDR0_04_TRRD_MASK 0x00070000
1028#define DDR0_04_TRRD_ENCODE(n) ((((u32)(n))&0x7)<<16)
1029#define DDR0_04_TRRD_DECODE(n) ((((u32)(n))>>16)&0x7)
1030#define DDR0_04_TRTP_MASK 0x00000700
1031#define DDR0_04_TRTP_ENCODE(n) ((((u32)(n))&0x7)<<8)
1032#define DDR0_04_TRTP_DECODE(n) ((((u32)(n))>>8)&0x7)
1033
1034#define DDR0_05 0x05
1035#define DDR0_05_TMRD_MASK 0x1F000000
1036#define DDR0_05_TMRD_ENCODE(n) ((((u32)(n))&0x1F)<<24)
1037#define DDR0_05_TMRD_DECODE(n) ((((u32)(n))>>24)&0x1F)
1038#define DDR0_05_TEMRS_MASK 0x00070000
1039#define DDR0_05_TEMRS_ENCODE(n) ((((u32)(n))&0x7)<<16)
1040#define DDR0_05_TEMRS_DECODE(n) ((((u32)(n))>>16)&0x7)
1041#define DDR0_05_TRP_MASK 0x00000F00
1042#define DDR0_05_TRP_ENCODE(n) ((((u32)(n))&0xF)<<8)
1043#define DDR0_05_TRP_DECODE(n) ((((u32)(n))>>8)&0xF)
1044#define DDR0_05_TRAS_MIN_MASK 0x000000FF
1045#define DDR0_05_TRAS_MIN_ENCODE(n) ((((u32)(n))&0xFF)<<0)
1046#define DDR0_05_TRAS_MIN_DECODE(n) ((((u32)(n))>>0)&0xFF)
1047
1048#define DDR0_06 0x06
1049#define DDR0_06_WRITEINTERP_MASK 0x01000000
1050#define DDR0_06_WRITEINTERP_ENCODE(n) ((((u32)(n))&0x1)<<24)
1051#define DDR0_06_WRITEINTERP_DECODE(n) ((((u32)(n))>>24)&0x1)
1052#define DDR0_06_TWTR_MASK 0x00070000
1053#define DDR0_06_TWTR_ENCODE(n) ((((u32)(n))&0x7)<<16)
1054#define DDR0_06_TWTR_DECODE(n) ((((u32)(n))>>16)&0x7)
1055#define DDR0_06_TDLL_MASK 0x0000FF00
1056#define DDR0_06_TDLL_ENCODE(n) ((((u32)(n))&0xFF)<<8)
1057#define DDR0_06_TDLL_DECODE(n) ((((u32)(n))>>8)&0xFF)
1058#define DDR0_06_TRFC_MASK 0x0000007F
1059#define DDR0_06_TRFC_ENCODE(n) ((((u32)(n))&0x7F)<<0)
1060#define DDR0_06_TRFC_DECODE(n) ((((u32)(n))>>0)&0x7F)
1061
1062#define DDR0_07 0x07
1063#define DDR0_07_NO_CMD_INIT_MASK 0x01000000
1064#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((u32)(n))&0x1)<<24)
1065#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((u32)(n))>>24)&0x1)
1066#define DDR0_07_TFAW_MASK 0x001F0000
1067#define DDR0_07_TFAW_ENCODE(n) ((((u32)(n))&0x1F)<<16)
1068#define DDR0_07_TFAW_DECODE(n) ((((u32)(n))>>16)&0x1F)
1069#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100
1070#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((u32)(n))&0x1)<<8)
1071#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((u32)(n))>>8)&0x1)
1072#define DDR0_07_AREFRESH_MASK 0x00000001
1073#define DDR0_07_AREFRESH_ENCODE(n) ((((u32)(n))&0x1)<<0)
1074#define DDR0_07_AREFRESH_DECODE(n) ((((u32)(n))>>0)&0x1)
1075
1076#define DDR0_08 0x08
1077#define DDR0_08_WRLAT_MASK 0x07000000
1078#define DDR0_08_WRLAT_ENCODE(n) ((((u32)(n))&0x7)<<24)
1079#define DDR0_08_WRLAT_DECODE(n) ((((u32)(n))>>24)&0x7)
1080#define DDR0_08_TCPD_MASK 0x00FF0000
1081#define DDR0_08_TCPD_ENCODE(n) ((((u32)(n))&0xFF)<<16)
1082#define DDR0_08_TCPD_DECODE(n) ((((u32)(n))>>16)&0xFF)
1083#define DDR0_08_DQS_N_EN_MASK 0x00000100
1084#define DDR0_08_DQS_N_EN_ENCODE(n) ((((u32)(n))&0x1)<<8)
1085#define DDR0_08_DQS_N_EN_DECODE(n) ((((u32)(n))>>8)&0x1)
1086#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001
1087#define DDR0_08_DDRII_ENCODE(n) ((((u32)(n))&0x1)<<0)
1088#define DDR0_08_DDRII_DECODE(n) ((((u32)(n))>>0)&0x1)
1089
1090#define DDR0_09 0x09
1091#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
1092#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((u32)(n))&0x1F)<<24)
1093#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((u32)(n))>>24)&0x1F)
1094#define DDR0_09_RTT_0_MASK 0x00030000
1095#define DDR0_09_RTT_0_ENCODE(n) ((((u32)(n))&0x3)<<16)
1096#define DDR0_09_RTT_0_DECODE(n) ((((u32)(n))>>16)&0x3)
1097#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00
1098#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((u32)(n))&0x7F)<<8)
1099#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((u32)(n))>>8)&0x7F)
1100#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F
1101#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((u32)(n))&0x7F)<<0)
1102#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((u32)(n))>>0)&0x7F)
1103
1104#define DDR0_10 0x0A
1105#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */
1106#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((u32)(n))&0x1)<<16)
1107#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((u32)(n))>>16)&0x1)
1108#define DDR0_10_CS_MAP_MASK 0x00000300
1109#define DDR0_10_CS_MAP_NO_MEM 0x00000000
1110#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100
1111#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200
1112#define DDR0_10_CS_MAP_ENCODE(n) ((((u32)(n))&0x3)<<8)
1113#define DDR0_10_CS_MAP_DECODE(n) ((((u32)(n))>>8)&0x3)
1114#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F
1115#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((u32)(n))&0x1F)<<0)
1116#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((u32)(n))>>0)&0x1F)
1117
1118#define DDR0_11 0x0B
1119#define DDR0_11_SREFRESH_MASK 0x01000000
1120#define DDR0_11_SREFRESH_ENCODE(n) ((((u32)(n))&0x1)<<24)
1121#define DDR0_11_SREFRESH_DECODE(n) ((((u32)(n))>>24)&0x1F)
1122#define DDR0_11_TXSNR_MASK 0x00FF0000
1123#define DDR0_11_TXSNR_ENCODE(n) ((((u32)(n))&0xFF)<<16)
1124#define DDR0_11_TXSNR_DECODE(n) ((((u32)(n))>>16)&0xFF)
1125#define DDR0_11_TXSR_MASK 0x0000FF00
1126#define DDR0_11_TXSR_ENCODE(n) ((((u32)(n))&0xFF)<<8)
1127#define DDR0_11_TXSR_DECODE(n) ((((u32)(n))>>8)&0xFF)
1128
1129#define DDR0_12 0x0C
1130#define DDR0_12_TCKE_MASK 0x0000007
1131#define DDR0_12_TCKE_ENCODE(n) ((((u32)(n))&0x7)<<0)
1132#define DDR0_12_TCKE_DECODE(n) ((((u32)(n))>>0)&0x7)
1133
1134#define DDR0_14 0x0E
1135#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000
1136#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((u32)(n))&0x1)<<24)
1137#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((u32)(n))>>24)&0x1)
1138#define DDR0_14_REDUC_MASK 0x00010000
1139#define DDR0_14_REDUC_64BITS 0x00000000
1140#define DDR0_14_REDUC_32BITS 0x00010000
1141#define DDR0_14_REDUC_ENCODE(n) ((((u32)(n))&0x1)<<16)
1142#define DDR0_14_REDUC_DECODE(n) ((((u32)(n))>>16)&0x1)
1143#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100
1144#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((u32)(n))&0x1)<<8)
1145#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((u32)(n))>>8)&0x1)
1146
1147#define DDR0_17 0x11
1148#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000
1149#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((u32)(n))&0x7F)<<24)
1150#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((u32)(n))>>24)&0x7F)
1151#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
1152#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
1153#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
1154#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((u32)(n))&0x1)<<16)
1155#define DDR0_17_DLLLOCKREG_DECODE(n) ((((u32)(n))>>16)&0x1)
1156#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */
1157#define DDR0_17_DLL_LOCK_ENCODE(n) ((((u32)(n))&0x7F)<<8)
1158#define DDR0_17_DLL_LOCK_DECODE(n) ((((u32)(n))>>8)&0x7F)
1159
1160#define DDR0_18 0x12
1161#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
1162#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000
1163#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((u32)(n))&0x7F)<<24)
1164#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((u32)(n))>>24)&0x7F)
1165#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000
1166#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((u32)(n))&0x7F)<<16)
1167#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((u32)(n))>>16)&0x7F)
1168#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00
1169#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((u32)(n))&0x7F)<<8)
1170#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((u32)(n))>>8)&0x7F)
1171#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F
1172#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((u32)(n))&0x7F)<<0)
1173#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((u32)(n))>>0)&0x7F)
1174
1175#define DDR0_19 0x13
1176#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
1177#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000
1178#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((u32)(n))&0x7F)<<24)
1179#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((u32)(n))>>24)&0x7F)
1180#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000
1181#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((u32)(n))&0x7F)<<16)
1182#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((u32)(n))>>16)&0x7F)
1183#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00
1184#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((u32)(n))&0x7F)<<8)
1185#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((u32)(n))>>8)&0x7F)
1186#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F
1187#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((u32)(n))&0x7F)<<0)
1188#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((u32)(n))>>0)&0x7F)
1189
1190#define DDR0_20 0x14
1191#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000
1192#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((u32)(n))&0x7F)<<24)
1193#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((u32)(n))>>24)&0x7F)
1194#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000
1195#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((u32)(n))&0x7F)<<16)
1196#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((u32)(n))>>16)&0x7F)
1197#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00
1198#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((u32)(n))&0x7F)<<8)
1199#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((u32)(n))>>8)&0x7F)
1200#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F
1201#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((u32)(n))&0x7F)<<0)
1202#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((u32)(n))>>0)&0x7F)
1203
1204#define DDR0_21 0x15
1205#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000
1206#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((u32)(n))&0x7F)<<24)
1207#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((u32)(n))>>24)&0x7F)
1208#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000
1209#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((u32)(n))&0x7F)<<16)
1210#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((u32)(n))>>16)&0x7F)
1211#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00
1212#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((u32)(n))&0x7F)<<8)
1213#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((u32)(n))>>8)&0x7F)
1214#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F
1215#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((u32)(n))&0x7F)<<0)
1216#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((u32)(n))>>0)&0x7F)
1217
1218#define DDR0_22 0x16
1219#define DDR0_22_CTRL_RAW_MASK 0x03000000
1220#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000
1221#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000
1222#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000
1223#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000
1224#define DDR0_22_CTRL_RAW_ENCODE(n) ((((u32)(n))&0x3)<<24)
1225#define DDR0_22_CTRL_RAW_DECODE(n) ((((u32)(n))>>24)&0x3)
1226#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
1227#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((u32)(n))&0x7F)<<16)
1228#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((u32)(n))>>16)&0x7F)
1229#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00
1230#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((u32)(n))&0x7F)<<8)
1231#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((u32)(n))>>8)&0x7F)
1232#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F
1233#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((u32)(n))&0x7F)<<0)
1234#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((u32)(n))>>0)&0x7F)
1235
1236#define DDR0_23 0x17
1237#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
1238#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((u32)(n))&0x3)<<24)
1239#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((u32)(n))>>24)&0x3)
1240#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */
1241#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((u32)(n))&0xFF)<<16)
1242#define DDR0_23_ECC_C_SYND_DECODE(n) ((((u32)(n))>>16)&0xFF)
1243#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */
1244#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((u32)(n))&0xFF)<<8)
1245#define DDR0_23_ECC_U_SYND_DECODE(n) ((((u32)(n))>>8)&0xFF)
1246#define DDR0_23_FWC_MASK 0x00000001 /* Write only */
1247#define DDR0_23_FWC_ENCODE(n) ((((u32)(n))&0x1)<<0)
1248#define DDR0_23_FWC_DECODE(n) ((((u32)(n))>>0)&0x1)
1249
1250#define DDR0_24 0x18
1251#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
1252#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((u32)(n))&0x3)<<24)
1253#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((u32)(n))>>24)&0x3)
1254#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000
1255#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((u32)(n))&0x3)<<16)
1256#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((u32)(n))>>16)&0x3)
1257#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300
1258#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((u32)(n))&0x3)<<8)
1259#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((u32)(n))>>8)&0x3)
1260#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003
1261#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((u32)(n))&0x3)<<0)
1262#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((u32)(n))>>0)&0x3)
1263
1264#define DDR0_25 0x19
1265#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */
1266#define DDR0_25_VERSION_ENCODE(n) ((((u32)(n))&0xFFFF)<<16)
1267#define DDR0_25_VERSION_DECODE(n) ((((u32)(n))>>16)&0xFFFF)
1268#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */
1269#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((u32)(n))&0x3FF)<<0)
1270#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((u32)(n))>>0)&0x3FF)
1271
1272#define DDR0_26 0x1A
1273#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000
1274#define DDR0_26_TRAS_MAX_ENCODE(n) ((((u32)(n))&0xFFFF)<<16)
1275#define DDR0_26_TRAS_MAX_DECODE(n) ((((u32)(n))>>16)&0xFFFF)
1276#define DDR0_26_TREF_MASK 0x00003FFF
1277#define DDR0_26_TREF_ENCODE(n) ((((u32)(n))&0x3FFF)<<0)
1278#define DDR0_26_TREF_DECODE(n) ((((u32)(n))>>0)&0x3FFF)
1279
1280#define DDR0_27 0x1B
1281#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
1282#define DDR0_27_EMRS_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<16)
1283#define DDR0_27_EMRS_DATA_DECODE(n) ((((u32)(n))>>16)&0x3FFF)
1284#define DDR0_27_TINIT_MASK 0x0000FFFF
1285#define DDR0_27_TINIT_ENCODE(n) ((((u32)(n))&0xFFFF)<<0)
1286#define DDR0_27_TINIT_DECODE(n) ((((u32)(n))>>0)&0xFFFF)
1287
1288#define DDR0_28 0x1C
1289#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000
1290#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<16)
1291#define DDR0_28_EMRS3_DATA_DECODE(n) ((((u32)(n))>>16)&0x3FFF)
1292#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF
1293#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<0)
1294#define DDR0_28_EMRS2_DATA_DECODE(n) ((((u32)(n))>>0)&0x3FFF)
1295
1296#define DDR0_31 0x1F
1297#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF
1298#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((u32)(n))&0xFFFF)<<0)
1299#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((u32)(n))>>0)&0xFFFF)
1300
1301#define DDR0_32 0x20
1302#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */
1303#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1304#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1305
1306#define DDR0_33 0x21
1307#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */
1308#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0)
1309#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1)
1310
1311#define DDR0_34 0x22
1312#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */
1313#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1314#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1315
1316#define DDR0_35 0x23
1317#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */
1318#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0)
1319#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1)
1320
1321#define DDR0_36 0x24
1322#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
1323#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1324#define DDR0_36_ECC_U_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1325
1326#define DDR0_37 0x25
1327#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
1328#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1329#define DDR0_37_ECC_U_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1330
1331#define DDR0_38 0x26
1332#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */
1333#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1334#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1335
1336#define DDR0_39 0x27
1337#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */
1338#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0)
1339#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1)
1340
1341#define DDR0_40 0x28
1342#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
1343#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1344#define DDR0_40_ECC_C_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1345
1346#define DDR0_41 0x29
1347#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
1348#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1349#define DDR0_41_ECC_C_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1350
1351#define DDR0_42 0x2A
1352#define DDR0_42_ADDR_PINS_MASK 0x07000000
1353#define DDR0_42_ADDR_PINS_ENCODE(n) ((((u32)(n))&0x7)<<24)
1354#define DDR0_42_ADDR_PINS_DECODE(n) ((((u32)(n))>>24)&0x7)
1355#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F
1356#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((u32)(n))&0xF)<<0)
1357#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((u32)(n))>>0)&0xF)
1358
1359#define DDR0_43 0x2B
1360#define DDR0_43_TWR_MASK 0x07000000
1361#define DDR0_43_TWR_ENCODE(n) ((((u32)(n))&0x7)<<24)
1362#define DDR0_43_TWR_DECODE(n) ((((u32)(n))>>24)&0x7)
1363#define DDR0_43_APREBIT_MASK 0x000F0000
1364#define DDR0_43_APREBIT_ENCODE(n) ((((u32)(n))&0xF)<<16)
1365#define DDR0_43_APREBIT_DECODE(n) ((((u32)(n))>>16)&0xF)
1366#define DDR0_43_COLUMN_SIZE_MASK 0x00000700
1367#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((u32)(n))&0x7)<<8)
1368#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((u32)(n))>>8)&0x7)
1369#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001
1370#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001
1371#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000
1372#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((u32)(n))&0x1)<<0)
1373#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((u32)(n))>>0)&0x1)
1374
1375#define DDR0_44 0x2C
1376#define DDR0_44_TRCD_MASK 0x000000FF
1377#define DDR0_44_TRCD_ENCODE(n) ((((u32)(n))&0xFF)<<0)
1378#define DDR0_44_TRCD_DECODE(n) ((((u32)(n))>>0)&0xFF)
1379
1380#endif /* CONFIG_SDRAM_PPC4xx_DENALI_DDR2 */
1381
Stefan Roese5ff88932008-09-08 14:11:12 +02001382#ifndef __ASSEMBLY__
Stefan Roese066003b2010-05-25 15:23:07 +02001383struct sdram_timing {
1384 u32 wrdtr;
1385 u32 clktr;
1386};
1387
Stefan Roese5ff88932008-09-08 14:11:12 +02001388/*
1389 * Prototypes
1390 */
Kim Phillipseef1cf22012-10-29 13:34:23 +00001391void ppc4xx_ibm_ddr2_register_dump(void);
Stefan Roese5ff88932008-09-08 14:11:12 +02001392u32 mfdcr_any(u32);
1393void mtdcr_any(u32, u32);
1394u32 ddr_wrdtr(u32);
1395u32 ddr_clktr(u32);
1396void spd_ddr_init_hang(void);
1397u32 DQS_autocalibration(void);
Stefan Roesefb951692009-09-28 17:33:45 +02001398phys_size_t sdram_memsize(void);
1399void dcbz_area(u32 start_address, u32 num_bytes);
Stefan Roese5ff88932008-09-08 14:11:12 +02001400#endif /* __ASSEMBLY__ */
1401
Stefan Roese17ceb062008-06-02 14:59:21 +02001402#endif /* _PPC4xx_SDRAM_H_ */