Pavel Machek | 35546f6 | 2016-06-07 12:37:23 +0200 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_SOCFPGA=y |
Pavel Machek | 35546f6 | 2016-06-07 12:37:23 +0200 | [diff] [blame] | 3 | CONFIG_TARGET_SOCFPGA_IS1=y |
| 4 | CONFIG_SPL_STACK_R_ADDR=0x00800000 |
| 5 | CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1" |
| 6 | CONFIG_SPL=y |
| 7 | CONFIG_SPL_STACK_R=y |
| 8 | CONFIG_FIT=y |
Heiko Schocher | 9dd1d0a | 2016-09-09 08:12:49 +0200 | [diff] [blame] | 9 | CONFIG_VERSION_VARIABLE=y |
Pavel Machek | 35546f6 | 2016-06-07 12:37:23 +0200 | [diff] [blame] | 10 | CONFIG_HUSH_PARSER=y |
| 11 | CONFIG_CMD_BOOTZ=y |
| 12 | # CONFIG_CMD_IMLS is not set |
| 13 | CONFIG_CMD_ASKENV=y |
| 14 | CONFIG_CMD_GREPENV=y |
Pavel Machek | 35546f6 | 2016-06-07 12:37:23 +0200 | [diff] [blame] | 15 | # CONFIG_CMD_FLASH is not set |
Pavel Machek | 35546f6 | 2016-06-07 12:37:23 +0200 | [diff] [blame] | 16 | CONFIG_CMD_SF=y |
| 17 | CONFIG_CMD_SPI=y |
| 18 | CONFIG_CMD_I2C=y |
| 19 | CONFIG_CMD_GPIO=y |
| 20 | CONFIG_CMD_DHCP=y |
| 21 | CONFIG_CMD_MII=y |
| 22 | CONFIG_CMD_PING=y |
| 23 | CONFIG_CMD_CACHE=y |
| 24 | CONFIG_CMD_TIME=y |
| 25 | CONFIG_CMD_EXT4=y |
| 26 | CONFIG_CMD_EXT4_WRITE=y |
| 27 | CONFIG_CMD_FAT=y |
| 28 | CONFIG_CMD_FS_GENERIC=y |
Tom Rini | aca5cd2 | 2016-09-08 16:11:59 -0400 | [diff] [blame] | 29 | CONFIG_SPL_DM=y |
Pavel Machek | 35546f6 | 2016-06-07 12:37:23 +0200 | [diff] [blame] | 30 | CONFIG_SPL_DM_SEQ_ALIAS=y |
Tom Rini | aca5cd2 | 2016-09-08 16:11:59 -0400 | [diff] [blame] | 31 | CONFIG_DM_GPIO=y |
Pavel Machek | 35546f6 | 2016-06-07 12:37:23 +0200 | [diff] [blame] | 32 | CONFIG_DWAPB_GPIO=y |
| 33 | CONFIG_SYS_I2C_DW=y |
| 34 | CONFIG_SPI_FLASH=y |
| 35 | CONFIG_SPI_FLASH_BAR=y |
| 36 | CONFIG_SPI_FLASH_STMICRO=y |
Pavel Machek | 35546f6 | 2016-06-07 12:37:23 +0200 | [diff] [blame] | 37 | CONFIG_DM_ETH=y |
| 38 | CONFIG_ETH_DESIGNWARE=y |
| 39 | CONFIG_SYS_NS16550=y |
| 40 | CONFIG_CADENCE_QSPI=y |