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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +09002/*
3 * board/renesas/alt/alt.c
4 *
Mitsuhiro Kimuracae72042015-03-04 15:57:03 +09005 * Copyright (C) 2014, 2015 Renesas Electronics Corporation
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +09006 */
7
8#include <common.h>
Simon Glass7b51b572019-08-01 09:46:52 -06009#include <env.h>
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090010#include <malloc.h>
Nobuhiro Iwamatsu9e116f62014-12-09 16:20:04 +090011#include <dm.h>
12#include <dm/platform_data/serial_sh.h>
Simon Glassf3998fd2019-08-02 09:44:25 -060013#include <env_internal.h>
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090014#include <asm/processor.h>
15#include <asm/mach-types.h>
16#include <asm/io.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090017#include <linux/errno.h>
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090018#include <asm/arch/sys_proto.h>
19#include <asm/gpio.h>
20#include <asm/arch/rmobile.h>
Nobuhiro Iwamatsu44e1eeb2014-12-02 16:52:19 +090021#include <asm/arch/rcar-mstp.h>
Nobuhiro Iwamatsu2b8c0812014-12-03 15:30:30 +090022#include <asm/arch/mmc.h>
Nobuhiro Iwamatsu25f96132014-11-19 14:26:33 +090023#include <asm/arch/sh_sdhi.h>
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090024#include <netdev.h>
25#include <miiphy.h>
26#include <i2c.h>
27#include <div64.h>
28#include "qos.h"
29
30DECLARE_GLOBAL_DATA_PTR;
31
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090032void s_init(void)
33{
34 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
35 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
36
37 /* Watchdog init */
38 writel(0xA5A5A500, &rwdt->rwtcsra);
39 writel(0xA5A5A500, &swdt->swtcsra);
40
41 /* QoS */
42 qos_init();
43}
44
Marek Vasutbb6d2ff2018-04-23 20:24:16 +020045#define TMU0_MSTP125 BIT(25)
46#define MMC0_MSTP315 BIT(15)
Nobuhiro Iwamatsu25f96132014-11-19 14:26:33 +090047
48#define SD1CKCR 0xE6150078
Marek Vasutbb6d2ff2018-04-23 20:24:16 +020049#define SD_97500KHZ 0x7
Nobuhiro Iwamatsu92ef38e2014-11-10 09:16:43 +090050
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090051int board_early_init_f(void)
52{
53 /* TMU */
54 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
55
Marek Vasutbb6d2ff2018-04-23 20:24:16 +020056 /* Set SD1 to the 97.5MHz */
57 writel(SD_97500KHZ, SD1CKCR);
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090058
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090059 return 0;
60}
61
Marek Vasutbb6d2ff2018-04-23 20:24:16 +020062#define ETHERNET_PHY_RESET 56 /* GPIO 1 24 */
63
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090064int board_init(void)
65{
66 /* adress of boot parameters */
Nobuhiro Iwamatsu47726842014-11-10 13:58:50 +090067 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090068
Marek Vasutbb6d2ff2018-04-23 20:24:16 +020069 /* Force ethernet PHY out of reset */
70 gpio_request(ETHERNET_PHY_RESET, "phy_reset");
71 gpio_direction_output(ETHERNET_PHY_RESET, 0);
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090072 mdelay(20);
Marek Vasutbb6d2ff2018-04-23 20:24:16 +020073 gpio_direction_output(ETHERNET_PHY_RESET, 1);
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090074 udelay(1);
75
76 return 0;
77}
78
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090079int dram_init(void)
80{
Siva Durga Prasad Paladugu12308b12018-07-16 15:56:11 +053081 if (fdtdec_setup_mem_size_base() != 0)
Marek Vasutbb6d2ff2018-04-23 20:24:16 +020082 return -EINVAL;
83
84 return 0;
85}
86
87int dram_init_banksize(void)
88{
89 fdtdec_setup_memory_banksize();
90
91 return 0;
92}
93
94/* KSZ8041RNLI */
95#define PHY_CONTROL1 0x1E
Marek Vasut4bbd4642019-03-30 07:05:09 +010096#define PHY_LED_MODE 0xC000
Marek Vasutbb6d2ff2018-04-23 20:24:16 +020097#define PHY_LED_MODE_ACK 0x4000
98int board_phy_config(struct phy_device *phydev)
99{
100 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
101 ret &= ~PHY_LED_MODE;
102 ret |= PHY_LED_MODE_ACK;
103 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +0900104
105 return 0;
106}
107
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +0900108void reset_cpu(ulong addr)
109{
Marek Vasutbb6d2ff2018-04-23 20:24:16 +0200110 struct udevice *dev;
Marek Vasut0c78ec62019-03-30 08:24:19 +0100111 const u8 pmic_bus = 7;
Marek Vasutbb6d2ff2018-04-23 20:24:16 +0200112 const u8 pmic_addr = 0x58;
113 u8 data;
114 int ret;
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +0900115
Marek Vasutbb6d2ff2018-04-23 20:24:16 +0200116 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
117 if (ret)
118 hang();
119
120 ret = dm_i2c_read(dev, 0x13, &data, 1);
121 if (ret)
122 hang();
123
124 data |= BIT(1);
125
126 ret = dm_i2c_write(dev, 0x13, &data, 1);
127 if (ret)
128 hang();
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +0900129}
Nobuhiro Iwamatsu9e116f62014-12-09 16:20:04 +0900130
Marek Vasutbb6d2ff2018-04-23 20:24:16 +0200131enum env_location env_get_location(enum env_operation op, int prio)
132{
133 const u32 load_magic = 0xb33fc0de;
Nobuhiro Iwamatsu9e116f62014-12-09 16:20:04 +0900134
Marek Vasutbb6d2ff2018-04-23 20:24:16 +0200135 /* Block environment access if loaded using JTAG */
136 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
137 (op != ENVOP_INIT))
138 return ENVL_UNKNOWN;
139
140 if (prio)
141 return ENVL_UNKNOWN;
142
143 return ENVL_SPI_FLASH;
144}