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Srinath915162d2011-04-18 17:40:35 -04001/*
2 * am3517_crane.h - Default configuration for AM3517 CraneBoard.
3 *
4 * Author: Srinath.R <srinath@mistralsolutions.com>
5 *
6 * Based on include/configs/am3517evm.h
7 *
8 * Copyright (C) 2011 Mistral Solutions pvt Ltd
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
Srinath915162d2011-04-18 17:40:35 -040011 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16/*
17 * High Level Configuration Options
18 */
Srinath915162d2011-04-18 17:40:35 -040019#define CONFIG_OMAP 1 /* in a TI OMAP core */
Srinath915162d2011-04-18 17:40:35 -040020#define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */
Nishanth Menonc6f90e12015-03-09 17:12:08 -050021/* Common ARM Erratas */
22#define CONFIG_ARM_ERRATA_454179
23#define CONFIG_ARM_ERRATA_430973
24#define CONFIG_ARM_ERRATA_621766
Srinath915162d2011-04-18 17:40:35 -040025
26#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
27
28#include <asm/arch/cpu.h> /* get chip and board defs */
Nishanth Menon987ec582015-03-09 17:12:04 -050029#include <asm/arch/omap.h>
Srinath915162d2011-04-18 17:40:35 -040030
Srinath915162d2011-04-18 17:40:35 -040031/* Clock Defines */
32#define V_OSCK 26000000 /* Clock output from T2 */
33#define V_SCLK (V_OSCK >> 1)
34
Srinath915162d2011-04-18 17:40:35 -040035#define CONFIG_MISC_INIT_R
36
37#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
38#define CONFIG_SETUP_MEMORY_TAGS 1
39#define CONFIG_INITRD_TAG 1
40#define CONFIG_REVISION_TAG 1
41
42/*
43 * Size of malloc() pool
44 */
45#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
46#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
47 /* initial data */
48/*
49 * DDR related
50 */
Srinath915162d2011-04-18 17:40:35 -040051#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
52
53/*
54 * Hardware drivers
55 */
56
57/*
58 * NS16550 Configuration
59 */
60#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
61
Srinath915162d2011-04-18 17:40:35 -040062#define CONFIG_SYS_NS16550_SERIAL
63#define CONFIG_SYS_NS16550_REG_SIZE (-4)
64#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
65
66/*
67 * select serial console configuration
68 */
69#define CONFIG_CONS_INDEX 3
70#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
71#define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */
72
73/* allow to overwrite serial and ethaddr */
74#define CONFIG_ENV_OVERWRITE
75#define CONFIG_BAUDRATE 115200
76#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
77 115200}
Srinath915162d2011-04-18 17:40:35 -040078
79/*
80 * USB configuration
Paul Kocialkowski95de1e22015-08-04 17:04:06 +020081 * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
82 * Enable CONFIG_USB_MUSB_UDC for Device functionalities.
Srinath915162d2011-04-18 17:40:35 -040083 */
84#define CONFIG_USB_AM35X 1
Paul Kocialkowski95de1e22015-08-04 17:04:06 +020085#define CONFIG_USB_MUSB_HCD 1
Srinath915162d2011-04-18 17:40:35 -040086
87#ifdef CONFIG_USB_AM35X
88
Paul Kocialkowski95de1e22015-08-04 17:04:06 +020089#ifdef CONFIG_USB_MUSB_HCD
Srinath915162d2011-04-18 17:40:35 -040090
Srinath915162d2011-04-18 17:40:35 -040091#define CONGIG_CMD_STORAGE
Srinath915162d2011-04-18 17:40:35 -040092
93#ifdef CONFIG_USB_KEYBOARD
94#define CONFIG_SYS_USB_EVENT_POLL
95#define CONFIG_PREBOOT "usb start"
96#endif /* CONFIG_USB_KEYBOARD */
97
Paul Kocialkowski95de1e22015-08-04 17:04:06 +020098#endif /* CONFIG_USB_MUSB_HCD */
Srinath915162d2011-04-18 17:40:35 -040099
Paul Kocialkowski95de1e22015-08-04 17:04:06 +0200100#ifdef CONFIG_USB_MUSB_UDC
Srinath915162d2011-04-18 17:40:35 -0400101/* USB device configuration */
102#define CONFIG_USB_DEVICE 1
103#define CONFIG_USB_TTY 1
Srinath915162d2011-04-18 17:40:35 -0400104/* Change these to suit your needs */
105#define CONFIG_USBD_VENDORID 0x0451
106#define CONFIG_USBD_PRODUCTID 0x5678
107#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
108#define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE"
Paul Kocialkowski95de1e22015-08-04 17:04:06 +0200109#endif /* CONFIG_USB_MUSB_UDC */
Srinath915162d2011-04-18 17:40:35 -0400110
111#endif /* CONFIG_USB_AM35X */
112
113/* commands to include */
Srinath915162d2011-04-18 17:40:35 -0400114#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
115
Srinath915162d2011-04-18 17:40:35 -0400116#define CONFIG_CMD_NAND /* NAND support */
Srinath915162d2011-04-18 17:40:35 -0400117
Srinath915162d2011-04-18 17:40:35 -0400118#define CONFIG_SYS_NO_FLASH
Heiko Schocher6789e842013-10-22 11:03:18 +0200119#define CONFIG_SYS_I2C
120#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
121#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
122#define CONFIG_SYS_I2C_OMAP34XX
Srinath915162d2011-04-18 17:40:35 -0400123
Srinath915162d2011-04-18 17:40:35 -0400124/*
125 * Board NAND Info.
126 */
127#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
128 /* to access nand */
129#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
130 /* to access */
131 /* nand at CS0 */
132
133#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
134 /* NAND devices */
Srinath915162d2011-04-18 17:40:35 -0400135
136#define CONFIG_JFFS2_NAND
137/* nand device jffs2 lives on */
138#define CONFIG_JFFS2_DEV "nand0"
139/* start of jffs2 partition */
140#define CONFIG_JFFS2_PART_OFFSET 0x680000
141#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
142
143/* Environment information */
Srinath915162d2011-04-18 17:40:35 -0400144
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000145#define CONFIG_BOOTFILE "uImage"
Srinath915162d2011-04-18 17:40:35 -0400146
147#define CONFIG_EXTRA_ENV_SETTINGS \
148 "loadaddr=0x82000000\0" \
149 "console=ttyS2,115200n8\0" \
Tom Rinia5a88212011-09-03 21:51:50 -0400150 "mmcdev=0\0" \
Srinath915162d2011-04-18 17:40:35 -0400151 "mmcargs=setenv bootargs console=${console} " \
152 "root=/dev/mmcblk0p2 rw " \
153 "rootfstype=ext3 rootwait\0" \
154 "nandargs=setenv bootargs console=${console} " \
155 "root=/dev/mtdblock4 rw " \
156 "rootfstype=jffs2\0" \
Tom Rinia5a88212011-09-03 21:51:50 -0400157 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
Srinath915162d2011-04-18 17:40:35 -0400158 "bootscript=echo Running bootscript from mmc ...; " \
159 "source ${loadaddr}\0" \
Tom Rinia5a88212011-09-03 21:51:50 -0400160 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
Srinath915162d2011-04-18 17:40:35 -0400161 "mmcboot=echo Booting from mmc ...; " \
162 "run mmcargs; " \
163 "bootm ${loadaddr}\0" \
164 "nandboot=echo Booting from nand ...; " \
165 "run nandargs; " \
166 "nand read ${loadaddr} 280000 400000; " \
167 "bootm ${loadaddr}\0" \
168
169#define CONFIG_BOOTCOMMAND \
Andrew Bradford66968112012-10-01 05:06:52 +0000170 "mmc dev ${mmcdev}; if mmc rescan; then " \
Srinath915162d2011-04-18 17:40:35 -0400171 "if run loadbootscript; then " \
172 "run bootscript; " \
173 "else " \
174 "if run loaduimage; then " \
175 "run mmcboot; " \
176 "else run nandboot; " \
177 "fi; " \
178 "fi; " \
179 "else run nandboot; fi"
180
181#define CONFIG_AUTO_COMPLETE 1
182/*
183 * Miscellaneous configurable options
184 */
Srinath915162d2011-04-18 17:40:35 -0400185#define CONFIG_SYS_LONGHELP /* undef to save memory */
Srinath915162d2011-04-18 17:40:35 -0400186#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
187/* Print Buffer Size */
188#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
189 sizeof(CONFIG_SYS_PROMPT) + 16)
190#define CONFIG_SYS_MAXARGS 32 /* max number of command */
191 /* args */
192/* Boot Argument Buffer Size */
193#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
194/* memtest works on */
195#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
196#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
197 0x01F00000) /* 31MB */
198
199#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
200 /* address */
201
202/*
203 * AM3517 has 12 GP timers, they can be driven by the system clock
204 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
205 * This rate is divided by a local divisor.
206 */
207#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
208#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
Srinath915162d2011-04-18 17:40:35 -0400209
210/*-----------------------------------------------------------------------
Srinath915162d2011-04-18 17:40:35 -0400211 * Physical Memory Map
212 */
213#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
214#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Srinath915162d2011-04-18 17:40:35 -0400215#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
216
Srinath915162d2011-04-18 17:40:35 -0400217/*-----------------------------------------------------------------------
218 * FLASH and environment organization
219 */
220
221/* **** PISMO SUPPORT *** */
Srinath915162d2011-04-18 17:40:35 -0400222#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
223 /* on one chip */
224#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
225#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
226
pekon gupta222a3112014-07-18 17:59:41 +0530227#define CONFIG_SYS_FLASH_BASE NAND_BASE
Srinath915162d2011-04-18 17:40:35 -0400228
229/* Monitor at start of flash */
230#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
231
232#define CONFIG_NAND_OMAP_GPMC
Srinath915162d2011-04-18 17:40:35 -0400233#define CONFIG_ENV_IS_IN_NAND 1
234#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
235
Luca Ceresoli6cbec7b2011-04-20 11:02:05 -0400236#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */
237#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
238#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
Srinath915162d2011-04-18 17:40:35 -0400239
240/*-----------------------------------------------------------------------
241 * CFI FLASH driver setup
242 */
243/* timeout values are in ticks */
244#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
245#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
246
247/* Flash banks JFFS2 should use */
248#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
249 CONFIG_SYS_MAX_NAND_DEVICE)
250#define CONFIG_SYS_JFFS2_MEM_NAND
251/* use flash_info[2] */
252#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
253#define CONFIG_SYS_JFFS2_NUM_BANKS 1
254
Srinath915162d2011-04-18 17:40:35 -0400255#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
256#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
257#define CONFIG_SYS_INIT_RAM_SIZE 0x800
258#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
259 CONFIG_SYS_INIT_RAM_SIZE - \
260 GENERATED_GBL_DATA_SIZE)
Tom Rinid067cc42011-11-18 12:48:11 +0000261
262/* Defines for SPL */
Tom Rini47f7bca2012-08-13 12:03:19 -0700263#define CONFIG_SPL_FRAMEWORK
Tom Rinid7cb93b2012-08-14 12:26:08 -0700264#define CONFIG_SPL_BOARD_INIT
Tom Rinid067cc42011-11-18 12:48:11 +0000265#define CONFIG_SPL_NAND_SIMPLE
266#define CONFIG_SPL_TEXT_BASE 0x40200800
Tom Rinifa2f81b2016-08-26 13:30:43 -0400267#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
268 CONFIG_SPL_TEXT_BASE)
Tom Rinid067cc42011-11-18 12:48:11 +0000269
270#define CONFIG_SPL_BSS_START_ADDR 0x80000000
271#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
272
Paul Kocialkowskie2ccdf82014-11-08 23:14:55 +0100273#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
Guillaume GARDET205b4f32014-10-15 17:53:11 +0200274#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Tom Rinid067cc42011-11-18 12:48:11 +0000275
Scott Wood6f2f01b2012-09-20 19:09:07 -0500276#define CONFIG_SPL_NAND_BASE
277#define CONFIG_SPL_NAND_DRIVERS
278#define CONFIG_SPL_NAND_ECC
Tom Rini983e3702016-11-07 21:34:54 -0500279#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
Tom Rinid067cc42011-11-18 12:48:11 +0000280
281/* NAND boot config */
Stefano Babic55f1b392015-07-26 15:18:15 +0200282#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
Tom Rinid067cc42011-11-18 12:48:11 +0000283#define CONFIG_SYS_NAND_5_ADDR_CYCLE
284#define CONFIG_SYS_NAND_PAGE_COUNT 64
285#define CONFIG_SYS_NAND_PAGE_SIZE 2048
286#define CONFIG_SYS_NAND_OOBSIZE 64
287#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
288#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
289#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
290 10, 11, 12, 13}
291#define CONFIG_SYS_NAND_ECCSIZE 512
292#define CONFIG_SYS_NAND_ECCBYTES 3
pekon gupta3f719062013-11-18 19:03:01 +0530293#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
Tom Rinid067cc42011-11-18 12:48:11 +0000294#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
295#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
296
297/*
298 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
299 * 64 bytes before this address should be set aside for u-boot.img's
300 * header. That is 0x800FFFC0--0x80100000 should not be used for any
301 * other needs.
302 */
303#define CONFIG_SYS_TEXT_BASE 0x80100000
304#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
305#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
306
Srinath915162d2011-04-18 17:40:35 -0400307#endif /* __CONFIG_H */