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Dirk Eibachb9944a72013-06-26 15:55:17 +02001/*
2 * (C) Copyright 2013
3 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
4 *
5 * based on P1022DS.h
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
Dirk Eibachb9944a72013-06-26 15:55:17 +020029#ifdef CONFIG_SDCARD
30#define CONFIG_RAMBOOT_SDCARD
31#endif
32
33#ifdef CONFIG_SPIFLASH
34#define CONFIG_RAMBOOT_SPIFLASH
35#endif
36
37/* High Level Configuration Options */
Dirk Eibachb9944a72013-06-26 15:55:17 +020038#define CONFIG_CONTROLCENTERD
39#define CONFIG_MP /* support multiple processors */
40
41#define CONFIG_SYS_NO_FLASH
42#define CONFIG_ENABLE_36BIT_PHYS
Dirk Eibachb9944a72013-06-26 15:55:17 +020043
Dirk Eibachb9944a72013-06-26 15:55:17 +020044#ifdef CONFIG_PHYS_64BIT
45#define CONFIG_ADDR_MAP
46#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
47#endif
48
49#define CONFIG_L2_CACHE
50#define CONFIG_BTB
51
52#define CONFIG_SYS_CLK_FREQ 66666600
53#define CONFIG_DDR_CLK_FREQ 66666600
54
55#define CONFIG_SYS_RAMBOOT
56
57#ifdef CONFIG_TRAILBLAZER
58
59#define CONFIG_SYS_TEXT_BASE 0xf8fc0000
60#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
61#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
62
63/*
64 * Config the L2 Cache
65 */
66#define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000
67#ifdef CONFIG_PHYS_64BIT
68#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull
69#else
70#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
71#endif
72#define CONFIG_SYS_L2_SIZE (256 << 10)
73#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
74
75#else /* CONFIG_TRAILBLAZER */
76
77#define CONFIG_SYS_TEXT_BASE 0x11000000
78#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
79#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
80
81#endif /* CONFIG_TRAILBLAZER */
82
83#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
84#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
85
Dirk Eibachb9944a72013-06-26 15:55:17 +020086/*
87 * Memory map
88 *
89 * 0x0000_0000 0x3fff_ffff DDR 1G Cacheable
90 * 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable
91 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
92 *
93 * Localbus non-cacheable
94 * 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable
95 * 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable
96 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
97 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
98 */
99
100#define CONFIG_SYS_INIT_RAM_LOCK
101#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
102#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* used area in RAM */
103#define CONFIG_SYS_GBL_DATA_OFFSET \
104 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
105#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
106
107#ifdef CONFIG_TRAILBLAZER
108/* leave CCSRBAR at default, because u-boot expects it to be exactly there */
109#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
110#else
111#define CONFIG_SYS_CCSRBAR 0xffe00000
112#endif
113#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
114#define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200)
115
116/*
117 * DDR Setup
118 */
119
120#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
121#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
122#define CONFIG_SYS_SDRAM_SIZE 1024
123#define CONFIG_VERY_BIG_RAM
124
Dirk Eibachb9944a72013-06-26 15:55:17 +0200125#define CONFIG_DIMM_SLOTS_PER_CTLR 1
126#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
127
128#define CONFIG_SYS_MEMTEST_START 0x00000000
129#define CONFIG_SYS_MEMTEST_END 0x3fffffff
130
131#ifdef CONFIG_TRAILBLAZER
132#define CONFIG_SPD_EEPROM
133#define SPD_EEPROM_ADDRESS 0x52
134/*#define CONFIG_FSL_DDR_INTERACTIVE*/
135#endif
136
137/*
138 * Local Bus Definitions
139 */
Dirk Eibachb9944a72013-06-26 15:55:17 +0200140
141#define CONFIG_SYS_ELBC_BASE 0xe0000000
142#ifdef CONFIG_PHYS_64BIT
143#define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull
144#else
145#define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE
146#endif
147
148#define CONFIG_UART_BR_PRELIM \
149 (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
150#define CONFIG_UART_OR_PRELIM (OR_AM_32KB | 0xff7)
151
152#define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */
153#define CONFIG_SYS_OR0_PRELIM 0 /* debugging, was never used */
154
155#define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM
156#define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM
157
158/*
159 * Serial Port
160 */
161#define CONFIG_CONS_INDEX 2
Dirk Eibachb9944a72013-06-26 15:55:17 +0200162#define CONFIG_SYS_NS16550_SERIAL
163#define CONFIG_SYS_NS16550_REG_SIZE 1
164#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
165
166#define CONFIG_SYS_BAUDRATE_TABLE \
167 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
168
169#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
170#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
171
172/*
173 * I2C
174 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200175#define CONFIG_SYS_I2C
176#define CONFIG_SYS_I2C_FSL
177#define CONFIG_SYS_FSL_I2C_SPEED 400000
178#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
179#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
180#define CONFIG_SYS_FSL_I2C2_SPEED 400000
181#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
182#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Dirk Eibach5568fb42014-07-03 09:28:21 +0200183
184#ifndef CONFIG_TRAILBLAZER
Dirk Eibach5568fb42014-07-03 09:28:21 +0200185#endif
Dirk Eibachb9944a72013-06-26 15:55:17 +0200186
187#define CONFIG_PCA9698 /* NXP PCA9698 */
188
189#define CONFIG_CMD_EEPROM
190#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
191#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
192
193#ifndef CONFIG_TRAILBLAZER
194/*
195 * eSPI - Enhanced SPI
196 */
197#define CONFIG_HARD_SPI
Dirk Eibachb9944a72013-06-26 15:55:17 +0200198
Dirk Eibachb9944a72013-06-26 15:55:17 +0200199#define CONFIG_SF_DEFAULT_SPEED 10000000
200#define CONFIG_SF_DEFAULT_MODE 0
201#endif
202
Dirk Eibachb9944a72013-06-26 15:55:17 +0200203#define CONFIG_SHA1
Dirk Eibachb9944a72013-06-26 15:55:17 +0200204
205/*
206 * MMC
207 */
Dirk Eibachb9944a72013-06-26 15:55:17 +0200208#define CONFIG_FSL_ESDHC
209#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
210
Dirk Eibachb9944a72013-06-26 15:55:17 +0200211#ifndef CONFIG_TRAILBLAZER
212
213/*
214 * Video
215 */
216#define CONFIG_FSL_DIU_FB
217#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
Dirk Eibachb9944a72013-06-26 15:55:17 +0200218#define CONFIG_CMD_BMP
219
220/*
221 * General PCI
222 * Memory space is mapped 1-1, but I/O space must start from 0.
223 */
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -0400224#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
Dirk Eibachb9944a72013-06-26 15:55:17 +0200225#define CONFIG_PCI_INDIRECT_BRIDGE
Dirk Eibachb9944a72013-06-26 15:55:17 +0200226#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
227#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
228#define CONFIG_CMD_PCI
229
230#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
231#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
232
233#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
234#ifdef CONFIG_PHYS_64BIT
235#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
236#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
237#else
238#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
239#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
240#endif
241#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
242#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
243#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
244#ifdef CONFIG_PHYS_64BIT
245#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
246#else
247#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
248#endif
249#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
250
251/*
252 * SATA
253 */
254#define CONFIG_LIBATA
255#define CONFIG_LBA48
256#define CONFIG_CMD_SATA
257
258#define CONFIG_FSL_SATA
259#define CONFIG_SYS_SATA_MAX_DEVICE 2
260#define CONFIG_SATA1
261#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
262#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
263#define CONFIG_SATA2
264#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
265#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
266
267/*
268 * Ethernet
269 */
270#define CONFIG_TSEC_ENET
271
272#define CONFIG_TSECV2
273
274#define CONFIG_MII /* MII PHY management */
275#define CONFIG_TSEC1 1
276#define CONFIG_TSEC1_NAME "eTSEC1"
277#define CONFIG_TSEC2 1
278#define CONFIG_TSEC2_NAME "eTSEC2"
279
280#define TSEC1_PHY_ADDR 0
281#define TSEC2_PHY_ADDR 1
282
283#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
284#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
285
286#define TSEC1_PHYIDX 0
287#define TSEC2_PHYIDX 0
288
289#define CONFIG_ETHPRIME "eTSEC1"
290
291#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
292
293/*
294 * USB
295 */
296#define CONFIG_USB_EHCI
Dirk Eibachb9944a72013-06-26 15:55:17 +0200297
298#define CONFIG_HAS_FSL_DR_USB
299#define CONFIG_USB_EHCI_FSL
300#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
301
302#endif /* CONFIG_TRAILBLAZER */
303
304/*
305 * Environment
306 */
307#if defined(CONFIG_TRAILBLAZER)
308#define CONFIG_ENV_IS_NOWHERE
309#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
Dirk Eibachb9944a72013-06-26 15:55:17 +0200310#elif defined(CONFIG_RAMBOOT_SPIFLASH)
311#define CONFIG_ENV_IS_IN_SPI_FLASH
312#define CONFIG_ENV_SPI_BUS 0
313#define CONFIG_ENV_SPI_CS 0
314#define CONFIG_ENV_SPI_MAX_HZ 10000000
315#define CONFIG_ENV_SPI_MODE 0
316#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
317#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
318#define CONFIG_ENV_SECT_SIZE 0x10000
319#elif defined(CONFIG_RAMBOOT_SDCARD)
320#define CONFIG_ENV_IS_IN_MMC
321#define CONFIG_FSL_FIXED_MMC_LOCATION
322#define CONFIG_ENV_SIZE 0x2000
323#define CONFIG_SYS_MMC_ENV_DEV 0
324#endif
325
326#define CONFIG_SYS_EXTRA_ENV_RELOC
327
Dirk Eibachb9944a72013-06-26 15:55:17 +0200328/*
329 * Command line configuration.
330 */
331#ifndef CONFIG_TRAILBLAZER
Dirk Eibachb9944a72013-06-26 15:55:17 +0200332#define CONFIG_SYS_LONGHELP
333#define CONFIG_CMDLINE_EDITING /* Command-line editing */
334#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
335#endif /* CONFIG_TRAILBLAZER */
336
337#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Dirk Eibachb9944a72013-06-26 15:55:17 +0200338#ifdef CONFIG_CMD_KGDB
339#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
340#else
341#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
342#endif
343/* Print Buffer Size */
344#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
345#define CONFIG_SYS_MAXARGS 16
346#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
347
Dirk Eibachb9944a72013-06-26 15:55:17 +0200348#ifndef CONFIG_TRAILBLAZER
349
Dirk Eibachb9944a72013-06-26 15:55:17 +0200350#define CONFIG_CMD_ERRATA
Dirk Eibachb9944a72013-06-26 15:55:17 +0200351#define CONFIG_CMD_IRQ
Dirk Eibachb9944a72013-06-26 15:55:17 +0200352#define CONFIG_CMD_REGINFO
353
354/*
355 * Board initialisation callbacks
356 */
Dirk Eibachb9944a72013-06-26 15:55:17 +0200357#define CONFIG_BOARD_EARLY_INIT_R
358#define CONFIG_MISC_INIT_R
359#define CONFIG_LAST_STAGE_INIT
360
Dirk Eibachb9944a72013-06-26 15:55:17 +0200361#else /* CONFIG_TRAILBLAZER */
362
Dirk Eibachb9944a72013-06-26 15:55:17 +0200363#define CONFIG_BOARD_EARLY_INIT_R
364#define CONFIG_LAST_STAGE_INIT
Dirk Eibachb9944a72013-06-26 15:55:17 +0200365
366#endif /* CONFIG_TRAILBLAZER */
367
368/*
369 * Miscellaneous configurable options
370 */
Dirk Eibachb9944a72013-06-26 15:55:17 +0200371#define CONFIG_HW_WATCHDOG
372#define CONFIG_LOADS_ECHO
373#define CONFIG_SYS_LOADS_BAUD_CHANGE
Dirk Eibachb9944a72013-06-26 15:55:17 +0200374
375/*
376 * For booting Linux, the board info and command line data
377 * have to be in the first 64 MB of memory, since this is
378 * the maximum mapped by the Linux kernel during initialization.
379 */
380#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Linux Memory map */
381#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
382
383/*
384 * Environment Configuration
385 */
386
387#ifdef CONFIG_TRAILBLAZER
388
Dirk Eibachb9944a72013-06-26 15:55:17 +0200389#define CONFIG_BAUDRATE 115200
390
391#define CONFIG_EXTRA_ENV_SETTINGS \
392 "mp_holdoff=1\0"
393
394#else
395
396#define CONFIG_HOSTNAME controlcenterd
397#define CONFIG_ROOTPATH "/opt/nfsroot"
398#define CONFIG_BOOTFILE "uImage"
399#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */
400
401#define CONFIG_LOADADDR 1000000
402
Dirk Eibachb9944a72013-06-26 15:55:17 +0200403
404#define CONFIG_BAUDRATE 115200
405
406#define CONFIG_EXTRA_ENV_SETTINGS \
407 "netdev=eth0\0" \
408 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
409 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
410 "tftpflash=tftpboot $loadaddr $uboot && " \
411 "protect off $ubootaddr +$filesize && " \
412 "erase $ubootaddr +$filesize && " \
413 "cp.b $loadaddr $ubootaddr $filesize && " \
414 "protect on $ubootaddr +$filesize && " \
415 "cmp.b $loadaddr $ubootaddr $filesize\0" \
416 "consoledev=ttyS1\0" \
417 "ramdiskaddr=2000000\0" \
418 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500419 "fdtaddr=1e00000\0" \
Dirk Eibachb9944a72013-06-26 15:55:17 +0200420 "fdtfile=controlcenterd.dtb\0" \
421 "bdev=sda3\0"
422
423/* these are used and NUL-terminated in env_default.h */
424#define CONFIG_NFSBOOTCOMMAND \
425 "setenv bootargs root=/dev/nfs rw " \
426 "nfsroot=$serverip:$rootpath " \
427 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
428 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
429 "tftp $loadaddr $bootfile;" \
430 "tftp $fdtaddr $fdtfile;" \
431 "bootm $loadaddr - $fdtaddr"
432
433#define CONFIG_RAMBOOTCOMMAND \
434 "setenv bootargs root=/dev/ram rw " \
435 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
436 "tftp $ramdiskaddr $ramdiskfile;" \
437 "tftp $loadaddr $bootfile;" \
438 "tftp $fdtaddr $fdtfile;" \
439 "bootm $loadaddr $ramdiskaddr $fdtaddr"
440
441#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
442
443#endif /* CONFIG_TRAILBLAZER */
444
445#endif