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Peter Korsgaarde3634262012-10-18 01:21:09 +00001/*
2 * board.h
3 *
4 * TI AM335x boards information header
5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Peter Korsgaarde3634262012-10-18 01:21:09 +00009 */
10
11#ifndef _BOARD_H_
12#define _BOARD_H_
13
Jyri Sarha8c17cbd2016-12-09 12:29:13 +020014/**
15 * AM335X (EMIF_4D) EMIF REG_COS_COUNT_1, REG_COS_COUNT_2, and
16 * REG_PR_OLD_COUNT values to avoid LCDC DMA FIFO underflows and Frame
17 * Synchronization Lost errors. The values are the biggest that work
18 * reliably with offered video modes and the memory subsystem on the
19 * boards. These register have are briefly documented in "7.3.3.5.2
20 * Command Starvation" section of AM335x TRM. The REG_COS_COUNT_1 and
21 * REG_COS_COUNT_2 do not have any effect on current versions of
22 * AM335x.
23 */
24#define EMIF_OCP_CONFIG_BEAGLEBONE_BLACK 0x00141414
25#define EMIF_OCP_CONFIG_AM335X_EVM 0x003d3d3d
26
Nishanth Menon770e68c2016-02-24 12:30:55 -060027static inline int board_is_bone(void)
Tom Riniace42752013-07-18 15:13:01 -040028{
Nishanth Menon770e68c2016-02-24 12:30:55 -060029 return board_ti_is("A335BONE");
Tom Riniace42752013-07-18 15:13:01 -040030}
31
Nishanth Menon770e68c2016-02-24 12:30:55 -060032static inline int board_is_bone_lt(void)
Tom Riniace42752013-07-18 15:13:01 -040033{
Nishanth Menon770e68c2016-02-24 12:30:55 -060034 return board_ti_is("A335BNLT");
Tom Riniace42752013-07-18 15:13:01 -040035}
36
Nishanth Menon770e68c2016-02-24 12:30:55 -060037static inline int board_is_bbg1(void)
Tom Riniace42752013-07-18 15:13:01 -040038{
Nishanth Menon770e68c2016-02-24 12:30:55 -060039 return board_is_bone_lt() && !strncmp(board_ti_get_rev(), "BBG1", 4);
Tom Riniace42752013-07-18 15:13:01 -040040}
41
Nishanth Menon770e68c2016-02-24 12:30:55 -060042static inline int board_is_evm_sk(void)
Tom Riniace42752013-07-18 15:13:01 -040043{
Nishanth Menon770e68c2016-02-24 12:30:55 -060044 return board_ti_is("A335X_SK");
Tom Riniace42752013-07-18 15:13:01 -040045}
46
Nishanth Menon770e68c2016-02-24 12:30:55 -060047static inline int board_is_idk(void)
Tom Riniace42752013-07-18 15:13:01 -040048{
Nishanth Menon770e68c2016-02-24 12:30:55 -060049 return !strncmp(board_ti_get_config(), "SKU#02", 6);
Tom Riniace42752013-07-18 15:13:01 -040050}
51
Nishanth Menon770e68c2016-02-24 12:30:55 -060052static inline int board_is_gp_evm(void)
Tom Riniace42752013-07-18 15:13:01 -040053{
Nishanth Menon770e68c2016-02-24 12:30:55 -060054 return board_ti_is("A33515BB");
55}
56
57static inline int board_is_evm_15_or_later(void)
58{
59 return (board_is_gp_evm() &&
60 strncmp("1.5", board_ti_get_rev(), 3) <= 0);
Tom Riniace42752013-07-18 15:13:01 -040061}
62
Lokesh Vutlaa9643322016-05-16 11:47:22 +053063static inline int board_is_icev2(void)
64{
65 return board_ti_is("A335_ICE") && !strncmp("2", board_ti_get_rev(), 1);
66}
67
Peter Korsgaarde3634262012-10-18 01:21:09 +000068/*
69 * We have three pin mux functions that must exist. We must be able to enable
70 * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
71 * main pinmux function that can be overridden to enable all other pinmux that
72 * is required on the board.
73 */
74void enable_uart0_pin_mux(void);
Andrew Bradford6422b702012-10-25 08:21:30 -040075void enable_uart1_pin_mux(void);
76void enable_uart2_pin_mux(void);
77void enable_uart3_pin_mux(void);
78void enable_uart4_pin_mux(void);
79void enable_uart5_pin_mux(void);
Peter Korsgaarde3634262012-10-18 01:21:09 +000080void enable_i2c0_pin_mux(void);
Nishanth Menon770e68c2016-02-24 12:30:55 -060081void enable_board_pin_mux(void);
Peter Korsgaarde3634262012-10-18 01:21:09 +000082#endif