blob: 23d87f682586ed0f21d12fa87492d2b7d458c268 [file] [log] [blame]
Wolfgang Denk9d407992006-07-10 23:07:28 +02001/*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenke2ffd592004-12-31 09:32:47 +00004 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denk9d407992006-07-10 23:07:28 +02006 ********************************************************************
7 *
8 * Lots of code copied from:
9 *
10 * i82365.c 1.352 - Linux driver for Intel 82365 and compatible
11 * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers.
12 * (C) 1999 David A. Hinds <dahinds@users.sourceforge.net>
wdenke2ffd592004-12-31 09:32:47 +000013 */
14
15#include <common.h>
wdenke2ffd592004-12-31 09:32:47 +000016
Wolfgang Denk9d407992006-07-10 23:07:28 +020017#ifdef CONFIG_I82365
18
19#include <command.h>
20#include <pci.h>
21#include <pcmcia.h>
22#include <asm/io.h>
23
24#include <pcmcia/ss.h>
25#include <pcmcia/i82365.h>
26#include <pcmcia/yenta.h>
27#include <pcmcia/cirrus.h>
wdenke2ffd592004-12-31 09:32:47 +000028
29static struct pci_device_id supported[] = {
30 {PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729},
Wolfgang Denk9d407992006-07-10 23:07:28 +020031 {0, 0}
wdenke2ffd592004-12-31 09:32:47 +000032};
33
Wolfgang Denk9d407992006-07-10 23:07:28 +020034#define CYCLE_TIME 120
wdenke2ffd592004-12-31 09:32:47 +000035
Wolfgang Denk9d407992006-07-10 23:07:28 +020036#ifdef DEBUG
37static void i82365_dump_regions (pci_dev_t dev);
38#endif
39
40typedef struct socket_info_t {
41 pci_dev_t dev;
42 u_short bcr;
43 u_char pci_lat, cb_lat, sub_bus, cache;
44 u_int cb_phys;
45
46 socket_cap_t cap;
47 u_short type;
48 u_int flags;
49 cirrus_state_t c_state;
50} socket_info_t;
51
52/* These definitions must match the pcic table! */
53typedef enum pcic_id {
54 IS_PD6710, IS_PD672X, IS_VT83C469
55} pcic_id;
56
57typedef struct pcic_t {
58 char *name;
59} pcic_t;
60
61static pcic_t pcic[] = {
62 {" Cirrus PD6710: "},
63 {" Cirrus PD672x: "},
64 {" VIA VT83C469: "},
65};
66
67static socket_info_t socket;
68static socket_state_t state;
69static struct pccard_mem_map mem;
70static struct pccard_io_map io;
71
72/*====================================================================*/
73
74/* Some PCI shortcuts */
75
76static int pci_readb (socket_info_t * s, int r, u_char * v)
wdenke2ffd592004-12-31 09:32:47 +000077{
Wolfgang Denk9d407992006-07-10 23:07:28 +020078 return pci_read_config_byte (s->dev, r, v);
79}
80static int pci_writeb (socket_info_t * s, int r, u_char v)
81{
82 return pci_write_config_byte (s->dev, r, v);
83}
84static int pci_readw (socket_info_t * s, int r, u_short * v)
85{
86 return pci_read_config_word (s->dev, r, v);
87}
88static int pci_writew (socket_info_t * s, int r, u_short v)
89{
90 return pci_write_config_word (s->dev, r, v);
91}
wdenke2ffd592004-12-31 09:32:47 +000092
Wolfgang Denk9d407992006-07-10 23:07:28 +020093/*====================================================================*/
94
95#define cb_readb(s) readb((s)->cb_phys + 1)
96#define cb_writeb(s, v) writeb(v, (s)->cb_phys)
97#define cb_writeb2(s, v) writeb(v, (s)->cb_phys + 1)
98#define cb_readl(s, r) readl((s)->cb_phys + (r))
99#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r))
100
101
102static u_char i365_get (socket_info_t * s, u_short reg)
103{
104 u_char val;
105#ifdef CONFIG_PCMCIA_SLOT_A
106 int slot = 0;
107#else
108 int slot = 1;
109#endif
110
111 val = I365_REG (slot, reg);
112
113 cb_writeb (s, val);
114 val = cb_readb (s);
115
116 debug ("i365_get slot:%x reg: %x val: %x\n", slot, reg, val);
117 return val;
118}
119
120static void i365_set (socket_info_t * s, u_short reg, u_char data)
121{
122#ifdef CONFIG_PCMCIA_SLOT_A
123 int slot = 0;
124#else
125 int slot = 1;
126#endif
127 u_char val;
128
129 val = I365_REG (slot, reg);
130
131 cb_writeb (s, val);
132 cb_writeb2 (s, data);
133
134 debug ("i365_set slot:%x reg: %x data:%x\n", slot, reg, data);
135}
136
137static void i365_bset (socket_info_t * s, u_short reg, u_char mask)
138{
139 i365_set (s, reg, i365_get (s, reg) | mask);
140}
141
142static void i365_bclr (socket_info_t * s, u_short reg, u_char mask)
143{
144 i365_set (s, reg, i365_get (s, reg) & ~mask);
145}
146
147#if 0 /* not used */
148static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b)
149{
150 u_char d = i365_get (s, reg);
151
152 i365_set (s, reg, (b) ? (d | mask) : (d & ~mask));
153}
154
155static u_short i365_get_pair (socket_info_t * s, u_short reg)
156{
157 return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8));
158}
159#endif /* not used */
160
161static void i365_set_pair (socket_info_t * s, u_short reg, u_short data)
162{
163 i365_set (s, reg, data & 0xff);
164 i365_set (s, reg + 1, data >> 8);
165}
166
167/*======================================================================
168
169 Code to save and restore global state information for Cirrus
170 PD67xx controllers, and to set and report global configuration
171 options.
172
173======================================================================*/
174
175#define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b))))
176
177static void cirrus_get_state (socket_info_t * s)
178{
179 int i;
180 cirrus_state_t *p = &s->c_state;
181
182 p->misc1 = i365_get (s, PD67_MISC_CTL_1);
183 p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
184 p->misc2 = i365_get (s, PD67_MISC_CTL_2);
185 for (i = 0; i < 6; i++)
186 p->timer[i] = i365_get (s, PD67_TIME_SETUP (0) + i);
187
188}
189
190static void cirrus_set_state (socket_info_t * s)
191{
192 int i;
193 u_char misc;
194 cirrus_state_t *p = &s->c_state;
195
196 misc = i365_get (s, PD67_MISC_CTL_2);
197 i365_set (s, PD67_MISC_CTL_2, p->misc2);
198 if (misc & PD67_MC2_SUSPEND)
199 udelay (50000);
200 misc = i365_get (s, PD67_MISC_CTL_1);
201 misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
202 i365_set (s, PD67_MISC_CTL_1, misc | p->misc1);
203 for (i = 0; i < 6; i++)
204 i365_set (s, PD67_TIME_SETUP (0) + i, p->timer[i]);
205}
206
207static u_int cirrus_set_opts (socket_info_t * s)
208{
209 cirrus_state_t *p = &s->c_state;
210 u_int mask = 0xffff;
Marek Vasut17f5f1e2011-10-21 14:17:31 +0000211 char buf[200] = {0};
Wolfgang Denk9d407992006-07-10 23:07:28 +0200212
213 if (has_ring == -1)
214 has_ring = 1;
215 flip (p->misc2, PD67_MC2_IRQ15_RI, has_ring);
216 flip (p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode);
217#if DEBUG
218 if (p->misc2 & PD67_MC2_IRQ15_RI)
219 strcat (buf, " [ring]");
220 if (p->misc2 & PD67_MC2_DYNAMIC_MODE)
221 strcat (buf, " [dyn mode]");
222 if (p->misc1 & PD67_MC1_INPACK_ENA)
223 strcat (buf, " [inpack]");
224#endif
225
226 if (p->misc2 & PD67_MC2_IRQ15_RI)
227 mask &= ~0x8000;
228 if (has_led > 0) {
229#if DEBUG
230 strcat (buf, " [led]");
231#endif
232 mask &= ~0x1000;
233 }
234 if (has_dma > 0) {
235#if DEBUG
236 strcat (buf, " [dma]");
237#endif
238 mask &= ~0x0600;
239 flip (p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass);
240#if DEBUG
241 if (p->misc2 & PD67_MC2_FREQ_BYPASS)
242 strcat (buf, " [freq bypass]");
243#endif
244 }
245
246 if (setup_time >= 0)
247 p->timer[0] = p->timer[3] = setup_time;
248 if (cmd_time > 0) {
249 p->timer[1] = cmd_time;
250 p->timer[4] = cmd_time * 2 + 4;
251 }
252 if (p->timer[1] == 0) {
253 p->timer[1] = 6;
254 p->timer[4] = 16;
255 if (p->timer[0] == 0)
256 p->timer[0] = p->timer[3] = 1;
257 }
258 if (recov_time >= 0)
259 p->timer[2] = p->timer[5] = recov_time;
260
261 debug ("i82365 Opt: %s [%d/%d/%d] [%d/%d/%d]\n",
262 buf,
263 p->timer[0], p->timer[1], p->timer[2],
264 p->timer[3], p->timer[4], p->timer[5]);
265
266 return mask;
267}
268
269/*======================================================================
270
271 Routines to handle common CardBus options
272
273======================================================================*/
274
275/* Default settings for PCI command configuration register */
276#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
277 PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
278
279static void cb_get_state (socket_info_t * s)
280{
281 pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache);
282 pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat);
283 pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat);
284 pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus);
285 pci_readb (s, CB_SUBORD_BUS, &s->sub_bus);
286 pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr);
287}
288
289static void cb_set_state (socket_info_t * s)
290{
291 pci_writew (s, PCI_COMMAND, CMD_DFLT);
292 pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache);
293 pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat);
294 pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat);
295 pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus);
296 pci_writeb (s, CB_SUBORD_BUS, s->sub_bus);
297 pci_writew (s, CB_BRIDGE_CONTROL, s->bcr);
298}
299
300static void cb_set_opts (socket_info_t * s)
301{
302}
303
304/*======================================================================
305
306 Power control for Cardbus controllers: used both for 16-bit and
307 Cardbus cards.
308
309======================================================================*/
310
311static int cb_set_power (socket_info_t * s, socket_state_t * state)
312{
313 u_int reg = 0;
314
315 reg = I365_PWR_NORESET;
316 if (state->flags & SS_PWR_AUTO)
317 reg |= I365_PWR_AUTO;
318 if (state->flags & SS_OUTPUT_ENA)
319 reg |= I365_PWR_OUT;
320 if (state->Vpp != 0) {
321 if (state->Vpp == 120) {
322 reg |= I365_VPP1_12V;
323 puts (" 12V card found: ");
324 } else if (state->Vpp == state->Vcc) {
325 reg |= I365_VPP1_5V;
326 } else {
327 puts (" power not found: ");
328 return -1;
329 }
330 }
331 if (state->Vcc != 0) {
332 reg |= I365_VCC_5V;
333 if (state->Vcc == 33) {
334 puts (" 3.3V card found: ");
335 i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
336 } else if (state->Vcc == 50) {
337 puts (" 5V card found: ");
338 i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
339 } else {
340 puts (" power not found: ");
341 return -1;
342 }
343 }
344
345 if (reg != i365_get (s, I365_POWER)) {
346 reg = (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V);
347 i365_set (s, I365_POWER, reg);
348 }
349
350 return 0;
351}
352
353/*======================================================================
354
355 Generic routines to get and set controller options
356
357======================================================================*/
358
359static void get_bridge_state (socket_info_t * s)
360{
361 cirrus_get_state (s);
362 cb_get_state (s);
363}
364
365static void set_bridge_state (socket_info_t * s)
366{
367 cb_set_state (s);
368 i365_set (s, I365_GBLCTL, 0x00);
369 i365_set (s, I365_GENCTL, 0x00);
370 cirrus_set_state (s);
371}
372
373static void set_bridge_opts (socket_info_t * s)
374{
375 cirrus_set_opts (s);
376 cb_set_opts (s);
377}
378
379/*====================================================================*/
380#define PD67_EXT_INDEX 0x2e /* Extension index */
381#define PD67_EXT_DATA 0x2f /* Extension data */
382#define PD67_EXD_VS1(s) (0x01 << ((s)<<1))
383
384#define pd67_ext_get(s, r) \
385 (i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA))
386
387static int i365_get_status (socket_info_t * s, u_int * value)
388{
389 u_int status;
390 u_char val;
391 u_char power, vcc, vpp;
392 u_int powerstate;
393
394 status = i365_get (s, I365_IDENT);
395 status = i365_get (s, I365_STATUS);
396 *value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
397 if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) {
398 *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
399 } else {
400 *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
401 *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
402 }
403 *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
404 *value |= (status & I365_CS_READY) ? SS_READY : 0;
405 *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
406
407 /* Check for Cirrus CL-PD67xx chips */
408 i365_set (s, PD67_CHIP_INFO, 0);
409 val = i365_get (s, PD67_CHIP_INFO);
410 s->type = -1;
411 if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) {
412 val = i365_get (s, PD67_CHIP_INFO);
413 if ((val & PD67_INFO_CHIP_ID) == 0) {
414 s->type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710;
415 i365_set (s, PD67_EXT_INDEX, 0xe5);
416 if (i365_get (s, PD67_EXT_INDEX) != 0xe5)
417 s->type = IS_VT83C469;
418 }
419 } else {
420 printf ("no Cirrus Chip found\n");
421 *value = 0;
wdenke2ffd592004-12-31 09:32:47 +0000422 return -1;
423 }
Wolfgang Denk9d407992006-07-10 23:07:28 +0200424
425 power = i365_get (s, I365_POWER);
426 state.flags |= (power & I365_PWR_AUTO) ? SS_PWR_AUTO : 0;
427 state.flags |= (power & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0;
428 vcc = power & I365_VCC_MASK;
429 vpp = power & I365_VPP1_MASK;
430 state.Vcc = state.Vpp = 0;
431 if((vcc== 0) || (vpp == 0)) {
432 /*
433 * On the Cirrus we get the info which card voltage
434 * we have in EXTERN DATA and write it to MISC_CTL1
435 */
436 powerstate = pd67_ext_get(s, PD67_EXTERN_DATA);
437 if (powerstate & PD67_EXD_VS1(0)) {
438 /* 5V Card */
439 i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
440 } else {
441 /* 3.3V Card */
442 i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
443 }
444 i365_set (s, I365_POWER, (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V));
445 power = i365_get (s, I365_POWER);
446 }
447 if (power & I365_VCC_5V) {
448 state.Vcc = (i365_get(s, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) ? 33 : 50;
449 }
450
451 if (power == I365_VPP1_12V)
452 state.Vpp = 120;
453
454 /* IO card, RESET flags, IO interrupt */
455 power = i365_get (s, I365_INTCTL);
456 state.flags |= (power & I365_PC_RESET) ? 0 : SS_RESET;
457 if (power & I365_PC_IOCARD)
458 state.flags |= SS_IOCARD;
459 state.io_irq = power & I365_IRQ_MASK;
460
461 /* Card status change mask */
462 power = i365_get (s, I365_CSCINT);
463 state.csc_mask = (power & I365_CSC_DETECT) ? SS_DETECT : 0;
464 if (state.flags & SS_IOCARD)
465 state.csc_mask |= (power & I365_CSC_STSCHG) ? SS_STSCHG : 0;
466 else {
467 state.csc_mask |= (power & I365_CSC_BVD1) ? SS_BATDEAD : 0;
468 state.csc_mask |= (power & I365_CSC_BVD2) ? SS_BATWARN : 0;
469 state.csc_mask |= (power & I365_CSC_READY) ? SS_READY : 0;
470 }
471 debug ("i82365: GetStatus(0) = flags %#3.3x, Vcc %d, Vpp %d, "
472 "io_irq %d, csc_mask %#2.2x\n", state.flags,
473 state.Vcc, state.Vpp, state.io_irq, state.csc_mask);
474
475 return 0;
476} /* i365_get_status */
477
478static int i365_set_socket (socket_info_t * s, socket_state_t * state)
479{
480 u_char reg;
481
482 set_bridge_state (s);
483
484 /* IO card, RESET flag */
485 reg = 0;
486 reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
487 reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
488 i365_set (s, I365_INTCTL, reg);
489
490 cb_set_power (s, state);
491
492#if 0
493 /* Card status change interrupt mask */
494 reg = s->cs_irq << 4;
495 if (state->csc_mask & SS_DETECT)
496 reg |= I365_CSC_DETECT;
497 if (state->flags & SS_IOCARD) {
498 if (state->csc_mask & SS_STSCHG)
499 reg |= I365_CSC_STSCHG;
500 } else {
501 if (state->csc_mask & SS_BATDEAD)
502 reg |= I365_CSC_BVD1;
503 if (state->csc_mask & SS_BATWARN)
504 reg |= I365_CSC_BVD2;
505 if (state->csc_mask & SS_READY)
506 reg |= I365_CSC_READY;
507 }
508 i365_set (s, I365_CSCINT, reg);
509 i365_get (s, I365_CSC);
510#endif /* 0 */
511
512 return 0;
513} /* i365_set_socket */
514
515/*====================================================================*/
516
517static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem)
518{
519 u_short base, i;
520 u_char map;
521
522 debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n",
523 mem->map, mem->flags, mem->speed,
524 mem->sys_start, mem->sys_stop, mem->card_start);
525
526 map = mem->map;
527 if ((map > 4) ||
528 (mem->card_start > 0x3ffffff) ||
529 (mem->sys_start > mem->sys_stop) ||
530 (mem->speed > 1000)) {
531 return -1;
532 }
533
534 /* Turn off the window before changing anything */
535 if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map))
536 i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map));
537
538 /* Take care of high byte, for PCI controllers */
539 i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24);
540
541 base = I365_MEM (map);
542 i = (mem->sys_start >> 12) & 0x0fff;
543 if (mem->flags & MAP_16BIT)
544 i |= I365_MEM_16BIT;
545 if (mem->flags & MAP_0WS)
546 i |= I365_MEM_0WS;
547 i365_set_pair (s, base + I365_W_START, i);
548
549 i = (mem->sys_stop >> 12) & 0x0fff;
550 switch (mem->speed / CYCLE_TIME) {
551 case 0:
552 break;
553 case 1:
554 i |= I365_MEM_WS0;
555 break;
556 case 2:
557 i |= I365_MEM_WS1;
558 break;
559 default:
560 i |= I365_MEM_WS1 | I365_MEM_WS0;
561 break;
562 }
563 i365_set_pair (s, base + I365_W_STOP, i);
564
565 i = 0;
566 if (mem->flags & MAP_WRPROT)
567 i |= I365_MEM_WRPROT;
568 if (mem->flags & MAP_ATTRIB)
569 i |= I365_MEM_REG;
570 i365_set_pair (s, base + I365_W_OFF, i);
571
572 /* set System Memory map Upper Adress */
573 i365_set(s, PD67_EXT_INDEX, PD67_MEM_PAGE(map));
574 i365_set(s, PD67_EXT_DATA, ((mem->sys_start >> 24) & 0xff));
575
576 /* Turn on the window if necessary */
577 if (mem->flags & MAP_ACTIVE)
578 i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map));
579 return 0;
580} /* i365_set_mem_map */
581
582static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io)
583{
584 u_char map, ioctl;
585
586 map = io->map;
587 /* comment out: comparison is always false due to limited range of data type */
588 if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */
589 (io->stop < io->start))
590 return -1;
591 /* Turn off the window before changing anything */
592 if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map))
593 i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map));
594 i365_set_pair (s, I365_IO (map) + I365_W_START, io->start);
595 i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop);
596 ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map);
597 if (io->speed)
598 ioctl |= I365_IOCTL_WAIT (map);
599 if (io->flags & MAP_0WS)
600 ioctl |= I365_IOCTL_0WS (map);
601 if (io->flags & MAP_16BIT)
602 ioctl |= I365_IOCTL_16BIT (map);
603 if (io->flags & MAP_AUTOSZ)
604 ioctl |= I365_IOCTL_IOCS16 (map);
605 i365_set (s, I365_IOCTL, ioctl);
606 /* Turn on the window if necessary */
607 if (io->flags & MAP_ACTIVE)
608 i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map));
609 return 0;
610} /* i365_set_io_map */
611
612/*====================================================================*/
613
614/*
615 * PCI_ADDR = (HOST_ADDR - 0xfe000000)
616 * see MPC 8245 Users Manual Adress Map B
617 */
618#define HOST_TO_PCI(addr) ((addr) - 0xfe000000)
619#define PCI_TO_HOST(addr) ((addr) + 0xfe000000)
620
Wolfgang Denkde550d62010-11-23 23:48:56 +0100621static int i82365_init (void)
Wolfgang Denk9d407992006-07-10 23:07:28 +0200622{
623 u_int val;
624 int i;
625
626 if ((socket.dev = pci_find_devices (supported, 0)) < 0) {
627 /* Controller not found */
628 printf ("No PD67290 device found !!\n");
629 return 1;
630 }
631 debug ("i82365 Device Found!\n");
632
633 socket.cb_phys = PCMCIA_IO_BASE;
wdenke2ffd592004-12-31 09:32:47 +0000634
635 /* set base address */
Wolfgang Denk9d407992006-07-10 23:07:28 +0200636 pci_write_config_dword (socket.dev, PCI_BASE_ADDRESS_0,
637 HOST_TO_PCI(socket.cb_phys));
wdenke2ffd592004-12-31 09:32:47 +0000638
639 /* enable mapped memory and IO addresses */
Wolfgang Denk9d407992006-07-10 23:07:28 +0200640 pci_write_config_dword (socket.dev,
wdenke2ffd592004-12-31 09:32:47 +0000641 PCI_COMMAND,
642 PCI_COMMAND_MEMORY |
643 PCI_COMMAND_IO | PCI_COMMAND_WAIT);
Wolfgang Denk9d407992006-07-10 23:07:28 +0200644
645 get_bridge_state (&socket);
646 set_bridge_opts (&socket);
647
648 i = i365_get_status (&socket, &val);
649
650 if (i > -1) {
651 puts (pcic[socket.type].name);
652 } else {
653 printf ("i82365: Controller not found.\n");
654 return 1;
655 }
656 if((val & SS_DETECT) != SS_DETECT){
657 puts ("No card\n");
658 return 1;
659 }
660
661 state.flags |= SS_OUTPUT_ENA;
662
663 i365_set_socket (&socket, &state);
664
665 for (i = 500; i; i--) {
666 if ((i365_get (&socket, I365_STATUS) & I365_CS_READY))
667 break;
668 udelay (1000);
669 }
670
671 if (i == 0) {
672 /* PC Card not ready for data transfer */
673 puts ("i82365 PC Card not ready for data transfer\n");
674 return 1;
675 }
676 debug (" PC Card ready for data transfer: ");
677
678 mem.map = 0;
679 mem.flags = MAP_ATTRIB | MAP_ACTIVE;
680 mem.speed = 300;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200681 mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR;
682 mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE - 1;
Wolfgang Denk9d407992006-07-10 23:07:28 +0200683 mem.card_start = 0;
684 i365_set_mem_map (&socket, &mem);
685
686 mem.map = 1;
687 mem.flags = MAP_ACTIVE;
688 mem.speed = 300;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200689 mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE;
690 mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + (2 * CONFIG_SYS_PCMCIA_MEM_SIZE) - 1;
Wolfgang Denk9d407992006-07-10 23:07:28 +0200691 mem.card_start = 0;
692 i365_set_mem_map (&socket, &mem);
693
694#ifdef DEBUG
695 i82365_dump_regions (socket.dev);
696#endif
697
wdenke2ffd592004-12-31 09:32:47 +0000698 return 0;
699}
Wolfgang Denk9d407992006-07-10 23:07:28 +0200700
Wolfgang Denkde550d62010-11-23 23:48:56 +0100701static void i82365_exit (void)
Wolfgang Denk9d407992006-07-10 23:07:28 +0200702{
703 io.map = 0;
704 io.flags = 0;
705 io.speed = 0;
706 io.start = 0;
707 io.stop = 0x1;
708
709 i365_set_io_map (&socket, &io);
710
711 mem.map = 0;
712 mem.flags = 0;
713 mem.speed = 0;
714 mem.sys_start = 0;
715 mem.sys_stop = 0x1000;
716 mem.card_start = 0;
717
718 i365_set_mem_map (&socket, &mem);
719
720 mem.map = 1;
721 mem.flags = 0;
722 mem.speed = 0;
723 mem.sys_start = 0;
724 mem.sys_stop = 0x1000;
725 mem.card_start = 0;
726
727 i365_set_mem_map (&socket, &mem);
728
729 state.Vcc = state.Vpp = 0;
730
731 i365_set_socket (&socket, &state);
732}
733
734int pcmcia_on (void)
735{
736 u_int rc;
737
738 debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
739
740 rc = i82365_init();
741 if (rc)
742 goto exit;
743
744 rc = check_ide_device(0);
745 if (rc == 0)
746 goto exit;
747
748 i82365_exit();
749
750exit:
751 return rc;
752}
753
Jon Loeligerfcec2eb2007-07-09 18:19:09 -0500754#if defined(CONFIG_CMD_PCMCIA)
Wolfgang Denk9d407992006-07-10 23:07:28 +0200755int pcmcia_off (void)
756{
757 printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
758
759 i82365_exit();
760
761 return 0;
762}
763#endif
764
765/*======================================================================
766
767 Debug stuff
768
769======================================================================*/
770
771#ifdef DEBUG
772static void i82365_dump_regions (pci_dev_t dev)
773{
774 u_int tmp[2];
775 u_int *mem = (void *) socket.cb_phys;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200776 u_char *cis = (void *) CONFIG_SYS_PCMCIA_MEM_ADDR;
777 u_char *ide = (void *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_REG_OFFSET);
Wolfgang Denk9d407992006-07-10 23:07:28 +0200778
779 pci_read_config_dword (dev, 0x00, tmp + 0);
780 pci_read_config_dword (dev, 0x80, tmp + 1);
781
782 printf ("PCI CONF: %08X ... %08X\n",
783 tmp[0], tmp[1]);
784 printf ("PCI MEM: ... %08X ... %08X\n",
785 mem[0x8 / 4], mem[0x800 / 4]);
786 printf ("CIS: ...%c%c%c%c%c%c%c%c...\n",
787 cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e],
788 cis[0x40], cis[0x42], cis[0x44], cis[0x48]);
789 printf ("CIS CONF: %02X %02X %02X ...\n",
790 cis[0x200], cis[0x202], cis[0x204]);
791 printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n",
792 ide[0], ide[1], ide[2], ide[3],
793 ide[4], ide[5], ide[6], ide[7]);
794}
795#endif /* DEBUG */
796
797#endif /* CONFIG_I82365 */