Dave Gerlach | a8c13c7 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Texas Instruments' K3 DDRSS driver |
| 4 | * |
| 5 | * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/ |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <clk.h> |
| 10 | #include <dm.h> |
| 11 | #include <dm/device_compat.h> |
| 12 | #include <ram.h> |
| 13 | #include <hang.h> |
| 14 | #include <log.h> |
| 15 | #include <asm/io.h> |
| 16 | #include <power-domain.h> |
| 17 | #include <wait_bit.h> |
| 18 | |
| 19 | #include "lpddr4_obj_if.h" |
| 20 | #include "lpddr4_if.h" |
| 21 | #include "lpddr4_structs_if.h" |
| 22 | #include "lpddr4_ctl_regs.h" |
| 23 | |
| 24 | #define SRAM_MAX 512 |
| 25 | |
| 26 | #define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS 0x80 |
| 27 | #define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS 0xc0 |
| 28 | |
Dave Gerlach | 9f9b5c1 | 2021-05-11 10:22:12 -0500 | [diff] [blame^] | 29 | #define DDRSS_V2A_R1_MAT_REG 0x0020 |
| 30 | #define DDRSS_ECC_CTRL_REG 0x0120 |
| 31 | |
Dave Gerlach | a8c13c7 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 32 | struct k3_ddrss_desc { |
| 33 | struct udevice *dev; |
| 34 | void __iomem *ddrss_ss_cfg; |
| 35 | void __iomem *ddrss_ctrl_mmr; |
| 36 | struct power_domain ddrcfg_pwrdmn; |
| 37 | struct power_domain ddrdata_pwrdmn; |
| 38 | struct clk ddr_clk; |
| 39 | struct clk osc_clk; |
| 40 | u32 ddr_freq1; |
| 41 | u32 ddr_freq2; |
| 42 | u32 ddr_fhs_cnt; |
| 43 | }; |
| 44 | |
| 45 | static lpddr4_obj *driverdt; |
| 46 | static lpddr4_config config; |
| 47 | static lpddr4_privatedata pd; |
| 48 | |
| 49 | static struct k3_ddrss_desc *ddrss; |
| 50 | |
| 51 | struct reginitdata { |
| 52 | u32 ctl_regs[LPDDR4_INTR_CTL_REG_COUNT]; |
| 53 | u16 ctl_regs_offs[LPDDR4_INTR_CTL_REG_COUNT]; |
| 54 | u32 pi_regs[LPDDR4_INTR_PHY_INDEP_REG_COUNT]; |
| 55 | u16 pi_regs_offs[LPDDR4_INTR_PHY_INDEP_REG_COUNT]; |
| 56 | u32 phy_regs[LPDDR4_INTR_PHY_REG_COUNT]; |
| 57 | u16 phy_regs_offs[LPDDR4_INTR_PHY_REG_COUNT]; |
| 58 | }; |
| 59 | |
| 60 | #define TH_MACRO_EXP(fld, str) (fld##str) |
| 61 | |
| 62 | #define TH_FLD_MASK(fld) TH_MACRO_EXP(fld, _MASK) |
| 63 | #define TH_FLD_SHIFT(fld) TH_MACRO_EXP(fld, _SHIFT) |
| 64 | #define TH_FLD_WIDTH(fld) TH_MACRO_EXP(fld, _WIDTH) |
| 65 | #define TH_FLD_WOCLR(fld) TH_MACRO_EXP(fld, _WOCLR) |
| 66 | #define TH_FLD_WOSET(fld) TH_MACRO_EXP(fld, _WOSET) |
| 67 | |
| 68 | #define str(s) #s |
| 69 | #define xstr(s) str(s) |
| 70 | |
| 71 | #define CTL_SHIFT 11 |
| 72 | #define PHY_SHIFT 11 |
| 73 | #define PI_SHIFT 10 |
| 74 | |
| 75 | #define DENALI_CTL_0_DRAM_CLASS_DDR4 0xA |
| 76 | #define DENALI_CTL_0_DRAM_CLASS_LPDDR4 0xB |
| 77 | |
| 78 | #define TH_OFFSET_FROM_REG(REG, SHIFT, offset) do {\ |
| 79 | char *i, *pstr = xstr(REG); offset = 0;\ |
| 80 | for (i = &pstr[SHIFT]; *i != '\0'; ++i) {\ |
| 81 | offset = offset * 10 + (*i - '0'); } \ |
| 82 | } while (0) |
| 83 | |
| 84 | static u32 k3_lpddr4_read_ddr_type(void) |
| 85 | { |
| 86 | u32 status = 0U; |
| 87 | u32 offset = 0U; |
| 88 | u32 regval = 0U; |
| 89 | u32 dram_class = 0U; |
| 90 | |
| 91 | TH_OFFSET_FROM_REG(LPDDR4__DRAM_CLASS__REG, CTL_SHIFT, offset); |
| 92 | status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val); |
| 93 | if (status > 0U) { |
| 94 | printf("%s: Failed to read DRAM_CLASS\n", __func__); |
| 95 | hang(); |
| 96 | } |
| 97 | |
| 98 | dram_class = ((regval & TH_FLD_MASK(LPDDR4__DRAM_CLASS__FLD)) >> |
| 99 | TH_FLD_SHIFT(LPDDR4__DRAM_CLASS__FLD)); |
| 100 | return dram_class; |
| 101 | } |
| 102 | |
| 103 | static void k3_lpddr4_freq_update(void) |
| 104 | { |
| 105 | unsigned int req_type, counter; |
| 106 | |
| 107 | for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) { |
| 108 | if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr + |
| 109 | CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80, |
| 110 | true, 10000, false)) { |
| 111 | printf("Timeout during frequency handshake\n"); |
| 112 | hang(); |
| 113 | } |
| 114 | |
| 115 | req_type = readl(ddrss->ddrss_ctrl_mmr + |
| 116 | CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS) & 0x03; |
| 117 | |
| 118 | debug("%s: received freq change req: req type = %d, req no. = %d\n", |
| 119 | __func__, req_type, counter); |
| 120 | |
| 121 | if (req_type == 1) |
| 122 | clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1); |
| 123 | else if (req_type == 2) |
| 124 | clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq2); |
| 125 | else if (req_type == 0) |
| 126 | /* Put DDR pll in bypass mode */ |
| 127 | clk_set_rate(&ddrss->ddr_clk, |
| 128 | clk_get_rate(&ddrss->osc_clk)); |
| 129 | else |
| 130 | printf("%s: Invalid freq request type\n", __func__); |
| 131 | |
| 132 | writel(0x1, ddrss->ddrss_ctrl_mmr + |
| 133 | CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS); |
| 134 | if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr + |
| 135 | CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80, |
| 136 | false, 10, false)) { |
| 137 | printf("Timeout during frequency handshake\n"); |
| 138 | hang(); |
| 139 | } |
| 140 | writel(0x0, ddrss->ddrss_ctrl_mmr + |
| 141 | CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS); |
| 142 | } |
| 143 | } |
| 144 | |
| 145 | static void k3_lpddr4_ack_freq_upd_req(void) |
| 146 | { |
| 147 | u32 dram_class; |
| 148 | |
| 149 | debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n"); |
| 150 | |
| 151 | dram_class = k3_lpddr4_read_ddr_type(); |
| 152 | |
| 153 | switch (dram_class) { |
| 154 | case DENALI_CTL_0_DRAM_CLASS_DDR4: |
| 155 | break; |
| 156 | case DENALI_CTL_0_DRAM_CLASS_LPDDR4: |
| 157 | k3_lpddr4_freq_update(); |
| 158 | break; |
| 159 | default: |
| 160 | printf("Unrecognized dram_class cannot update frequency!\n"); |
| 161 | } |
| 162 | } |
| 163 | |
| 164 | static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss) |
| 165 | { |
| 166 | u32 dram_class; |
| 167 | int ret; |
| 168 | |
| 169 | dram_class = k3_lpddr4_read_ddr_type(); |
| 170 | |
| 171 | switch (dram_class) { |
| 172 | case DENALI_CTL_0_DRAM_CLASS_DDR4: |
| 173 | /* Set to ddr_freq1 from DT for DDR4 */ |
| 174 | ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1); |
| 175 | break; |
| 176 | case DENALI_CTL_0_DRAM_CLASS_LPDDR4: |
| 177 | /* Set to bypass frequency for LPDDR4*/ |
| 178 | ret = clk_set_rate(&ddrss->ddr_clk, clk_get_rate(&ddrss->osc_clk)); |
| 179 | break; |
| 180 | default: |
| 181 | ret = -EINVAL; |
| 182 | printf("Unrecognized dram_class cannot init frequency!\n"); |
| 183 | } |
| 184 | |
| 185 | if (ret < 0) |
| 186 | dev_err(ddrss->dev, "ddr clk init failed: %d\n", ret); |
| 187 | else |
| 188 | ret = 0; |
| 189 | |
| 190 | return ret; |
| 191 | } |
| 192 | |
| 193 | static void k3_lpddr4_info_handler(const lpddr4_privatedata *pd, |
| 194 | lpddr4_infotype infotype) |
| 195 | { |
| 196 | if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE) |
| 197 | k3_lpddr4_ack_freq_upd_req(); |
| 198 | } |
| 199 | |
| 200 | static int k3_ddrss_power_on(struct k3_ddrss_desc *ddrss) |
| 201 | { |
| 202 | int ret; |
| 203 | |
| 204 | debug("%s(ddrss=%p)\n", __func__, ddrss); |
| 205 | |
| 206 | ret = power_domain_on(&ddrss->ddrcfg_pwrdmn); |
| 207 | if (ret) { |
| 208 | dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret); |
| 209 | return ret; |
| 210 | } |
| 211 | |
| 212 | ret = power_domain_on(&ddrss->ddrdata_pwrdmn); |
| 213 | if (ret) { |
| 214 | dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret); |
| 215 | return ret; |
| 216 | } |
| 217 | |
| 218 | return 0; |
| 219 | } |
| 220 | |
| 221 | static int k3_ddrss_ofdata_to_priv(struct udevice *dev) |
| 222 | { |
| 223 | struct k3_ddrss_desc *ddrss = dev_get_priv(dev); |
| 224 | phys_addr_t reg; |
| 225 | int ret; |
| 226 | |
| 227 | debug("%s(dev=%p)\n", __func__, dev); |
| 228 | |
| 229 | reg = dev_read_addr_name(dev, "cfg"); |
| 230 | if (reg == FDT_ADDR_T_NONE) { |
| 231 | dev_err(dev, "No reg property for DDRSS wrapper logic\n"); |
| 232 | return -EINVAL; |
| 233 | } |
| 234 | ddrss->ddrss_ss_cfg = (void *)reg; |
| 235 | |
| 236 | reg = dev_read_addr_name(dev, "ctrl_mmr_lp4"); |
| 237 | if (reg == FDT_ADDR_T_NONE) { |
| 238 | dev_err(dev, "No reg property for CTRL MMR\n"); |
| 239 | return -EINVAL; |
| 240 | } |
| 241 | ddrss->ddrss_ctrl_mmr = (void *)reg; |
| 242 | |
| 243 | ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0); |
| 244 | if (ret) { |
| 245 | dev_err(dev, "power_domain_get() failed: %d\n", ret); |
| 246 | return ret; |
| 247 | } |
| 248 | |
| 249 | ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1); |
| 250 | if (ret) { |
| 251 | dev_err(dev, "power_domain_get() failed: %d\n", ret); |
| 252 | return ret; |
| 253 | } |
| 254 | |
| 255 | ret = clk_get_by_index(dev, 0, &ddrss->ddr_clk); |
| 256 | if (ret) |
| 257 | dev_err(dev, "clk get failed%d\n", ret); |
| 258 | |
| 259 | ret = clk_get_by_index(dev, 1, &ddrss->osc_clk); |
| 260 | if (ret) |
| 261 | dev_err(dev, "clk get failed for osc clk %d\n", ret); |
| 262 | |
| 263 | ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1); |
| 264 | if (ret) |
| 265 | dev_err(dev, "ddr freq1 not populated %d\n", ret); |
| 266 | |
| 267 | ret = dev_read_u32(dev, "ti,ddr-freq2", &ddrss->ddr_freq2); |
| 268 | if (ret) |
| 269 | dev_err(dev, "ddr freq2 not populated %d\n", ret); |
| 270 | |
| 271 | ret = dev_read_u32(dev, "ti,ddr-fhs-cnt", &ddrss->ddr_fhs_cnt); |
| 272 | if (ret) |
| 273 | dev_err(dev, "ddr fhs cnt not populated %d\n", ret); |
| 274 | |
| 275 | return ret; |
| 276 | } |
| 277 | |
| 278 | void k3_lpddr4_probe(void) |
| 279 | { |
| 280 | u32 status = 0U; |
| 281 | u16 configsize = 0U; |
| 282 | |
| 283 | status = driverdt->probe(&config, &configsize); |
| 284 | |
| 285 | if ((status != 0) || (configsize != sizeof(lpddr4_privatedata)) |
| 286 | || (configsize > SRAM_MAX)) { |
| 287 | printf("%s: FAIL\n", __func__); |
| 288 | hang(); |
| 289 | } else { |
| 290 | debug("%s: PASS\n", __func__); |
| 291 | } |
| 292 | } |
| 293 | |
| 294 | void k3_lpddr4_init(void) |
| 295 | { |
| 296 | u32 status = 0U; |
| 297 | |
| 298 | if ((sizeof(pd) != sizeof(lpddr4_privatedata)) |
| 299 | || (sizeof(pd) > SRAM_MAX)) { |
| 300 | printf("%s: FAIL\n", __func__); |
| 301 | hang(); |
| 302 | } |
| 303 | |
| 304 | config.ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg; |
| 305 | config.infohandler = (lpddr4_infocallback) k3_lpddr4_info_handler; |
| 306 | |
| 307 | status = driverdt->init(&pd, &config); |
| 308 | |
| 309 | if ((status > 0U) || |
| 310 | (pd.ctlbase != (struct lpddr4_ctlregs_s *)config.ctlbase) || |
| 311 | (pd.ctlinterrupthandler != config.ctlinterrupthandler) || |
| 312 | (pd.phyindepinterrupthandler != config.phyindepinterrupthandler)) { |
| 313 | printf("%s: FAIL\n", __func__); |
| 314 | hang(); |
| 315 | } else { |
| 316 | debug("%s: PASS\n", __func__); |
| 317 | } |
| 318 | } |
| 319 | |
| 320 | void populate_data_array_from_dt(struct reginitdata *reginit_data) |
| 321 | { |
| 322 | int ret, i; |
| 323 | |
| 324 | ret = dev_read_u32_array(ddrss->dev, "ti,ctl-data", |
| 325 | (u32 *)reginit_data->ctl_regs, |
| 326 | LPDDR4_INTR_CTL_REG_COUNT); |
| 327 | if (ret) |
| 328 | printf("Error reading ctrl data %d\n", ret); |
| 329 | |
| 330 | for (i = 0; i < LPDDR4_INTR_CTL_REG_COUNT; i++) |
| 331 | reginit_data->ctl_regs_offs[i] = i; |
| 332 | |
| 333 | ret = dev_read_u32_array(ddrss->dev, "ti,pi-data", |
| 334 | (u32 *)reginit_data->pi_regs, |
| 335 | LPDDR4_INTR_PHY_INDEP_REG_COUNT); |
| 336 | if (ret) |
| 337 | printf("Error reading PI data\n"); |
| 338 | |
| 339 | for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++) |
| 340 | reginit_data->pi_regs_offs[i] = i; |
| 341 | |
| 342 | ret = dev_read_u32_array(ddrss->dev, "ti,phy-data", |
| 343 | (u32 *)reginit_data->phy_regs, |
| 344 | LPDDR4_INTR_PHY_REG_COUNT); |
| 345 | if (ret) |
| 346 | printf("Error reading PHY data %d\n", ret); |
| 347 | |
| 348 | for (i = 0; i < LPDDR4_INTR_PHY_REG_COUNT; i++) |
| 349 | reginit_data->phy_regs_offs[i] = i; |
| 350 | } |
| 351 | |
| 352 | void k3_lpddr4_hardware_reg_init(void) |
| 353 | { |
| 354 | u32 status = 0U; |
| 355 | struct reginitdata reginitdata; |
| 356 | |
| 357 | populate_data_array_from_dt(®initdata); |
| 358 | |
| 359 | status = driverdt->writectlconfig(&pd, reginitdata.ctl_regs, |
| 360 | reginitdata.ctl_regs_offs, |
| 361 | LPDDR4_INTR_CTL_REG_COUNT); |
| 362 | if (!status) |
| 363 | status = driverdt->writephyindepconfig(&pd, reginitdata.pi_regs, |
| 364 | reginitdata.pi_regs_offs, |
| 365 | LPDDR4_INTR_PHY_INDEP_REG_COUNT); |
| 366 | if (!status) |
| 367 | status = driverdt->writephyconfig(&pd, reginitdata.phy_regs, |
| 368 | reginitdata.phy_regs_offs, |
| 369 | LPDDR4_INTR_PHY_REG_COUNT); |
| 370 | if (status) { |
| 371 | printf("%s: FAIL\n", __func__); |
| 372 | hang(); |
| 373 | } |
| 374 | } |
| 375 | |
| 376 | void k3_lpddr4_start(void) |
| 377 | { |
| 378 | u32 status = 0U; |
| 379 | u32 regval = 0U; |
| 380 | u32 offset = 0U; |
| 381 | |
| 382 | TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset); |
| 383 | |
| 384 | status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val); |
| 385 | if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) { |
| 386 | printf("%s: Pre start FAIL\n", __func__); |
| 387 | hang(); |
| 388 | } |
| 389 | |
| 390 | status = driverdt->start(&pd); |
| 391 | if (status > 0U) { |
| 392 | printf("%s: FAIL\n", __func__); |
| 393 | hang(); |
| 394 | } |
| 395 | |
| 396 | status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val); |
| 397 | if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) { |
| 398 | printf("%s: Post start FAIL\n", __func__); |
| 399 | hang(); |
| 400 | } else { |
| 401 | debug("%s: Post start PASS\n", __func__); |
| 402 | } |
| 403 | } |
| 404 | |
| 405 | static int k3_ddrss_probe(struct udevice *dev) |
| 406 | { |
| 407 | int ret; |
| 408 | |
| 409 | ddrss = dev_get_priv(dev); |
| 410 | |
| 411 | debug("%s(dev=%p)\n", __func__, dev); |
| 412 | |
| 413 | ret = k3_ddrss_ofdata_to_priv(dev); |
| 414 | if (ret) |
| 415 | return ret; |
| 416 | |
| 417 | ddrss->dev = dev; |
| 418 | ret = k3_ddrss_power_on(ddrss); |
| 419 | if (ret) |
| 420 | return ret; |
| 421 | |
Dave Gerlach | 9f9b5c1 | 2021-05-11 10:22:12 -0500 | [diff] [blame^] | 422 | #ifdef CONFIG_K3_AM64_DDRSS |
| 423 | |
| 424 | writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_R1_MAT_REG); |
| 425 | writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG); |
| 426 | #endif |
| 427 | |
Dave Gerlach | a8c13c7 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 428 | driverdt = lpddr4_getinstance(); |
| 429 | k3_lpddr4_probe(); |
| 430 | k3_lpddr4_init(); |
| 431 | k3_lpddr4_hardware_reg_init(); |
| 432 | |
| 433 | ret = k3_ddrss_init_freq(ddrss); |
| 434 | if (ret) |
| 435 | return ret; |
| 436 | |
| 437 | k3_lpddr4_start(); |
| 438 | |
| 439 | return ret; |
| 440 | } |
| 441 | |
| 442 | static int k3_ddrss_get_info(struct udevice *dev, struct ram_info *info) |
| 443 | { |
| 444 | return 0; |
| 445 | } |
| 446 | |
| 447 | static struct ram_ops k3_ddrss_ops = { |
| 448 | .get_info = k3_ddrss_get_info, |
| 449 | }; |
| 450 | |
| 451 | static const struct udevice_id k3_ddrss_ids[] = { |
Dave Gerlach | 9f9b5c1 | 2021-05-11 10:22:12 -0500 | [diff] [blame^] | 452 | {.compatible = "ti,am64-ddrss"}, |
Dave Gerlach | a8c13c7 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 453 | {.compatible = "ti,j721e-ddrss"}, |
| 454 | {} |
| 455 | }; |
| 456 | |
| 457 | U_BOOT_DRIVER(k3_ddrss) = { |
| 458 | .name = "k3_ddrss", |
| 459 | .id = UCLASS_RAM, |
| 460 | .of_match = k3_ddrss_ids, |
| 461 | .ops = &k3_ddrss_ops, |
| 462 | .probe = k3_ddrss_probe, |
| 463 | .priv_auto = sizeof(struct k3_ddrss_desc), |
| 464 | }; |