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Jagannadha Sutradharudu Tekif8f36c52014-01-09 01:48:26 +05301/*
2 * Xilinx Zynq 7000 DTSI
3 * Describes the hardware common to all Zynq 7000-based boards.
4 *
5 * Copyright (C) 2013 Xilinx, Inc.
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9/include/ "skeleton.dtsi"
10
11/ {
12 compatible = "xlnx,zynq-7000";
Masahiro Yamada580a54c2014-05-15 20:37:53 +090013
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu@0 {
19 compatible = "arm,cortex-a9";
20 device_type = "cpu";
21 reg = <0>;
22 clocks = <&clkc 3>;
23 clock-latency = <1000>;
24 operating-points = <
25 /* kHz uV */
26 666667 1000000
27 333334 1000000
28 222223 1000000
29 >;
30 };
31
32 cpu@1 {
33 compatible = "arm,cortex-a9";
34 device_type = "cpu";
35 reg = <1>;
36 clocks = <&clkc 3>;
37 };
38 };
39
40 pmu {
41 compatible = "arm,cortex-a9-pmu";
42 interrupts = <0 5 4>, <0 6 4>;
43 interrupt-parent = <&intc>;
44 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
45 };
46
47 amba {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 interrupt-parent = <&intc>;
52 ranges;
53
54 i2c0: zynq-i2c@e0004000 {
55 compatible = "cdns,i2c-r1p10";
56 status = "disabled";
57 clocks = <&clkc 38>;
58 interrupt-parent = <&intc>;
59 interrupts = <0 25 4>;
60 reg = <0xe0004000 0x1000>;
61 #address-cells = <1>;
62 #size-cells = <0>;
63 };
64
65 i2c1: zynq-i2c@e0005000 {
66 compatible = "cdns,i2c-r1p10";
67 status = "disabled";
68 clocks = <&clkc 39>;
69 interrupt-parent = <&intc>;
70 interrupts = <0 48 4>;
71 reg = <0xe0005000 0x1000>;
72 #address-cells = <1>;
73 #size-cells = <0>;
74 };
75
76 intc: interrupt-controller@f8f01000 {
77 compatible = "arm,cortex-a9-gic";
78 #interrupt-cells = <3>;
79 #address-cells = <1>;
80 interrupt-controller;
81 reg = <0xF8F01000 0x1000>,
82 <0xF8F00100 0x100>;
83 };
84
85 L2: cache-controller {
86 compatible = "arm,pl310-cache";
87 reg = <0xF8F02000 0x1000>;
88 arm,data-latency = <3 2 2>;
89 arm,tag-latency = <2 2 2>;
90 cache-unified;
91 cache-level = <2>;
92 };
93
94 uart0: uart@e0000000 {
95 compatible = "xlnx,xuartps";
96 status = "disabled";
97 clocks = <&clkc 23>, <&clkc 40>;
98 clock-names = "ref_clk", "aper_clk";
99 reg = <0xE0000000 0x1000>;
100 interrupts = <0 27 4>;
101 };
102
103 uart1: uart@e0001000 {
104 compatible = "xlnx,xuartps";
105 status = "disabled";
106 clocks = <&clkc 24>, <&clkc 41>;
107 clock-names = "ref_clk", "aper_clk";
108 reg = <0xE0001000 0x1000>;
109 interrupts = <0 50 4>;
110 };
111
112 gem0: ethernet@e000b000 {
113 compatible = "cdns,gem";
114 reg = <0xe000b000 0x4000>;
115 status = "disabled";
116 interrupts = <0 22 4>;
117 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
118 clock-names = "pclk", "hclk", "tx_clk";
119 };
120
121 gem1: ethernet@e000c000 {
122 compatible = "cdns,gem";
123 reg = <0xe000c000 0x4000>;
124 status = "disabled";
125 interrupts = <0 45 4>;
126 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
127 clock-names = "pclk", "hclk", "tx_clk";
128 };
129
130 sdhci0: ps7-sdhci@e0100000 {
131 compatible = "arasan,sdhci-8.9a";
132 status = "disabled";
133 clock-names = "clk_xin", "clk_ahb";
134 clocks = <&clkc 21>, <&clkc 32>;
135 interrupt-parent = <&intc>;
136 interrupts = <0 24 4>;
137 reg = <0xe0100000 0x1000>;
138 } ;
139
140 sdhci1: ps7-sdhci@e0101000 {
141 compatible = "arasan,sdhci-8.9a";
142 status = "disabled";
143 clock-names = "clk_xin", "clk_ahb";
144 clocks = <&clkc 22>, <&clkc 33>;
145 interrupt-parent = <&intc>;
146 interrupts = <0 47 4>;
147 reg = <0xe0101000 0x1000>;
148 } ;
149
150 slcr: slcr@f8000000 {
151 #address-cells = <1>;
152 #size-cells = <1>;
153 compatible = "xlnx,zynq-slcr", "syscon";
154 reg = <0xF8000000 0x1000>;
155 ranges;
156 clkc: clkc@100 {
157 #clock-cells = <1>;
158 compatible = "xlnx,ps7-clkc";
159 ps-clk-frequency = <33333333>;
160 fclk-enable = <0>;
161 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
162 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
163 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
164 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
165 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
166 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
167 "gem1_aper", "sdio0_aper", "sdio1_aper",
168 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
169 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
170 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
171 "dbg_trc", "dbg_apb";
172 reg = <0x100 0x100>;
173 };
174 };
175
176 global_timer: timer@f8f00200 {
177 compatible = "arm,cortex-a9-global-timer";
178 reg = <0xf8f00200 0x20>;
179 interrupts = <1 11 0x301>;
180 interrupt-parent = <&intc>;
181 clocks = <&clkc 4>;
182 };
183
184 ttc0: ttc0@f8001000 {
185 interrupt-parent = <&intc>;
186 interrupts = < 0 10 4 0 11 4 0 12 4 >;
187 compatible = "cdns,ttc";
188 clocks = <&clkc 6>;
189 reg = <0xF8001000 0x1000>;
190 };
191
192 ttc1: ttc1@f8002000 {
193 interrupt-parent = <&intc>;
194 interrupts = < 0 37 4 0 38 4 0 39 4 >;
195 compatible = "cdns,ttc";
196 clocks = <&clkc 6>;
197 reg = <0xF8002000 0x1000>;
198 };
199 scutimer: scutimer@f8f00600 {
200 interrupt-parent = <&intc>;
201 interrupts = < 1 13 0x301 >;
202 compatible = "arm,cortex-a9-twd-timer";
203 reg = < 0xf8f00600 0x20 >;
204 clocks = <&clkc 4>;
205 } ;
206 };
Jagannadha Sutradharudu Tekif8f36c52014-01-09 01:48:26 +0530207};