blob: 43e5bea60d9421f06665e386e06971449274db08 [file] [log] [blame]
Masahiro Yamada8f062432015-12-16 10:54:07 +09001/*
2 * Device Tree Source commonly used by UniPhier ARM SoCs
3 *
4 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+ X11
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
Masahiro Yamadacc336092016-02-02 21:11:33 +090012 clocks {
13 refclk: ref {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 };
17 };
18
Masahiro Yamada8f062432015-12-16 10:54:07 +090019 soc: soc {
20 compatible = "simple-bus";
21 #address-cells = <1>;
22 #size-cells = <1>;
23 ranges;
24 interrupt-parent = <&intc>;
25
26 extbus: extbus {
27 compatible = "simple-bus";
28 #address-cells = <2>;
29 #size-cells = <1>;
30 };
31
32 serial0: serial@54006800 {
33 compatible = "socionext,uniphier-uart";
34 status = "disabled";
35 reg = <0x54006800 0x40>;
36 interrupts = <0 33 4>;
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_uart0>;
39 clocks = <&uart_clk>;
40 };
41
42 serial1: serial@54006900 {
43 compatible = "socionext,uniphier-uart";
44 status = "disabled";
45 reg = <0x54006900 0x40>;
46 interrupts = <0 35 4>;
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_uart1>;
49 clocks = <&uart_clk>;
50 };
51
52 serial2: serial@54006a00 {
53 compatible = "socionext,uniphier-uart";
54 status = "disabled";
55 reg = <0x54006a00 0x40>;
56 interrupts = <0 37 4>;
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_uart2>;
59 clocks = <&uart_clk>;
60 };
61
62 serial3: serial@54006b00 {
63 compatible = "socionext,uniphier-uart";
64 status = "disabled";
65 reg = <0x54006b00 0x40>;
66 interrupts = <0 177 4>;
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_uart3>;
69 clocks = <&uart_clk>;
70 };
71
72 system-bus-controller@58c00000 {
73 compatible = "socionext,uniphier-system-bus-controller";
74 reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
75 };
76
Masahiro Yamada9fbb2f72016-02-02 21:11:35 +090077 peri: perictrl@59820000 {
78 /* specify compatible in each SoC DTSI */
79 reg = <0x59820000 0x200>;
80 #clock-cells = <1>;
81 };
82
Masahiro Yamada8f062432015-12-16 10:54:07 +090083 timer@60000200 {
84 compatible = "arm,cortex-a9-global-timer";
85 reg = <0x60000200 0x20>;
86 interrupts = <1 11 0x104>;
87 clocks = <&arm_timer_clk>;
88 };
89
90 timer@60000600 {
91 compatible = "arm,cortex-a9-twd-timer";
92 reg = <0x60000600 0x20>;
93 interrupts = <1 13 0x104>;
94 clocks = <&arm_timer_clk>;
95 };
96
97 intc: interrupt-controller@60001000 {
98 compatible = "arm,cortex-a9-gic";
99 reg = <0x60001000 0x1000>,
100 <0x60000100 0x100>;
101 #interrupt-cells = <3>;
102 interrupt-controller;
103 };
104
105 pinctrl: pinctrl@5f801000 {
106 /* specify compatible in each SoC DTSI */
107 reg = <0x5f801000 0xe00>;
108 };
109
Masahiro Yamada233812a2016-02-02 21:11:34 +0900110 sysctrl: sysctrl@61840000 {
111 /* specify compatible in each SoC DTSI */
112 reg = <0x61840000 0x4000>;
113 #clock-cells = <1>;
114 clock-names = "ref";
115 clocks = <&refclk>;
116 };
117
Masahiro Yamada8f062432015-12-16 10:54:07 +0900118 nand: nand@68000000 {
119 compatible = "denali,denali-nand-dt";
120 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
121 reg-names = "nand_data", "denali_reg";
122 };
123 };
124};
125
126/include/ "uniphier-pinctrl.dtsi"