blob: f5c6f3e7d29071704cd8baa541f88808d5cbfabb [file] [log] [blame]
Simon Glass18530302013-03-19 04:58:56 +00001/*
2 * Copyright (c) 2011-12 The Chromium OS Authors.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Simon Glass18530302013-03-19 04:58:56 +00005 *
6 * This file is derived from the flashrom project.
7 */
8
9#include <common.h>
10#include <malloc.h>
11#include <spi.h>
12#include <pci.h>
13#include <pci_ids.h>
14#include <asm/io.h>
15
16#include "ich.h"
17
18#define SPI_OPCODE_WREN 0x06
19#define SPI_OPCODE_FAST_READ 0x0b
20
21struct ich_ctlr {
22 pci_dev_t dev; /* PCI device number */
23 int ich_version; /* Controller version, 7 or 9 */
24 int ichspi_lock;
25 int locked;
26 uint8_t *opmenu;
27 int menubytes;
28 void *base; /* Base of register set */
29 uint16_t *preop;
30 uint16_t *optype;
31 uint32_t *addr;
32 uint8_t *data;
33 unsigned databytes;
34 uint8_t *status;
35 uint16_t *control;
36 uint32_t *bbar;
37 uint32_t *pr; /* only for ich9 */
38 uint8_t *speed; /* pointer to speed control */
39 ulong max_speed; /* Maximum bus speed in MHz */
40};
41
42struct ich_ctlr ctlr;
43
44static inline struct ich_spi_slave *to_ich_spi(struct spi_slave *slave)
45{
46 return container_of(slave, struct ich_spi_slave, slave);
47}
48
49static unsigned int ich_reg(const void *addr)
50{
51 return (unsigned)(addr - ctlr.base) & 0xffff;
52}
53
54static u8 ich_readb(const void *addr)
55{
56 u8 value = readb(addr);
57
58 debug("read %2.2x from %4.4x\n", value, ich_reg(addr));
59
60 return value;
61}
62
63static u16 ich_readw(const void *addr)
64{
65 u16 value = readw(addr);
66
67 debug("read %4.4x from %4.4x\n", value, ich_reg(addr));
68
69 return value;
70}
71
72static u32 ich_readl(const void *addr)
73{
74 u32 value = readl(addr);
75
76 debug("read %8.8x from %4.4x\n", value, ich_reg(addr));
77
78 return value;
79}
80
81static void ich_writeb(u8 value, void *addr)
82{
83 writeb(value, addr);
84 debug("wrote %2.2x to %4.4x\n", value, ich_reg(addr));
85}
86
87static void ich_writew(u16 value, void *addr)
88{
89 writew(value, addr);
90 debug("wrote %4.4x to %4.4x\n", value, ich_reg(addr));
91}
92
93static void ich_writel(u32 value, void *addr)
94{
95 writel(value, addr);
96 debug("wrote %8.8x to %4.4x\n", value, ich_reg(addr));
97}
98
99static void write_reg(const void *value, void *dest, uint32_t size)
100{
101 memcpy_toio(dest, value, size);
102}
103
104static void read_reg(const void *src, void *value, uint32_t size)
105{
106 memcpy_fromio(value, src, size);
107}
108
109static void ich_set_bbar(struct ich_ctlr *ctlr, uint32_t minaddr)
110{
111 const uint32_t bbar_mask = 0x00ffff00;
112 uint32_t ichspi_bbar;
113
114 minaddr &= bbar_mask;
115 ichspi_bbar = ich_readl(ctlr->bbar) & ~bbar_mask;
116 ichspi_bbar |= minaddr;
117 ich_writel(ichspi_bbar, ctlr->bbar);
118}
119
120int spi_cs_is_valid(unsigned int bus, unsigned int cs)
121{
122 puts("spi_cs_is_valid used but not implemented\n");
123 return 0;
124}
125
126struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
127 unsigned int max_hz, unsigned int mode)
128{
129 struct ich_spi_slave *ich;
130
131 ich = spi_alloc_slave(struct ich_spi_slave, bus, cs);
132 if (!ich) {
133 puts("ICH SPI: Out of memory\n");
134 return NULL;
135 }
136
Simon Glass5e6fb692013-03-11 06:08:07 +0000137 /*
138 * Yes this controller can only write a small number of bytes at
139 * once! The limit is typically 64 bytes.
140 */
141 ich->slave.max_write_size = ctlr.databytes;
Simon Glass18530302013-03-19 04:58:56 +0000142 ich->speed = max_hz;
143
144 return &ich->slave;
145}
146
147void spi_free_slave(struct spi_slave *slave)
148{
149 struct ich_spi_slave *ich = to_ich_spi(slave);
150
151 free(ich);
152}
153
154/*
155 * Check if this device ID matches one of supported Intel PCH devices.
156 *
157 * Return the ICH version if there is a match, or zero otherwise.
158 */
159static int get_ich_version(uint16_t device_id)
160{
161 if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC)
162 return 7;
163
164 if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
165 device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) ||
166 (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
167 device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX))
168 return 9;
169
170 return 0;
171}
172
173/* @return 1 if the SPI flash supports the 33MHz speed */
174static int ich9_can_do_33mhz(pci_dev_t dev)
175{
176 u32 fdod, speed;
177
178 /* Observe SPI Descriptor Component Section 0 */
179 pci_write_config_dword(dev, 0xb0, 0x1000);
180
181 /* Extract the Write/Erase SPI Frequency from descriptor */
182 pci_read_config_dword(dev, 0xb4, &fdod);
183
184 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
185 speed = (fdod >> 21) & 7;
186
187 return speed == 1;
188}
189
190static int ich_find_spi_controller(pci_dev_t *devp, int *ich_versionp)
191{
192 int last_bus = pci_last_busno();
193 int bus;
194
195 if (last_bus == -1) {
196 debug("No PCI busses?\n");
197 return -1;
198 }
199
200 for (bus = 0; bus <= last_bus; bus++) {
201 uint16_t vendor_id, device_id;
202 uint32_t ids;
203 pci_dev_t dev;
204
205 dev = PCI_BDF(bus, 31, 0);
206 pci_read_config_dword(dev, 0, &ids);
207 vendor_id = ids;
208 device_id = ids >> 16;
209
210 if (vendor_id == PCI_VENDOR_ID_INTEL) {
211 *devp = dev;
212 *ich_versionp = get_ich_version(device_id);
213 return 0;
214 }
215 }
216
217 debug("ICH SPI: No ICH found.\n");
218 return -1;
219}
220
221static int ich_init_controller(struct ich_ctlr *ctlr)
222{
223 uint8_t *rcrb; /* Root Complex Register Block */
224 uint32_t rcba; /* Root Complex Base Address */
225
226 pci_read_config_dword(ctlr->dev, 0xf0, &rcba);
227 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
228 rcrb = (uint8_t *)(rcba & 0xffffc000);
229 if (ctlr->ich_version == 7) {
230 struct ich7_spi_regs *ich7_spi;
231
232 ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020);
233 ctlr->ichspi_lock = ich_readw(&ich7_spi->spis) & SPIS_LOCK;
234 ctlr->opmenu = ich7_spi->opmenu;
235 ctlr->menubytes = sizeof(ich7_spi->opmenu);
236 ctlr->optype = &ich7_spi->optype;
237 ctlr->addr = &ich7_spi->spia;
238 ctlr->data = (uint8_t *)ich7_spi->spid;
239 ctlr->databytes = sizeof(ich7_spi->spid);
240 ctlr->status = (uint8_t *)&ich7_spi->spis;
241 ctlr->control = &ich7_spi->spic;
242 ctlr->bbar = &ich7_spi->bbar;
243 ctlr->preop = &ich7_spi->preop;
244 ctlr->base = ich7_spi;
245 } else if (ctlr->ich_version == 9) {
246 struct ich9_spi_regs *ich9_spi;
247
248 ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
249 ctlr->ichspi_lock = ich_readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
250 ctlr->opmenu = ich9_spi->opmenu;
251 ctlr->menubytes = sizeof(ich9_spi->opmenu);
252 ctlr->optype = &ich9_spi->optype;
253 ctlr->addr = &ich9_spi->faddr;
254 ctlr->data = (uint8_t *)ich9_spi->fdata;
255 ctlr->databytes = sizeof(ich9_spi->fdata);
256 ctlr->status = &ich9_spi->ssfs;
257 ctlr->control = (uint16_t *)ich9_spi->ssfc;
258 ctlr->speed = ich9_spi->ssfc + 2;
259 ctlr->bbar = &ich9_spi->bbar;
260 ctlr->preop = &ich9_spi->preop;
261 ctlr->pr = &ich9_spi->pr[0];
262 ctlr->base = ich9_spi;
263 } else {
264 debug("ICH SPI: Unrecognized ICH version %d.\n",
265 ctlr->ich_version);
266 return -1;
267 }
268 debug("ICH SPI: Version %d detected\n", ctlr->ich_version);
269
270 /* Work out the maximum speed we can support */
271 ctlr->max_speed = 20000000;
272 if (ctlr->ich_version == 9 && ich9_can_do_33mhz(ctlr->dev))
273 ctlr->max_speed = 33000000;
274
275 ich_set_bbar(ctlr, 0);
276
277 return 0;
278}
279
280void spi_init(void)
281{
282 uint8_t bios_cntl;
283
284 if (ich_find_spi_controller(&ctlr.dev, &ctlr.ich_version)) {
285 printf("ICH SPI: Cannot find device\n");
286 return;
287 }
288
289 if (ich_init_controller(&ctlr)) {
290 printf("ICH SPI: Cannot setup controller\n");
291 return;
292 }
293
294 /*
295 * Disable the BIOS write protect so write commands are allowed. On
296 * v9, deassert SMM BIOS Write Protect Disable.
297 */
298 pci_read_config_byte(ctlr.dev, 0xdc, &bios_cntl);
299 if (ctlr.ich_version == 9)
300 bios_cntl &= ~(1 << 5);
301 pci_write_config_byte(ctlr.dev, 0xdc, bios_cntl | 0x1);
302}
303
304int spi_claim_bus(struct spi_slave *slave)
305{
306 /* Handled by ICH automatically. */
307 return 0;
308}
309
310void spi_release_bus(struct spi_slave *slave)
311{
312 /* Handled by ICH automatically. */
313}
314
315void spi_cs_activate(struct spi_slave *slave)
316{
317 /* Handled by ICH automatically. */
318}
319
320void spi_cs_deactivate(struct spi_slave *slave)
321{
322 /* Handled by ICH automatically. */
323}
324
325static inline void spi_use_out(struct spi_trans *trans, unsigned bytes)
326{
327 trans->out += bytes;
328 trans->bytesout -= bytes;
329}
330
331static inline void spi_use_in(struct spi_trans *trans, unsigned bytes)
332{
333 trans->in += bytes;
334 trans->bytesin -= bytes;
335}
336
337static void spi_setup_type(struct spi_trans *trans, int data_bytes)
338{
339 trans->type = 0xFF;
340
341 /* Try to guess spi type from read/write sizes. */
342 if (trans->bytesin == 0) {
343 if (trans->bytesout + data_bytes > 4)
344 /*
345 * If bytesin = 0 and bytesout > 4, we presume this is
346 * a write data operation, which is accompanied by an
347 * address.
348 */
349 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
350 else
351 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
352 return;
353 }
354
355 if (trans->bytesout == 1) { /* and bytesin is > 0 */
356 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
357 return;
358 }
359
360 if (trans->bytesout == 4) /* and bytesin is > 0 */
361 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
362
363 /* Fast read command is called with 5 bytes instead of 4 */
364 if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
365 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
366 --trans->bytesout;
367 }
368}
369
370static int spi_setup_opcode(struct spi_trans *trans)
371{
372 uint16_t optypes;
373 uint8_t opmenu[ctlr.menubytes];
374
375 trans->opcode = trans->out[0];
376 spi_use_out(trans, 1);
377 if (!ctlr.ichspi_lock) {
378 /* The lock is off, so just use index 0. */
379 ich_writeb(trans->opcode, ctlr.opmenu);
380 optypes = ich_readw(ctlr.optype);
381 optypes = (optypes & 0xfffc) | (trans->type & 0x3);
382 ich_writew(optypes, ctlr.optype);
383 return 0;
384 } else {
385 /* The lock is on. See if what we need is on the menu. */
386 uint8_t optype;
387 uint16_t opcode_index;
388
389 /* Write Enable is handled as atomic prefix */
390 if (trans->opcode == SPI_OPCODE_WREN)
391 return 0;
392
393 read_reg(ctlr.opmenu, opmenu, sizeof(opmenu));
394 for (opcode_index = 0; opcode_index < ctlr.menubytes;
395 opcode_index++) {
396 if (opmenu[opcode_index] == trans->opcode)
397 break;
398 }
399
400 if (opcode_index == ctlr.menubytes) {
401 printf("ICH SPI: Opcode %x not found\n",
402 trans->opcode);
403 return -1;
404 }
405
406 optypes = ich_readw(ctlr.optype);
407 optype = (optypes >> (opcode_index * 2)) & 0x3;
408 if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
409 optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
410 trans->bytesout >= 3) {
411 /* We guessed wrong earlier. Fix it up. */
412 trans->type = optype;
413 }
414 if (optype != trans->type) {
415 printf("ICH SPI: Transaction doesn't fit type %d\n",
416 optype);
417 return -1;
418 }
419 return opcode_index;
420 }
421}
422
423static int spi_setup_offset(struct spi_trans *trans)
424{
425 /* Separate the SPI address and data. */
426 switch (trans->type) {
427 case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
428 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
429 return 0;
430 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
431 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
432 trans->offset = ((uint32_t)trans->out[0] << 16) |
433 ((uint32_t)trans->out[1] << 8) |
434 ((uint32_t)trans->out[2] << 0);
435 spi_use_out(trans, 3);
436 return 1;
437 default:
438 printf("Unrecognized SPI transaction type %#x\n", trans->type);
439 return -1;
440 }
441}
442
443/*
444 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
York Sun472d5462013-04-01 11:29:11 -0700445 * below is true) or 0. In case the wait was for the bit(s) to set - write
Simon Glass18530302013-03-19 04:58:56 +0000446 * those bits back, which would cause resetting them.
447 *
448 * Return the last read status value on success or -1 on failure.
449 */
450static int ich_status_poll(u16 bitmask, int wait_til_set)
451{
452 int timeout = 600000; /* This will result in 6s */
453 u16 status = 0;
454
455 while (timeout--) {
456 status = ich_readw(ctlr.status);
457 if (wait_til_set ^ ((status & bitmask) == 0)) {
458 if (wait_til_set)
459 ich_writew((status & bitmask), ctlr.status);
460 return status;
461 }
462 udelay(10);
463 }
464
465 printf("ICH SPI: SCIP timeout, read %x, expected %x\n",
466 status, bitmask);
467 return -1;
468}
469
470/*
471int spi_xfer(struct spi_slave *slave, const void *dout,
472 unsigned int bitsout, void *din, unsigned int bitsin)
473*/
474int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
475 void *din, unsigned long flags)
476{
477 struct ich_spi_slave *ich = to_ich_spi(slave);
478 uint16_t control;
479 int16_t opcode_index;
480 int with_address;
481 int status;
482 int bytes = bitlen / 8;
483 struct spi_trans *trans = &ich->trans;
484 unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END);
485 int using_cmd = 0;
486 /* Align read transactions to 64-byte boundaries */
487 char buff[ctlr.databytes];
488
489 /* Ee don't support writing partial bytes. */
490 if (bitlen % 8) {
491 debug("ICH SPI: Accessing partial bytes not supported\n");
492 return -1;
493 }
494
495 /* An empty end transaction can be ignored */
496 if (type == SPI_XFER_END && !dout && !din)
497 return 0;
498
499 if (type & SPI_XFER_BEGIN)
500 memset(trans, '\0', sizeof(*trans));
501
502 /* Dp we need to come back later to finish it? */
503 if (dout && type == SPI_XFER_BEGIN) {
504 if (bytes > ICH_MAX_CMD_LEN) {
505 debug("ICH SPI: Command length limit exceeded\n");
506 return -1;
507 }
508 memcpy(trans->cmd, dout, bytes);
509 trans->cmd_len = bytes;
510 debug("ICH SPI: Saved %d bytes\n", bytes);
511 return 0;
512 }
513
514 /*
515 * We process a 'middle' spi_xfer() call, which has no
516 * SPI_XFER_BEGIN/END, as an independent transaction as if it had
517 * an end. We therefore repeat the command. This is because ICH
518 * seems to have no support for this, or because interest (in digging
519 * out the details and creating a special case in the code) is low.
520 */
521 if (trans->cmd_len) {
522 trans->out = trans->cmd;
523 trans->bytesout = trans->cmd_len;
524 using_cmd = 1;
525 debug("ICH SPI: Using %d bytes\n", trans->cmd_len);
526 } else {
527 trans->out = dout;
528 trans->bytesout = dout ? bytes : 0;
529 }
530
531 trans->in = din;
532 trans->bytesin = din ? bytes : 0;
533
534 /* There has to always at least be an opcode. */
535 if (!trans->bytesout) {
536 debug("ICH SPI: No opcode for transfer\n");
537 return -1;
538 }
539
540 if (ich_status_poll(SPIS_SCIP, 0) == -1)
541 return -1;
542
543 ich_writew(SPIS_CDS | SPIS_FCERR, ctlr.status);
544
545 spi_setup_type(trans, using_cmd ? bytes : 0);
546 opcode_index = spi_setup_opcode(trans);
547 if (opcode_index < 0)
548 return -1;
549 with_address = spi_setup_offset(trans);
550 if (with_address < 0)
551 return -1;
552
553 if (trans->opcode == SPI_OPCODE_WREN) {
554 /*
555 * Treat Write Enable as Atomic Pre-Op if possible
556 * in order to prevent the Management Engine from
557 * issuing a transaction between WREN and DATA.
558 */
559 if (!ctlr.ichspi_lock)
560 ich_writew(trans->opcode, ctlr.preop);
561 return 0;
562 }
563
564 if (ctlr.speed && ctlr.max_speed >= 33000000) {
565 int byte;
566
567 byte = ich_readb(ctlr.speed);
568 if (ich->speed >= 33000000)
569 byte |= SSFC_SCF_33MHZ;
570 else
571 byte &= ~SSFC_SCF_33MHZ;
572 ich_writeb(byte, ctlr.speed);
573 }
574
575 /* See if we have used up the command data */
576 if (using_cmd && dout && bytes) {
577 trans->out = dout;
578 trans->bytesout = bytes;
579 debug("ICH SPI: Moving to data, %d bytes\n", bytes);
580 }
581
582 /* Preset control fields */
583 control = ich_readw(ctlr.control);
584 control &= ~SSFC_RESERVED;
585 control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
586
587 /* Issue atomic preop cycle if needed */
588 if (ich_readw(ctlr.preop))
589 control |= SPIC_ACS;
590
591 if (!trans->bytesout && !trans->bytesin) {
592 /* SPI addresses are 24 bit only */
593 if (with_address)
594 ich_writel(trans->offset & 0x00FFFFFF, ctlr.addr);
595
596 /*
597 * This is a 'no data' command (like Write Enable), its
598 * bitesout size was 1, decremented to zero while executing
599 * spi_setup_opcode() above. Tell the chip to send the
600 * command.
601 */
602 ich_writew(control, ctlr.control);
603
604 /* wait for the result */
605 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
606 if (status == -1)
607 return -1;
608
609 if (status & SPIS_FCERR) {
610 debug("ICH SPI: Command transaction error\n");
611 return -1;
612 }
613
614 return 0;
615 }
616
617 /*
618 * Check if this is a write command atempting to transfer more bytes
619 * than the controller can handle. Iterations for writes are not
620 * supported here because each SPI write command needs to be preceded
621 * and followed by other SPI commands, and this sequence is controlled
622 * by the SPI chip driver.
623 */
624 if (trans->bytesout > ctlr.databytes) {
625 debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n");
626 return -1;
627 }
628
629 /*
630 * Read or write up to databytes bytes at a time until everything has
631 * been sent.
632 */
633 while (trans->bytesout || trans->bytesin) {
634 uint32_t data_length;
635 uint32_t aligned_offset;
636 uint32_t diff;
637
638 aligned_offset = trans->offset & ~(ctlr.databytes - 1);
639 diff = trans->offset - aligned_offset;
640
641 /* SPI addresses are 24 bit only */
642 ich_writel(aligned_offset & 0x00FFFFFF, ctlr.addr);
643
644 if (trans->bytesout)
645 data_length = min(trans->bytesout, ctlr.databytes);
646 else
647 data_length = min(trans->bytesin, ctlr.databytes);
648
649 /* Program data into FDATA0 to N */
650 if (trans->bytesout) {
651 write_reg(trans->out, ctlr.data, data_length);
652 spi_use_out(trans, data_length);
653 if (with_address)
654 trans->offset += data_length;
655 }
656
657 /* Add proper control fields' values */
658 control &= ~((ctlr.databytes - 1) << 8);
659 control |= SPIC_DS;
660 control |= (data_length - 1) << 8;
661
662 /* write it */
663 ich_writew(control, ctlr.control);
664
665 /* Wait for Cycle Done Status or Flash Cycle Error. */
666 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
667 if (status == -1)
668 return -1;
669
670 if (status & SPIS_FCERR) {
671 debug("ICH SPI: Data transaction error\n");
672 return -1;
673 }
674
675 if (trans->bytesin) {
676 if (diff) {
677 data_length -= diff;
678 read_reg(ctlr.data, buff, ctlr.databytes);
679 memcpy(trans->in, buff + diff, data_length);
680 } else {
681 read_reg(ctlr.data, trans->in, data_length);
682 }
683 spi_use_in(trans, data_length);
684 if (with_address)
685 trans->offset += data_length;
686 }
687 }
688
689 /* Clear atomic preop now that xfer is done */
690 ich_writew(0, ctlr.preop);
691
692 return 0;
693}
694
695
696/*
697 * This uses the SPI controller from the Intel Cougar Point and Panther Point
698 * PCH to write-protect portions of the SPI flash until reboot. The changes
699 * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's
700 * done elsewhere.
701 */
702int spi_write_protect_region(uint32_t lower_limit, uint32_t length, int hint)
703{
704 uint32_t tmplong;
705 uint32_t upper_limit;
706
707 if (!ctlr.pr) {
708 printf("%s: operation not supported on this chipset\n",
709 __func__);
710 return -1;
711 }
712
713 if (length == 0 ||
714 lower_limit > (0xFFFFFFFFUL - length) + 1 ||
715 hint < 0 || hint > 4) {
716 printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__,
717 lower_limit, length, hint);
718 return -1;
719 }
720
721 upper_limit = lower_limit + length - 1;
722
723 /*
724 * Determine bits to write, as follows:
725 * 31 Write-protection enable (includes erase operation)
726 * 30:29 reserved
727 * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff)
728 * 15 Read-protection enable
729 * 14:13 reserved
730 * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000)
731 */
732 tmplong = 0x80000000 |
733 ((upper_limit & 0x01fff000) << 4) |
734 ((lower_limit & 0x01fff000) >> 12);
735
736 printf("%s: writing 0x%08x to %p\n", __func__, tmplong,
737 &ctlr.pr[hint]);
738 ctlr.pr[hint] = tmplong;
739
740 return 0;
741}