Dirk Eibach | a605ea7 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010 |
| 3 | * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <common.h> |
| 25 | #include <command.h> |
| 26 | #include <asm/processor.h> |
| 27 | #include <asm/io.h> |
| 28 | #include <asm/ppc4xx-gpio.h> |
| 29 | |
| 30 | #include <miiphy.h> |
| 31 | |
Dirk Eibach | 2da0fc0 | 2011-01-21 09:31:21 +0100 | [diff] [blame] | 32 | #include <gdsys_fpga.h> |
Dirk Eibach | a605ea7 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 33 | |
| 34 | #define PHYREG_CONTROL 0 |
| 35 | #define PHYREG_PAGE_ADDRESS 22 |
| 36 | #define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16 |
| 37 | #define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26 |
| 38 | |
| 39 | enum { |
Dirk Eibach | a605ea7 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 40 | UNITTYPE_CCD_SWITCH = 1, |
| 41 | }; |
| 42 | |
| 43 | enum { |
| 44 | HWVER_100 = 0, |
| 45 | HWVER_110 = 1, |
| 46 | HWVER_121 = 2, |
| 47 | HWVER_122 = 3, |
| 48 | }; |
| 49 | |
| 50 | int configure_gbit_phy(unsigned char addr) |
| 51 | { |
| 52 | unsigned short value; |
| 53 | |
| 54 | /* select page 2 */ |
| 55 | if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr, |
| 56 | PHYREG_PAGE_ADDRESS, 0x0002)) |
| 57 | goto err_out; |
| 58 | /* disable SGMII autonegotiation */ |
| 59 | if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr, |
| 60 | PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a)) |
| 61 | goto err_out; |
| 62 | /* select page 0 */ |
| 63 | if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr, |
| 64 | PHYREG_PAGE_ADDRESS, 0x0000)) |
| 65 | goto err_out; |
| 66 | /* switch from powerdown to normal operation */ |
| 67 | if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr, |
| 68 | PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value)) |
| 69 | goto err_out; |
| 70 | if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr, |
| 71 | PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004)) |
| 72 | goto err_out; |
| 73 | /* reset phy so settings take effect */ |
| 74 | if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr, |
| 75 | PHYREG_CONTROL, 0x9140)) |
| 76 | goto err_out; |
| 77 | |
| 78 | return 0; |
| 79 | |
| 80 | err_out: |
| 81 | printf("Error writing to the PHY addr=%02x\n", addr); |
| 82 | return -1; |
| 83 | } |
| 84 | |
| 85 | /* |
| 86 | * Check Board Identity: |
| 87 | */ |
| 88 | int checkboard(void) |
| 89 | { |
Dirk Eibach | 2da0fc0 | 2011-01-21 09:31:21 +0100 | [diff] [blame] | 90 | ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); |
Dirk Eibach | a605ea7 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 91 | char *s = getenv("serial#"); |
Dirk Eibach | 2da0fc0 | 2011-01-21 09:31:21 +0100 | [diff] [blame] | 92 | u16 versions = in_le16(&fpga->versions); |
| 93 | u16 fpga_version = in_le16(&fpga->fpga_version); |
| 94 | u16 fpga_features = in_le16(&fpga->fpga_features); |
Dirk Eibach | a605ea7 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 95 | unsigned unit_type; |
| 96 | unsigned hardware_version; |
| 97 | unsigned feature_channels; |
| 98 | unsigned feature_expansion; |
| 99 | |
| 100 | unit_type = (versions & 0xf000) >> 12; |
| 101 | hardware_version = versions & 0x000f; |
| 102 | feature_channels = fpga_features & 0x007f; |
| 103 | feature_expansion = fpga_features & (1<<15); |
| 104 | |
| 105 | printf("Board: "); |
| 106 | |
| 107 | printf("CATCenter Io"); |
| 108 | |
| 109 | if (s != NULL) { |
| 110 | puts(", serial# "); |
| 111 | puts(s); |
| 112 | } |
| 113 | puts("\n "); |
| 114 | |
| 115 | switch (unit_type) { |
| 116 | case UNITTYPE_CCD_SWITCH: |
| 117 | printf("CCD-Switch"); |
| 118 | break; |
| 119 | |
| 120 | default: |
| 121 | printf("UnitType %d(not supported)", unit_type); |
| 122 | break; |
| 123 | } |
| 124 | |
| 125 | switch (hardware_version) { |
| 126 | case HWVER_100: |
| 127 | printf(" HW-Ver 1.00\n"); |
| 128 | break; |
| 129 | |
| 130 | case HWVER_110: |
| 131 | printf(" HW-Ver 1.10\n"); |
| 132 | break; |
| 133 | |
| 134 | case HWVER_121: |
| 135 | printf(" HW-Ver 1.21\n"); |
| 136 | break; |
| 137 | |
| 138 | case HWVER_122: |
| 139 | printf(" HW-Ver 1.22\n"); |
| 140 | break; |
| 141 | |
| 142 | default: |
| 143 | printf(" HW-Ver %d(not supported)\n", |
| 144 | hardware_version); |
| 145 | break; |
| 146 | } |
| 147 | |
| 148 | printf(" FPGA V %d.%02d, features:", |
| 149 | fpga_version / 100, fpga_version % 100); |
| 150 | |
| 151 | printf(" %d channel(s)", feature_channels); |
| 152 | |
| 153 | printf(", expansion %ssupported\n", feature_expansion ? "" : "un"); |
| 154 | |
| 155 | return 0; |
| 156 | } |
| 157 | |
| 158 | /* |
| 159 | * setup Gbit PHYs |
| 160 | */ |
| 161 | int last_stage_init(void) |
| 162 | { |
Dirk Eibach | 2da0fc0 | 2011-01-21 09:31:21 +0100 | [diff] [blame] | 163 | ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); |
Dirk Eibach | a605ea7 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 164 | unsigned int k; |
| 165 | |
| 166 | miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME, |
| 167 | bb_miiphy_read, bb_miiphy_write); |
| 168 | |
| 169 | for (k = 0; k < 32; ++k) |
| 170 | configure_gbit_phy(k); |
| 171 | |
| 172 | /* take fpga serdes blocks out of reset */ |
Dirk Eibach | 2da0fc0 | 2011-01-21 09:31:21 +0100 | [diff] [blame] | 173 | out_le16(&fpga->quad_serdes_reset, 0); |
Dirk Eibach | a605ea7 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 174 | |
| 175 | return 0; |
| 176 | } |