blob: 99b13311cefde00ae3a849123c936a702e6140c6 [file] [log] [blame]
wdenkf5c5ef42005-04-05 16:26:47 +00001/*
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +02002 * (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de>
3 *
4 * (C) Copyright 2006
5 * Thomas Waehner, TQ-Systems GmbH, thomas.waehner@tqs.de.
6 *
Stefan Roesed96f41e2005-11-30 13:06:40 +01007 * (C) Copyright 2005
8 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 *
wdenkf5c5ef42005-04-05 16:26:47 +000010 * Copyright 2004 Freescale Semiconductor.
11 * (C) Copyright 2002,2003, Motorola Inc.
12 * Xianghua Xiao, (X.Xiao@motorola.com)
13 *
14 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
15 *
16 * See file CREDITS for list of people who contributed to this
17 * project.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Wolfgang Denk3cbd8232008-11-02 16:14:22 +010026 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenkf5c5ef42005-04-05 16:26:47 +000027 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA
33 */
34
wdenkf5c5ef42005-04-05 16:26:47 +000035#include <common.h>
36#include <pci.h>
37#include <asm/processor.h>
38#include <asm/immap_85xx.h>
Kumar Galac8514622009-04-02 13:22:48 -050039#include <asm/fsl_pci.h>
Wolfgang Grandeggerd9ee8432008-06-05 13:12:05 +020040#include <asm/io.h>
Kumar Gala5d27e022010-12-15 04:55:20 -060041#include <asm/fsl_serdes.h>
Peter Tyser06412752010-09-29 13:37:28 -050042#include <linux/compiler.h>
wdenkf5c5ef42005-04-05 16:26:47 +000043#include <ioports.h>
Stefan Roesed96f41e2005-11-30 13:06:40 +010044#include <flash.h>
Wolfgang Grandegger25991352008-06-05 13:12:06 +020045#include <libfdt.h>
46#include <fdt_support.h>
Ben Warren10efa022008-08-31 20:37:00 -070047#include <netdev.h>
wdenkf5c5ef42005-04-05 16:26:47 +000048
Wolfgang Denkd87080b2006-03-31 18:32:53 +020049DECLARE_GLOBAL_DATA_PTR;
50
Stefan Roesed96f41e2005-11-30 13:06:40 +010051extern flash_info_t flash_info[]; /* FLASH chips info */
wdenkf5c5ef42005-04-05 16:26:47 +000052
53void local_bus_init (void);
Stefan Roesef18e8742006-03-01 17:00:49 +010054ulong flash_get_size (ulong base, int banknum);
Wolfgang Denk966083e2006-07-21 15:24:56 +020055
Wolfgang Denkbd3143f2006-07-19 14:49:35 +020056#ifdef CONFIG_PS2MULT
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +020057void ps2mult_early_init (void);
Wolfgang Denkbd3143f2006-07-19 14:49:35 +020058#endif
wdenkf5c5ef42005-04-05 16:26:47 +000059
Stefan Roesed96f41e2005-11-30 13:06:40 +010060#ifdef CONFIG_CPM2
wdenkf5c5ef42005-04-05 16:26:47 +000061/*
62 * I/O Port configuration table
63 *
64 * if conf is 1, then that port pin will be configured at boot time
65 * according to the five values podr/pdir/ppar/psor/pdat for that entry
66 */
67
68const iop_conf_t iop_conf_tab[4][32] = {
69
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +020070 /* Port A: conf, ppar, psor, pdir, podr, pdat */
71 {
72 {1, 1, 1, 0, 0, 0}, /* PA31: FCC1 MII COL */
73 {1, 1, 1, 0, 0, 0}, /* PA30: FCC1 MII CRS */
74 {1, 1, 1, 1, 0, 0}, /* PA29: FCC1 MII TX_ER */
75 {1, 1, 1, 1, 0, 0}, /* PA28: FCC1 MII TX_EN */
76 {1, 1, 1, 0, 0, 0}, /* PA27: FCC1 MII RX_DV */
77 {1, 1, 1, 0, 0, 0}, /* PA26: FCC1 MII RX_ER */
78 {0, 1, 0, 1, 0, 0}, /* PA25: FCC1 ATMTXD[0] */
79 {0, 1, 0, 1, 0, 0}, /* PA24: FCC1 ATMTXD[1] */
80 {0, 1, 0, 1, 0, 0}, /* PA23: FCC1 ATMTXD[2] */
81 {0, 1, 0, 1, 0, 0}, /* PA22: FCC1 ATMTXD[3] */
82 {1, 1, 0, 1, 0, 0}, /* PA21: FCC1 MII TxD[3] */
83 {1, 1, 0, 1, 0, 0}, /* PA20: FCC1 MII TxD[2] */
84 {1, 1, 0, 1, 0, 0}, /* PA19: FCC1 MII TxD[1] */
85 {1, 1, 0, 1, 0, 0}, /* PA18: FCC1 MII TxD[0] */
86 {1, 1, 0, 0, 0, 0}, /* PA17: FCC1 MII RxD[0] */
87 {1, 1, 0, 0, 0, 0}, /* PA16: FCC1 MII RxD[1] */
88 {1, 1, 0, 0, 0, 0}, /* PA15: FCC1 MII RxD[2] */
89 {1, 1, 0, 0, 0, 0}, /* PA14: FCC1 MII RxD[3] */
90 {0, 1, 0, 0, 0, 0}, /* PA13: FCC1 ATMRXD[3] */
91 {0, 1, 0, 0, 0, 0}, /* PA12: FCC1 ATMRXD[2] */
92 {0, 1, 0, 0, 0, 0}, /* PA11: FCC1 ATMRXD[1] */
93 {0, 1, 0, 0, 0, 0}, /* PA10: FCC1 ATMRXD[0] */
94 {0, 1, 1, 1, 0, 0}, /* PA9 : FCC1 L1TXD */
95 {0, 1, 1, 0, 0, 0}, /* PA8 : FCC1 L1RXD */
96 {0, 0, 0, 1, 0, 0}, /* PA7 : PA7 */
97 {0, 1, 1, 1, 0, 0}, /* PA6 : TDM A1 L1RSYNC */
98 {0, 0, 0, 1, 0, 0}, /* PA5 : PA5 */
99 {0, 0, 0, 1, 0, 0}, /* PA4 : PA4 */
100 {0, 0, 0, 1, 0, 0}, /* PA3 : PA3 */
101 {0, 0, 0, 1, 0, 0}, /* PA2 : PA2 */
102 {0, 0, 0, 0, 0, 0}, /* PA1 : FREERUN */
103 {0, 0, 0, 1, 0, 0} /* PA0 : PA0 */
104 },
wdenkf5c5ef42005-04-05 16:26:47 +0000105
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200106 /* Port B: conf, ppar, psor, pdir, podr, pdat */
107 {
108 {1, 1, 0, 1, 0, 0}, /* PB31: FCC2 MII TX_ER */
109 {1, 1, 0, 0, 0, 0}, /* PB30: FCC2 MII RX_DV */
110 {1, 1, 1, 1, 0, 0}, /* PB29: FCC2 MII TX_EN */
111 {1, 1, 0, 0, 0, 0}, /* PB28: FCC2 MII RX_ER */
112 {1, 1, 0, 0, 0, 0}, /* PB27: FCC2 MII COL */
113 {1, 1, 0, 0, 0, 0}, /* PB26: FCC2 MII CRS */
114 {1, 1, 0, 1, 0, 0}, /* PB25: FCC2 MII TxD[3] */
115 {1, 1, 0, 1, 0, 0}, /* PB24: FCC2 MII TxD[2] */
116 {1, 1, 0, 1, 0, 0}, /* PB23: FCC2 MII TxD[1] */
117 {1, 1, 0, 1, 0, 0}, /* PB22: FCC2 MII TxD[0] */
118 {1, 1, 0, 0, 0, 0}, /* PB21: FCC2 MII RxD[0] */
119 {1, 1, 0, 0, 0, 0}, /* PB20: FCC2 MII RxD[1] */
120 {1, 1, 0, 0, 0, 0}, /* PB19: FCC2 MII RxD[2] */
121 {1, 1, 0, 0, 0, 0}, /* PB18: FCC2 MII RxD[3] */
122 {1, 1, 0, 0, 0, 0}, /* PB17: FCC3:RX_DIV */
123 {1, 1, 0, 0, 0, 0}, /* PB16: FCC3:RX_ERR */
124 {1, 1, 0, 1, 0, 0}, /* PB15: FCC3:TX_ERR */
125 {1, 1, 0, 1, 0, 0}, /* PB14: FCC3:TX_EN */
126 {1, 1, 0, 0, 0, 0}, /* PB13: FCC3:COL */
127 {1, 1, 0, 0, 0, 0}, /* PB12: FCC3:CRS */
128 {1, 1, 0, 0, 0, 0}, /* PB11: FCC3:RXD */
129 {1, 1, 0, 0, 0, 0}, /* PB10: FCC3:RXD */
130 {1, 1, 0, 0, 0, 0}, /* PB9 : FCC3:RXD */
131 {1, 1, 0, 0, 0, 0}, /* PB8 : FCC3:RXD */
132 {1, 1, 0, 1, 0, 0}, /* PB7 : FCC3:TXD */
133 {1, 1, 0, 1, 0, 0}, /* PB6 : FCC3:TXD */
134 {1, 1, 0, 1, 0, 0}, /* PB5 : FCC3:TXD */
135 {1, 1, 0, 1, 0, 0}, /* PB4 : FCC3:TXD */
136 {0, 0, 0, 0, 0, 0}, /* PB3 : pin doesn't exist */
137 {0, 0, 0, 0, 0, 0}, /* PB2 : pin doesn't exist */
138 {0, 0, 0, 0, 0, 0}, /* PB1 : pin doesn't exist */
139 {0, 0, 0, 0, 0, 0} /* PB0 : pin doesn't exist */
140 },
wdenkf5c5ef42005-04-05 16:26:47 +0000141
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200142 /* Port C: conf, ppar, psor, pdir, podr, pdat */
143 {
144 {0, 0, 0, 1, 0, 0}, /* PC31: PC31 */
145 {0, 0, 0, 1, 0, 0}, /* PC30: PC30 */
146 {0, 1, 1, 0, 0, 0}, /* PC29: SCC1 EN *CLSN */
147 {0, 0, 0, 1, 0, 0}, /* PC28: PC28 */
148 {0, 0, 0, 1, 0, 0}, /* PC27: UART Clock in */
149 {0, 0, 0, 1, 0, 0}, /* PC26: PC26 */
150 {0, 0, 0, 1, 0, 0}, /* PC25: PC25 */
151 {0, 0, 0, 1, 0, 0}, /* PC24: PC24 */
152 {0, 1, 0, 1, 0, 0}, /* PC23: ATMTFCLK */
153 {0, 1, 0, 0, 0, 0}, /* PC22: ATMRFCLK */
154 {1, 1, 0, 0, 0, 0}, /* PC21: SCC1 EN RXCLK */
155 {1, 1, 0, 0, 0, 0}, /* PC20: SCC1 EN TXCLK */
156 {1, 1, 0, 0, 0, 0}, /* PC19: FCC2 MII RX_CLK CLK13 */
157 {1, 1, 0, 0, 0, 0}, /* PC18: FCC Tx Clock (CLK14) */
158 {1, 1, 0, 0, 0, 0}, /* PC17: PC17 */
159 {1, 1, 0, 0, 0, 0}, /* PC16: FCC Tx Clock (CLK16) */
160 {0, 1, 0, 0, 0, 0}, /* PC15: PC15 */
161 {0, 1, 0, 0, 0, 0}, /* PC14: SCC1 EN *CD */
162 {0, 1, 0, 0, 0, 0}, /* PC13: PC13 */
163 {0, 1, 0, 1, 0, 0}, /* PC12: PC12 */
164 {0, 0, 0, 1, 0, 0}, /* PC11: LXT971 transmit control */
165 {0, 0, 0, 1, 0, 0}, /* PC10: FETHMDC */
166 {0, 0, 0, 0, 0, 0}, /* PC9 : FETHMDIO */
167 {0, 0, 0, 1, 0, 0}, /* PC8 : PC8 */
168 {0, 0, 0, 1, 0, 0}, /* PC7 : PC7 */
169 {0, 0, 0, 1, 0, 0}, /* PC6 : PC6 */
170 {0, 0, 0, 1, 0, 0}, /* PC5 : PC5 */
171 {0, 0, 0, 1, 0, 0}, /* PC4 : PC4 */
172 {0, 0, 0, 1, 0, 0}, /* PC3 : PC3 */
173 {0, 0, 0, 1, 0, 1}, /* PC2 : ENET FDE */
174 {0, 0, 0, 1, 0, 0}, /* PC1 : ENET DSQE */
175 {0, 0, 0, 1, 0, 0}, /* PC0 : ENET LBK */
176 },
wdenkf5c5ef42005-04-05 16:26:47 +0000177
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200178 /* Port D: conf, ppar, psor, pdir, podr, pdat */
179 {
Wolfgang Grandegger5d5bd832008-06-05 13:12:01 +0200180#ifdef CONFIG_TQM8560
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200181 {1, 1, 0, 0, 0, 0}, /* PD31: SCC1 EN RxD */
182 {1, 1, 1, 1, 0, 0}, /* PD30: SCC1 EN TxD */
183 {1, 1, 0, 1, 0, 0}, /* PD29: SCC1 EN TENA */
Wolfgang Grandegger5d5bd832008-06-05 13:12:01 +0200184#else /* !CONFIG_TQM8560 */
185 {0, 0, 0, 0, 0, 0}, /* PD31: PD31 */
186 {0, 0, 0, 0, 0, 0}, /* PD30: PD30 */
187 {0, 0, 0, 0, 0, 0}, /* PD29: PD29 */
188#endif /* CONFIG_TQM8560 */
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200189 {1, 1, 0, 0, 0, 0}, /* PD28: PD28 */
190 {1, 1, 0, 1, 0, 0}, /* PD27: PD27 */
191 {1, 1, 0, 1, 0, 0}, /* PD26: PD26 */
192 {0, 0, 0, 1, 0, 0}, /* PD25: PD25 */
193 {0, 0, 0, 1, 0, 0}, /* PD24: PD24 */
194 {0, 0, 0, 1, 0, 0}, /* PD23: PD23 */
195 {0, 0, 0, 1, 0, 0}, /* PD22: PD22 */
196 {0, 0, 0, 1, 0, 0}, /* PD21: PD21 */
197 {0, 0, 0, 1, 0, 0}, /* PD20: PD20 */
198 {0, 0, 0, 1, 0, 0}, /* PD19: PD19 */
199 {0, 0, 0, 1, 0, 0}, /* PD18: PD18 */
200 {0, 1, 0, 0, 0, 0}, /* PD17: FCC1 ATMRXPRTY */
201 {0, 1, 0, 1, 0, 0}, /* PD16: FCC1 ATMTXPRTY */
202 {0, 1, 1, 0, 1, 0}, /* PD15: I2C SDA */
203 {0, 0, 0, 1, 0, 0}, /* PD14: LED */
204 {0, 0, 0, 0, 0, 0}, /* PD13: PD13 */
205 {0, 0, 0, 0, 0, 0}, /* PD12: PD12 */
206 {0, 0, 0, 0, 0, 0}, /* PD11: PD11 */
207 {0, 0, 0, 0, 0, 0}, /* PD10: PD10 */
208 {0, 1, 0, 1, 0, 0}, /* PD9 : SMC1 TXD */
209 {0, 1, 0, 0, 0, 0}, /* PD8 : SMC1 RXD */
210 {0, 0, 0, 1, 0, 1}, /* PD7 : PD7 */
211 {0, 0, 0, 1, 0, 1}, /* PD6 : PD6 */
212 {0, 0, 0, 1, 0, 1}, /* PD5 : PD5 */
213 {0, 0, 0, 1, 0, 1}, /* PD4 : PD4 */
214 {0, 0, 0, 0, 0, 0}, /* PD3 : pin doesn't exist */
215 {0, 0, 0, 0, 0, 0}, /* PD2 : pin doesn't exist */
216 {0, 0, 0, 0, 0, 0}, /* PD1 : pin doesn't exist */
217 {0, 0, 0, 0, 0, 0} /* PD0 : pin doesn't exist */
218 }
wdenkf5c5ef42005-04-05 16:26:47 +0000219};
Stefan Roesed96f41e2005-11-30 13:06:40 +0100220#endif /* CONFIG_CPM2 */
wdenkf5c5ef42005-04-05 16:26:47 +0000221
Stefan Roesed96f41e2005-11-30 13:06:40 +0100222#define CASL_STRING1 "casl=xx"
223#define CASL_STRING2 "casl="
wdenkf5c5ef42005-04-05 16:26:47 +0000224
Stefan Roesed96f41e2005-11-30 13:06:40 +0100225static const int casl_table[] = { 20, 25, 30 };
226#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
227
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200228int cas_latency (void)
wdenkf5c5ef42005-04-05 16:26:47 +0000229{
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200230 char *s = getenv ("serial#");
Stefan Roesed96f41e2005-11-30 13:06:40 +0100231 int casl;
232 int val;
233 int i;
234
235 casl = CONFIG_DDR_DEFAULT_CL;
236
237 if (s != NULL) {
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200238 if (strncmp(s + strlen (s) - strlen (CASL_STRING1),
239 CASL_STRING2, strlen (CASL_STRING2)) == 0) {
240 val = simple_strtoul (s + strlen (s) - 2, NULL, 10);
Stefan Roesed96f41e2005-11-30 13:06:40 +0100241
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200242 for (i = 0; i < N_CASL; ++i) {
Stefan Roesed96f41e2005-11-30 13:06:40 +0100243 if (val == casl_table[i]) {
244 return val;
245 }
246 }
247 }
248 }
249
250 return casl;
wdenkf5c5ef42005-04-05 16:26:47 +0000251}
252
253int checkboard (void)
254{
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200255 char *s = getenv ("serial#");
Stefan Roesed96f41e2005-11-30 13:06:40 +0100256
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200257 printf ("Board: %s", CONFIG_BOARDNAME);
Stefan Roesed96f41e2005-11-30 13:06:40 +0100258 if (s != NULL) {
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200259 puts (", serial# ");
260 puts (s);
Stefan Roesed96f41e2005-11-30 13:06:40 +0100261 }
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200262 putc ('\n');
wdenkf5c5ef42005-04-05 16:26:47 +0000263
wdenkf5c5ef42005-04-05 16:26:47 +0000264 /*
265 * Initialize local bus.
266 */
267 local_bus_init ();
268
269 return 0;
270}
271
Stefan Roesed96f41e2005-11-30 13:06:40 +0100272int misc_init_r (void)
wdenkf5c5ef42005-04-05 16:26:47 +0000273{
Stefan Roesed96f41e2005-11-30 13:06:40 +0100274 /*
275 * Adjust flash start and offset to detected values
276 */
277 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
278 gd->bd->bi_flashoffset = 0;
Stefan Roese9d2a8732005-08-31 12:55:50 +0200279
Stefan Roesed96f41e2005-11-30 13:06:40 +0100280 /*
Wolfgang Grandegger45dee2e2008-06-05 13:12:03 +0200281 * Recalculate CS configuration if second FLASH bank is available
Stefan Roesed96f41e2005-11-30 13:06:40 +0100282 */
Wolfgang Grandegger45dee2e2008-06-05 13:12:03 +0200283 if (flash_info[0].size > 0) {
Becky Brucef51cdaf2010-06-17 11:37:20 -0500284 set_lbc_or(1, ((-flash_info[0].size) & 0xffff8000) |
285 (CONFIG_SYS_OR1_PRELIM & 0x00007fff));
286 set_lbc_br(1, gd->bd->bi_flashstart |
287 (CONFIG_SYS_BR1_PRELIM & 0x00007fff));
wdenkf5c5ef42005-04-05 16:26:47 +0000288 /*
Wolfgang Grandegger45dee2e2008-06-05 13:12:03 +0200289 * Re-check to get correct base address for bank 1
wdenkf5c5ef42005-04-05 16:26:47 +0000290 */
Wolfgang Grandegger45dee2e2008-06-05 13:12:03 +0200291 flash_get_size (gd->bd->bi_flashstart, 0);
292 } else {
Becky Brucef51cdaf2010-06-17 11:37:20 -0500293 set_lbc_or(1, 0);
294 set_lbc_br(1, 0);
wdenkf5c5ef42005-04-05 16:26:47 +0000295 }
wdenkf5c5ef42005-04-05 16:26:47 +0000296
wdenkf5c5ef42005-04-05 16:26:47 +0000297 /*
Wolfgang Grandegger45dee2e2008-06-05 13:12:03 +0200298 * If bank 1 is equipped, bank 0 is mapped after bank 1
wdenkf5c5ef42005-04-05 16:26:47 +0000299 */
Becky Brucef51cdaf2010-06-17 11:37:20 -0500300 set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) |
301 (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
Becky Bruceb1b76462010-11-11 11:33:05 -0600302 set_lbc_br(0, (gd->bd->bi_flashstart + flash_info[0].size) |
Becky Brucef51cdaf2010-06-17 11:37:20 -0500303 (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
304
Wolfgang Grandegger45dee2e2008-06-05 13:12:03 +0200305 /*
306 * Re-check to get correct base address for bank 0
307 */
308 flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1);
wdenkf5c5ef42005-04-05 16:26:47 +0000309
Wolfgang Grandegger45dee2e2008-06-05 13:12:03 +0200310 /*
311 * Re-do flash protection upon new addresses
312 */
313 flash_protect (FLAG_PROTECT_CLEAR,
314 gd->bd->bi_flashstart, 0xffffffff,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
Stefan Roesed96f41e2005-11-30 13:06:40 +0100316
Wolfgang Grandegger45dee2e2008-06-05 13:12:03 +0200317 /* Monitor protection ON by default */
318 flash_protect (FLAG_PROTECT_SET,
Wolfgang Grandegger31ca9112009-02-11 18:38:19 +0100319 CONFIG_SYS_MONITOR_BASE, 0xffffffff,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
Stefan Roesed96f41e2005-11-30 13:06:40 +0100321
Wolfgang Grandegger45dee2e2008-06-05 13:12:03 +0200322 /* Environment protection ON by default */
323 flash_protect (FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200324 CONFIG_ENV_ADDR,
325 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
Stefan Roesed96f41e2005-11-30 13:06:40 +0100327
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200328#ifdef CONFIG_ENV_ADDR_REDUND
Wolfgang Grandegger45dee2e2008-06-05 13:12:03 +0200329 /* Redundant environment protection ON by default */
330 flash_protect (FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200331 CONFIG_ENV_ADDR_REDUND,
Wolfgang Denkdfcd7f22009-05-15 00:16:03 +0200332 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
Wolfgang Grandegger45dee2e2008-06-05 13:12:03 +0200334#endif
Stefan Roesed96f41e2005-11-30 13:06:40 +0100335
336 return 0;
wdenkf5c5ef42005-04-05 16:26:47 +0000337}
338
Wolfgang Grandeggerd9ee8432008-06-05 13:12:05 +0200339#ifdef CONFIG_CAN_DRIVER
340/*
341 * Initialize UPMC RAM
342 */
343static void upmc_write (u_char addr, uint val)
344{
Becky Brucef51cdaf2010-06-17 11:37:20 -0500345 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Wolfgang Grandeggerd9ee8432008-06-05 13:12:05 +0200346
347 out_be32 (&lbc->mdr, val);
348
349 clrsetbits_be32(&lbc->mcmr, MxMR_MAD_MSK,
350 MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
351
352 /* dummy access to perform write */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353 out_8 ((void __iomem *)CONFIG_SYS_CAN_BASE, 0);
Wolfgang Grandeggerd9ee8432008-06-05 13:12:05 +0200354
355 /* normal operation */
356 clrbits_be32(&lbc->mcmr, MxMR_OP_WARR);
357}
358#endif /* CONFIG_CAN_DRIVER */
359
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200360uint get_lbc_clock (void)
361{
Becky Brucef51cdaf2010-06-17 11:37:20 -0500362 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200363 sys_info_t sys_info;
Trent Piephoa5d212a2008-12-03 15:16:34 -0800364 ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200365
366 get_sys_info (&sys_info);
367
368 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
369#ifdef CONFIG_MPC8548
370 /*
371 * Yes, the entire PQ38 family use the same
372 * bit-representation for twice the clock divider value.
373 */
374 clkdiv *= 2;
375#endif
376 return sys_info.freqSystemBus / clkdiv;
377 }
378
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379 puts("Invalid clock divider value in CONFIG_SYS_LBC_LCRR\n");
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200380
381 return 0;
382}
383
wdenkf5c5ef42005-04-05 16:26:47 +0000384/*
385 * Initialize Local Bus
386 */
wdenkf5c5ef42005-04-05 16:26:47 +0000387void local_bus_init (void)
388{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Becky Brucef51cdaf2010-06-17 11:37:20 -0500390 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200391 uint lbc_mhz = get_lbc_clock () / 1000000;
wdenkf5c5ef42005-04-05 16:26:47 +0000392
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200393#ifdef CONFIG_MPC8548
394 uint svr = get_svr ();
395 uint lcrr;
396
397 /*
398 * MPC revision < 2.0
399 * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1:
400 * Modify engineering use only register at address 0xE_0F20.
401 * "1. Read register at offset 0xE_0F20
402 * 2. And value with 0x0000_FFFF
403 * 3. OR result with 0x0000_0004
404 * 4. Write result back to offset 0xE_0F20."
405 *
406 * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2:
407 * Modify engineering use only register at address 0xE_0F20.
408 * "1. Read register at offset 0xE_0F20
409 * 2. And value with 0xFFFF_FFDF
410 * 3. Write result back to offset 0xE_0F20."
411 *
412 * Since it is the same register, we do the modification in one step.
413 */
414 if (SVR_MAJ (svr) < 2) {
415 uint dummy = gur->lbiuiplldcr1;
416 dummy &= 0x0000FFDF;
417 dummy |= 0x00000004;
418 gur->lbiuiplldcr1 = dummy;
419 }
420
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421 lcrr = CONFIG_SYS_LBC_LCRR;
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200422
423 /*
424 * Local Bus Clock > 83.3 MHz. According to timing
425 * specifications set LCRR[EADC] to 2 delay cycles.
426 */
427 if (lbc_mhz > 83) {
428 lcrr &= ~LCRR_EADC;
429 lcrr |= LCRR_EADC_2;
430 }
431
432 /*
433 * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
434 * disable PLL bypass for Local Bus Clock > 83 MHz.
435 */
436 if (lbc_mhz >= 66)
437 lcrr &= (~LCRR_DBYP); /* DLL Enabled */
438
439 else
440 lcrr |= LCRR_DBYP; /* DLL Bypass */
441
442 lbc->lcrr = lcrr;
443 asm ("sync;isync;msync");
444
445 /*
446 * According to MPC8548ERMAD Rev.1.3 read back LCRR
447 * and terminate with isync
448 */
449 lcrr = lbc->lcrr;
450 asm ("isync;");
451
452 /* let DLL stabilize */
453 udelay (500);
454
455#else /* !CONFIG_MPC8548 */
wdenkf5c5ef42005-04-05 16:26:47 +0000456
457 /*
458 * Errata LBC11.
459 * Fix Local Bus clock glitch when DLL is enabled.
460 *
Wolfgang Denk8ed44d92008-10-19 02:35:50 +0200461 * If localbus freq is < 66MHz, DLL bypass mode must be used.
462 * If localbus freq is > 133MHz, DLL can be safely enabled.
wdenkf5c5ef42005-04-05 16:26:47 +0000463 * Between 66 and 133, the DLL is enabled with an override workaround.
464 */
465
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200466 if (lbc_mhz < 66) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467 lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */
Stefan Roesef2302d42008-08-06 14:05:38 +0200468 lbc->ltedr = LTEDR_BMD | LTEDR_PARD | LTEDR_WPD | LTEDR_WARA |
469 LTEDR_RAWA | LTEDR_CSD; /* Disable all error checking */
wdenkf5c5ef42005-04-05 16:26:47 +0000470
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200471 } else if (lbc_mhz >= 133) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200472 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
wdenkf5c5ef42005-04-05 16:26:47 +0000473
474 } else {
475 /*
476 * On REV1 boards, need to change CLKDIV before enable DLL.
477 * Default CLKDIV is 8, change it to 4 temporarily.
478 */
479 uint pvr = get_pvr ();
480 uint temp_lbcdll = 0;
481
482 if (pvr == PVR_85xx_REV1) {
483 /* FIXME: Justify the high bit here. */
484 lbc->lcrr = 0x10000004;
485 }
486
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200487 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
wdenkf5c5ef42005-04-05 16:26:47 +0000488 udelay (200);
489
490 /*
491 * Sample LBC DLL ctrl reg, upshift it to set the
492 * override bits.
493 */
494 temp_lbcdll = gur->lbcdllcr;
495 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
496 asm ("sync;isync;msync");
497 }
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200498#endif /* !CONFIG_MPC8548 */
Wolfgang Grandeggerd9ee8432008-06-05 13:12:05 +0200499
500#ifdef CONFIG_CAN_DRIVER
501 /*
502 * According to timing specifications EAD must be
503 * set if Local Bus Clock is > 83 MHz.
504 */
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200505 if (lbc_mhz > 83)
Becky Brucef51cdaf2010-06-17 11:37:20 -0500506 set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
Wolfgang Grandeggerd9ee8432008-06-05 13:12:05 +0200507 else
Becky Brucef51cdaf2010-06-17 11:37:20 -0500508 set_lbc_or(2, CONFIG_SYS_OR2_CAN);
509 set_lbc_br(2, CONFIG_SYS_BR2_CAN);
Wolfgang Grandeggerd9ee8432008-06-05 13:12:05 +0200510
511 /* LGPL4 is UPWAIT */
512 out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
513
514 /* Initialize UPMC for CAN: single read */
515 upmc_write (0x00, 0xFFFFED00);
516 upmc_write (0x01, 0xCCFFCC00);
517 upmc_write (0x02, 0x00FFCF00);
518 upmc_write (0x03, 0x00FFCF00);
519 upmc_write (0x04, 0x00FFDC00);
520 upmc_write (0x05, 0x00FFCF00);
521 upmc_write (0x06, 0x00FFED00);
522 upmc_write (0x07, 0x3FFFCC07);
523
524 /* Initialize UPMC for CAN: single write */
525 upmc_write (0x18, 0xFFFFED00);
526 upmc_write (0x19, 0xCCFFEC00);
527 upmc_write (0x1A, 0x00FFED80);
528 upmc_write (0x1B, 0x00FFED80);
529 upmc_write (0x1C, 0x00FFFC00);
530 upmc_write (0x1D, 0x0FFFEC00);
531 upmc_write (0x1E, 0x0FFFEF00);
532 upmc_write (0x1F, 0x3FFFEC05);
533#endif /* CONFIG_CAN_DRIVER */
wdenkf5c5ef42005-04-05 16:26:47 +0000534}
535
wdenkf5c5ef42005-04-05 16:26:47 +0000536/*
537 * Initialize PCI Devices, report devices found.
538 */
539
Wolfgang Grandeggera3182342009-02-11 18:38:20 +0100540#ifdef CONFIG_PCI1
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200541static struct pci_controller pci1_hose;
Wolfgang Grandeggera3182342009-02-11 18:38:20 +0100542#endif /* CONFIG_PCI1 */
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200543
Peter Tyser06412752010-09-29 13:37:28 -0500544void pci_init_board (void)
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200545{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200546 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Kumar Gala48f27912010-12-17 10:23:45 -0600547 int first_free_busno = 0;
Wolfgang Grandeggera3182342009-02-11 18:38:20 +0100548#ifdef CONFIG_PCI1
Kumar Gala48f27912010-12-17 10:23:45 -0600549 struct fsl_pci_info pci_info;
550 int pcie_ep;
551
552 u32 devdisr = in_be32(&gur->devdisr);
553
Peter Tyser06412752010-09-29 13:37:28 -0500554 uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
555 uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200556 uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */
Peter Tyser06412752010-09-29 13:37:28 -0500557 uint pci_clk_sel = in_be32(&gur->porpllsr) & MPC85xx_PORDEVSR_PCI1_SPD;
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200558
Peter Tyser06412752010-09-29 13:37:28 -0500559 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
Kumar Gala48f27912010-12-17 10:23:45 -0600560 SET_STD_PCI_INFO(pci_info, 1);
561 set_next_law(pci_info.mem_phys,
562 law_size_bits(pci_info.mem_size), pci_info.law);
563 set_next_law(pci_info.io_phys,
564 law_size_bits(pci_info.io_size), pci_info.law);
565
566 pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs);
Peter Tyser8ca78f22010-10-29 17:59:24 -0500567 printf("PCI1: %d bit, %s MHz, %s, %s, %s\n",
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200568 (pci_32) ? 32 : 64,
569 (pci_speed == 33333333) ? "33" :
570 (pci_speed == 66666666) ? "66" : "unknown",
571 pci_clk_sel ? "sync" : "async",
Peter Tyser06412752010-09-29 13:37:28 -0500572 pcie_ep ? "agent" : "host",
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200573 pci_arb ? "arbiter" : "external-arbiter");
Kumar Gala48f27912010-12-17 10:23:45 -0600574 first_free_busno = fsl_pci_init_port(&pci_info,
Peter Tyser06412752010-09-29 13:37:28 -0500575 &pci1_hose, first_free_busno);
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200576#ifdef CONFIG_PCIX_CHECK
Peter Tyser06412752010-09-29 13:37:28 -0500577 if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1)) {
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200578 ushort reg16 =
579 PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
580 PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
Peter Tyser06412752010-09-29 13:37:28 -0500581 uint dev = PCI_BDF(0, 0, 0);
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200582
583 /* PCI-X init */
584 if (CONFIG_SYS_CLK_FREQ < 66000000)
585 puts ("PCI-X will only work at 66 MHz\n");
586
Peter Tyser06412752010-09-29 13:37:28 -0500587 pci_write_config_word(dev, PCIX_COMMAND, reg16);
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200588 }
wdenkf5c5ef42005-04-05 16:26:47 +0000589#endif
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200590 } else {
Peter Tyser8ca78f22010-10-29 17:59:24 -0500591 printf("PCI1: disabled\n");
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200592 }
Peter Tyser06412752010-09-29 13:37:28 -0500593#else
594 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
595#endif
wdenkf5c5ef42005-04-05 16:26:47 +0000596
Kumar Gala48f27912010-12-17 10:23:45 -0600597 fsl_pcie_init_board(first_free_busno);
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200598}
wdenkf5c5ef42005-04-05 16:26:47 +0000599
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200600#ifdef CONFIG_OF_BOARD_SETUP
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200601void ft_board_setup (void *blob, bd_t *bd)
602{
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200603 ft_cpu_setup (blob, bd);
604
Kumar Gala6525d512010-07-08 22:37:44 -0500605 FT_FSL_PCI_SETUP;
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200606}
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200607#endif /* CONFIG_OF_BOARD_SETUP */
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200608
Wolfgang Denkbc8bb6d2006-06-16 16:40:54 +0200609#ifdef CONFIG_BOARD_EARLY_INIT_R
610int board_early_init_r (void)
611{
612#ifdef CONFIG_PS2MULT
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200613 ps2mult_early_init ();
Wolfgang Denkbc8bb6d2006-06-16 16:40:54 +0200614#endif /* CONFIG_PS2MULT */
615 return (0);
616}
617#endif /* CONFIG_BOARD_EARLY_INIT_R */
Ben Warren10efa022008-08-31 20:37:00 -0700618
619int board_eth_init(bd_t *bis)
620{
621 cpu_eth_init(bis); /* Intialize TSECs first */
622 return pci_eth_init(bis);
623}