| Ying-Chun Liu (PaulLiu) | ddb56f3 | 2022-02-08 09:22:38 +0800 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_SPL_SYS_ICACHE_OFF=y |
| 3 | CONFIG_SPL_SYS_DCACHE_OFF=y |
| 4 | CONFIG_ARCH_IMX8M=y |
| 5 | CONFIG_SYS_TEXT_BASE=0x40200000 |
| 6 | CONFIG_SYS_LOAD_ADDR=0x40480000 |
| 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 9 | CONFIG_SYS_MALLOC_F_LEN=0x10000 |
| 10 | CONFIG_NR_DRAM_BANKS=3 |
| 11 | CONFIG_ENV_SIZE=0x2000 |
| 12 | CONFIG_ENV_OFFSET=0x400000 |
| 13 | CONFIG_ENV_SECT_SIZE=0x10000 |
| 14 | CONFIG_SYS_I2C_MXC_I2C1=y |
| 15 | CONFIG_SYS_I2C_MXC_I2C2=y |
| 16 | CONFIG_SYS_I2C_MXC_I2C3=y |
| 17 | CONFIG_SYS_I2C_MXC_I2C4=y |
| 18 | CONFIG_DM_GPIO=y |
| 19 | CONFIG_SPL_TEXT_BASE=0x920000 |
| 20 | CONFIG_TARGET_IMX8MP_RSB3720A1_4G=y |
| 21 | CONFIG_SPL_MMC=y |
| 22 | CONFIG_SPL_SERIAL=y |
| 23 | CONFIG_SPL_DRIVERS_MISC=y |
| 24 | CONFIG_SPL=y |
| 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 |
| 26 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-rsb3720-a1" |
| 27 | CONFIG_DISTRO_DEFAULTS=y |
| 28 | CONFIG_FIT=y |
| 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 |
| 30 | CONFIG_FIT_SIGNATURE=y |
| 31 | CONFIG_SPL_LOAD_FIT=y |
| 32 | # CONFIG_USE_SPL_FIT_GENERATOR is not set |
| 33 | CONFIG_OF_BOARD_SETUP=y |
| 34 | CONFIG_OF_SYSTEM_SETUP=y |
| 35 | CONFIG_IMX_CONFIG="board/advantech/imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg" |
| 36 | CONFIG_DEFAULT_FDT_FILE="imx8mp-rsb3720-a1.dtb" |
| 37 | CONFIG_ARCH_MISC_INIT=y |
| 38 | CONFIG_BOARD_EARLY_INIT_F=y |
| 39 | CONFIG_BOARD_LATE_INIT=y |
| 40 | CONFIG_SPL_BOARD_INIT=y |
| 41 | CONFIG_SPL_BOOTROM_SUPPORT=y |
| 42 | CONFIG_SPL_SEPARATE_BSS=y |
| 43 | CONFIG_SYS_PROMPT="u-boot=> " |
| 44 | CONFIG_CMD_BOOTEFI_SELFTEST=y |
| 45 | CONFIG_CMD_ERASEENV=y |
| 46 | CONFIG_CMD_NVEDIT_EFI=y |
| 47 | CONFIG_CMD_EEPROM=y |
| 48 | CONFIG_CMD_MEMTEST=y |
| 49 | CONFIG_CMD_SHA1SUM=y |
| 50 | CONFIG_CMD_BIND=y |
| 51 | CONFIG_CMD_CLK=y |
| 52 | CONFIG_CMD_DFU=y |
| 53 | CONFIG_CMD_FUSE=y |
| 54 | CONFIG_CMD_GPIO=y |
| 55 | CONFIG_CMD_GPT=y |
| 56 | CONFIG_CMD_I2C=y |
| 57 | CONFIG_CMD_MMC=y |
| 58 | CONFIG_CMD_READ=y |
| 59 | CONFIG_CMD_SNTP=y |
| 60 | CONFIG_CMD_BMP=y |
| 61 | CONFIG_CMD_CACHE=y |
| 62 | CONFIG_CMD_EFIDEBUG=y |
| 63 | CONFIG_CMD_RTC=y |
| 64 | CONFIG_CMD_TIME=y |
| 65 | CONFIG_CMD_GETTIME=y |
| 66 | CONFIG_CMD_TIMER=y |
| 67 | CONFIG_CMD_REGULATOR=y |
| 68 | CONFIG_CMD_EXT4_WRITE=y |
| 69 | CONFIG_OF_CONTROL=y |
| 70 | CONFIG_SPL_OF_CONTROL=y |
| 71 | CONFIG_ENV_OVERWRITE=y |
| 72 | CONFIG_ENV_IS_IN_MMC=y |
| 73 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
| 74 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 75 | CONFIG_SYS_MMC_ENV_DEV=2 |
| 76 | CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 |
| 77 | CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y |
| 78 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
| 79 | CONFIG_NET_RANDOM_ETHADDR=y |
| 80 | CONFIG_SPL_DM=y |
| 81 | CONFIG_REGMAP=y |
| 82 | CONFIG_SYSCON=y |
| 83 | CONFIG_CLK_COMPOSITE_CCF=y |
| 84 | CONFIG_CLK_IMX8MP=y |
| 85 | CONFIG_DFU_TFTP=y |
| 86 | CONFIG_DFU_MMC=y |
| 87 | CONFIG_DFU_RAM=y |
| 88 | CONFIG_DFU_SF=y |
| 89 | CONFIG_UDP_FUNCTION_FASTBOOT=y |
| 90 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
| 91 | CONFIG_FASTBOOT_BUF_SIZE=0x5000000 |
| 92 | CONFIG_FASTBOOT_FLASH=y |
| 93 | CONFIG_FASTBOOT_UUU_SUPPORT=y |
| 94 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 |
| 95 | CONFIG_MXC_GPIO=y |
| 96 | CONFIG_DM_PCA953X=y |
| 97 | CONFIG_DM_I2C=y |
| 98 | CONFIG_SYS_I2C_MXC=y |
| 99 | CONFIG_LED=y |
| 100 | CONFIG_LED_GPIO=y |
| 101 | CONFIG_SUPPORT_EMMC_RPMB=y |
| 102 | CONFIG_SUPPORT_EMMC_BOOT=y |
| 103 | CONFIG_MMC_IO_VOLTAGE=y |
| 104 | CONFIG_MMC_UHS_SUPPORT=y |
| 105 | CONFIG_MMC_HS400_ES_SUPPORT=y |
| 106 | CONFIG_MMC_HS400_SUPPORT=y |
| 107 | CONFIG_FSL_ESDHC_IMX=y |
| 108 | CONFIG_FSL_USDHC=y |
| 109 | CONFIG_DM_SPI_FLASH=y |
| 110 | CONFIG_SF_DEFAULT_MODE=0 |
| 111 | CONFIG_SF_DEFAULT_SPEED=40000000 |
| 112 | CONFIG_SPI_FLASH_BAR=y |
| 113 | CONFIG_SPI_FLASH_STMICRO=y |
| 114 | CONFIG_PHY_REALTEK=y |
| 115 | CONFIG_DM_ETH_PHY=y |
| 116 | CONFIG_DM_ETH=y |
| 117 | CONFIG_PHY_GIGE=y |
| 118 | CONFIG_DWC_ETH_QOS=y |
| 119 | CONFIG_DWC_ETH_QOS_IMX=y |
| 120 | CONFIG_FEC_MXC=y |
| 121 | CONFIG_MII=y |
| 122 | CONFIG_PINCTRL=y |
| 123 | CONFIG_PINCTRL_IMX8M=y |
| 124 | CONFIG_DM_REGULATOR=y |
| 125 | CONFIG_DM_REGULATOR_FIXED=y |
| 126 | CONFIG_DM_REGULATOR_GPIO=y |
| 127 | CONFIG_DM_RTC=y |
| 128 | CONFIG_RTC_S35392A=y |
| 129 | CONFIG_MXC_UART=y |
| 130 | CONFIG_SPI=y |
| 131 | CONFIG_DM_SPI=y |
| 132 | CONFIG_SYSRESET=y |
| 133 | CONFIG_SYSRESET_PSCI=y |
| 134 | CONFIG_DM_THERMAL=y |
| 135 | CONFIG_SDP_LOADADDR=0x40480000 |
| 136 | CONFIG_DM_VIDEO=y |
| 137 | CONFIG_SYS_WHITE_ON_BLACK=y |
| 138 | CONFIG_SHA512_ALGO=y |
| 139 | CONFIG_SHA512=y |
| 140 | CONFIG_SHA384=y |
| 141 | CONFIG_LZO=y |
| 142 | CONFIG_BZIP2=y |
| 143 | CONFIG_OF_LIBFDT_OVERLAY=y |
| 144 | CONFIG_EFI_SET_TIME=y |
| 145 | CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y |
| 146 | CONFIG_EFI_CAPSULE_ON_DISK=y |
| 147 | CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y |
| 148 | CONFIG_EFI_SECURE_BOOT=y |
| 149 | CONFIG_SYS_MALLOC_LEN=0x2000000 |
| 150 | CONFIG_SPL_GPIO=y |
| 151 | CONFIG_SPL_POWER_I2C=y |
| 152 | CONFIG_SPL_DM_I2C=y |
| 153 | CONFIG_SPL_DM_PMIC=y |
| 154 | CONFIG_SPL_DM_PMIC_PCA9450=y |
| 155 | CONFIG_DM_PMIC=y |
| 156 | CONFIG_DM_PMIC_PCA9450=y |
| 157 | CONFIG_SPL_DM_REGULATOR=y |
| 158 | CONFIG_SPL_DM_REGULATOR_FIXED=y |
| 159 | CONFIG_SPL_DM_REGULATOR_GPIO=y |
| 160 | CONFIG_SPL_POWER=y |
| 161 | CONFIG_SPL_I2C=y |
| 162 | CONFIG_IMX_WATCHDOG=y |
| 163 | CONFIG_SYSRESET_WATCHDOG=y |
| 164 | CONFIG_SPL_PINCTRL=y |
| 165 | CONFIG_SPL_SYS_MALLOC_SIMPLE=y |
| 166 | CONFIG_SPL_WATCHDOG=y |
| 167 | CONFIG_SPL_SYSRESET=y |