| Stefan Roese | 5fef24c | 2020-06-30 12:08:58 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Marvell / Cavium Inc. EVB CN7300 |
| 4 | */ |
| 5 | |
| 6 | /dts-v1/; |
| 7 | |
| Stefan Roese | a078c65 | 2020-07-30 13:56:17 +0200 | [diff] [blame^] | 8 | #include "mrvl,cn73xx.dtsi" |
| Stefan Roese | 5fef24c | 2020-06-30 12:08:58 +0200 | [diff] [blame] | 9 | |
| 10 | / { |
| 11 | model = "cavium,ebb7304"; |
| 12 | compatible = "cavium,ebb7304"; |
| 13 | |
| 14 | aliases { |
| 15 | serial0 = &uart0; |
| 16 | }; |
| 17 | |
| 18 | chosen { |
| 19 | stdout-path = &uart0; |
| 20 | }; |
| 21 | }; |
| 22 | |
| 23 | &bootbus { |
| 24 | /* |
| 25 | * bootbus CS0 for CFI flash is remapped (0x1fc0.0000 -> 1f40.0000) |
| 26 | * as the initial size is too small for the 8MiB flash device |
| 27 | */ |
| 28 | ranges = <0 0 0 0x1f400000 0xc00000>, |
| 29 | <1 0 0x10000 0x10000000 0>, |
| 30 | <2 0 0x10000 0x20000000 0>, |
| 31 | <3 0 0x10000 0x30000000 0>, |
| 32 | <4 0 0 0x1d020000 0x10000>, |
| 33 | <5 0 0x10000 0x50000000 0>, |
| 34 | <6 0 0x10000 0x60000000 0>, |
| 35 | <7 0 0x10000 0x70000000 0>; |
| 36 | |
| 37 | cavium,cs-config@0 { |
| 38 | compatible = "cavium,octeon-3860-bootbus-config"; |
| 39 | cavium,cs-index = <0>; |
| 40 | cavium,t-adr = <10>; |
| 41 | cavium,t-ce = <50>; |
| 42 | cavium,t-oe = <50>; |
| 43 | cavium,t-we = <35>; |
| 44 | cavium,t-rd-hld = <25>; |
| 45 | cavium,t-wr-hld = <35>; |
| 46 | cavium,t-pause = <0>; |
| 47 | cavium,t-wait = <50>; |
| 48 | cavium,t-page = <30>; |
| 49 | cavium,t-rd-dly = <0>; |
| 50 | cavium,page-mode = <1>; |
| 51 | cavium,pages = <8>; |
| 52 | cavium,bus-width = <8>; |
| 53 | }; |
| 54 | |
| 55 | cavium,cs-config@4 { |
| 56 | compatible = "cavium,octeon-3860-bootbus-config"; |
| 57 | cavium,cs-index = <4>; |
| 58 | cavium,t-adr = <10>; |
| 59 | cavium,t-ce = <10>; |
| 60 | cavium,t-oe = <160>; |
| 61 | cavium,t-we = <100>; |
| 62 | cavium,t-rd-hld = <10>; |
| 63 | cavium,t-wr-hld = <0>; |
| 64 | cavium,t-pause = <50>; |
| 65 | cavium,t-wait = <50>; |
| 66 | cavium,t-page = <10>; |
| 67 | cavium,t-rd-dly = <10>; |
| 68 | cavium,pages = <0>; |
| 69 | cavium,bus-width = <8>; |
| 70 | }; |
| 71 | |
| 72 | flash0: nor@0,0 { |
| 73 | compatible = "cfi-flash"; |
| 74 | reg = <0 0 0x800000>; |
| 75 | #address-cells = <1>; |
| 76 | #size-cells = <1>; |
| 77 | partition@0 { |
| 78 | label = "bootloader"; |
| 79 | reg = <0 0x340000>; |
| 80 | read-only; |
| 81 | }; |
| 82 | partition@300000 { |
| 83 | label = "storage"; |
| 84 | reg = <0x340000 0x4be000>; |
| 85 | }; |
| 86 | partition@7fe000 { |
| 87 | label = "environment"; |
| 88 | reg = <0x7fe000 0x2000>; |
| 89 | read-only; |
| 90 | }; |
| 91 | }; |
| 92 | }; |
| 93 | |
| 94 | &uart0 { |
| 95 | clock-frequency = <1200000000>; |
| 96 | }; |
| Stefan Roese | 7ab9328 | 2020-07-30 13:56:15 +0200 | [diff] [blame] | 97 | |
| 98 | &i2c0 { |
| 99 | u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */ |
| 100 | clock-frequency = <100000>; |
| 101 | }; |
| 102 | |
| 103 | &i2c1 { |
| 104 | u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */ |
| 105 | clock-frequency = <100000>; |
| 106 | }; |