blob: ec3978a70aa7ce05f5f8d20519d8b15224bdac63 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Chunhe Lan373762c2015-03-20 17:08:54 +08002/*
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 *
5 * Author: Chunhe Lan <Chunhe.Lan@freescale.com>
Chunhe Lan373762c2015-03-20 17:08:54 +08006 */
7
8#include <common.h>
Simon Glass24b852a2015-11-08 23:47:45 -07009#include <console.h>
Simon Glassf3998fd2019-08-02 09:44:25 -060010#include <env_internal.h>
Chunhe Lan373762c2015-03-20 17:08:54 +080011#include <asm/spl.h>
12#include <malloc.h>
13#include <ns16550.h>
14#include <nand.h>
15#include <mmc.h>
16#include <fsl_esdhc.h>
17#include <i2c.h>
18
19#include "t4rdb.h"
20
21#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
22
23DECLARE_GLOBAL_DATA_PTR;
24
25phys_size_t get_effective_memsize(void)
26{
27 return CONFIG_SYS_L3_SIZE;
28}
29
30unsigned long get_board_sys_clk(void)
31{
32 return CONFIG_SYS_CLK_FREQ;
33}
34
35unsigned long get_board_ddr_clk(void)
36{
37 return CONFIG_DDR_CLK_FREQ;
38}
39
40void board_init_f(ulong bootflag)
41{
42 u32 plat_ratio, sys_clk, ccb_clk;
43 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
44
45 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
46 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
47
48 /* Update GD pointer */
49 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
50
51 /* compiler optimization barrier needed for GCC >= 3.4 */
52 __asm__ __volatile__("" : : : "memory");
53
54 console_init_f();
55
56 /* initialize selected port with appropriate baud rate */
57 sys_clk = get_board_sys_clk();
58 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
59 ccb_clk = sys_clk * plat_ratio / 2;
60
61 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
62 ccb_clk / 16 / CONFIG_BAUDRATE);
63
64 puts("\nSD boot...\n");
65
66 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
67}
68
69void board_init_r(gd_t *gd, ulong dest_addr)
70{
71 bd_t *bd;
72
73 bd = (bd_t *)(gd + sizeof(gd_t));
74 memset(bd, 0, sizeof(bd_t));
75 gd->bd = bd;
76 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
77 bd->bi_memsize = CONFIG_SYS_L3_SIZE;
78
Simon Glasscbcbf712017-01-23 13:31:22 -070079 arch_cpu_init();
Chunhe Lan373762c2015-03-20 17:08:54 +080080 get_clocks();
81 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
82 CONFIG_SPL_RELOC_MALLOC_SIZE);
Sumit Garged4708a2016-05-25 12:41:48 -040083 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
Chunhe Lan373762c2015-03-20 17:08:54 +080084
85 mmc_initialize(bd);
86 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
Tom Rinia09fea12019-11-18 20:02:10 -050087 (uchar *)SPL_ENV_ADDR);
Chunhe Lan373762c2015-03-20 17:08:54 +080088
Tom Rinia09fea12019-11-18 20:02:10 -050089 gd->env_addr = (ulong)(SPL_ENV_ADDR);
Simon Glass203e94f2017-08-03 12:21:56 -060090 gd->env_valid = ENV_VALID;
Chunhe Lan373762c2015-03-20 17:08:54 +080091
92 i2c_init_all();
93
Simon Glassf1683aa2017-04-06 12:47:05 -060094 dram_init();
Chunhe Lan373762c2015-03-20 17:08:54 +080095
96 mmc_boot();
97}